GB2530494A

GB2530494A - An undervoltage-lockout circuit

Info

Publication number: GB2530494A
Application number: GB1416595.5A
Authority: GB
Inventors: Frank Warnes
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2014-09-19
Filing date: 2014-09-19
Publication date: 2016-03-30
Anticipated expiration: 2034-09-19
Also published as: GB2530494B; GB201416595D0

Abstract

A DC to DC converter 200 has a combined start-up and undervoltage lockout circuit (UVLC) 201 connected to a switching circuit 202. The UVLC controls the switching circuit so that a start-up operation is prevented until the voltage of the power rail has risen above a start-up voltage. Once operation has begun, the switching circuit is turned off when the voltage falls below a undervoltage lockout threshold voltage. The undervoltage lockout threshold voltage is lower than the start-up voltage, so there is hysteresis in the control of the switching circuit. The converter comprises a power input terminal and a power output terminal with a primary transformer winding P1 connected to the input terminal and a secondary transformer winding S1 connected to the output terminal. The switching circuit is implemented using a switching MOSFET TR1 and a PWM controller U1, where the switch controller controls the switch to supply a periodic signal to energise the primary transformer coil. The undervoltage lockout circuit comprises a voltage sense and control circuit and a hysteresis circuit.

Description

I

AN UNDERVOLTAGE-LOCKOUT CIRCUIT

The application relates to a power converter, and in particular to a power converter having an undervoltage lockout circuit for controlling power switching.

In a DC to DC convortor, the primary w nding of the Lransformei cod is switched by a switching circuit to set up an alternating magnetic field which threads a secondary winding of the transformer coil. An output stage drcuit connected to the secondary winding regulates and smoothes the voltage signal from the secondary winding to provide a regulated DC voltage at the output. The switching circuit requires a voltage input above a minimum value to contro the switching reliably and to provide sufficient power to the primary side winding If a sufficient input voltage is not required the operation of the switch and transformer cannot be carried out correctly, leading to undesirable power dissipation in the transformer windings.

Many DC to DC converters therefore include an under-voltage lockout feature. This ensures that at input voltages that are not sufficiently high operation of the switching circuit is disabled Low cost DC to DC power converters are often discrete self-oscillating converters or are designed around low cost Pulse Width Modulation (PWM) controllers These power supplies generally have no under voltage lockout feature, meaning that they may not be suitably controlled when the power supply voltage received at their input is insufficient.

We have therefore appreciated that it would be desirable to provide a low cost underioltage lockout circuit for a DC to DC converter.

SUMMARY OF THE INVENTION

The invention is defined in the independent claims to which reference should now be made, Advantageous features are set forth in the dependent claims.

According to a first aspect of the invention, there is provided a DC to DC converter having a power input terminal and a power output terminal, a primary transformer coil connected to the power input terminal, and a secondary transformer coil connected to the power output terminal, a switching circuit having a swtch and a switch controller the switch controller controlling the switch to supply a periodic signal to energise the primary transformer coil; a undervoltage lockout circuit having an output connected to the switching controller, a voltage sense and control circuit, and a hysteresis circuit the undervoltage lock out circuit receiving a power supply voltage at an input; wherein the voltage sense and control circuit supples a first activation signal to the switch controller and a second activation signal to the hysteresis circuit when an rising input voltage received from the power supply at start-up of the converter is detected to exceed a start-up voltage threshold; a hysteresis circuit, coupled to the voltage sense and control circuit, which is activated by the second activation signal to modify the voltage being sensed by the voltage sense and control circuit to establish an under voltage lockout threshold; the undervoltage lockout threshold controlling shut-down of the device when the voltage received from the power supply is falling and is detected by the voltage sense and control circuit as faDing below the undervoltage lockout threshold: wherein the undervoltage lockout threshold is lower than the start-up voltage threshold.

The voltage sense and control circuit may comprise: a comparator having a non-inverting input and an inverting input, a positive power supply input terminal and a negative power supply input terminal, the non-invertng input connected to the power supply voltage and the inverting input receiving a reference voltage signal, the output of the comparator connected to the switch controller to provide the first activation signal, and connected to he non-inverting input via a feedback path to provide a positive feedback signal at the non-inverting input.

The hysteresis circur compnses a resistance element in the feedback path The resistance element may comprise a resistor and a diode.

1 he converter may corn pr'se a voitage divider arranged between the high voltage input power line and the low voltage power line, wherein the voltage at the intermediate point between in the divider is used to supply a voltage signal to the positive power supply terminal of the comparator, and the reference voltage signal to the inverting input.

In the converter, the reference voltage signal is set by a voltage divider arranged between the positive power supply terminal of the comparator and the low voltage rail. The voltage divider may be a precision shunt regulator comprising a resistor and a diode.

In an alternative embodiment, the voltage sense and control circuit comorises a first transistor having its emitter coupled to the high voltage power line, its base coupled to the low voltage power line via a further resistance element placed in series between the base the low voltage line, and its collector coupled in series with the hysteresis circuit The further resistance element may comprise at least a first reverse-biased Zener diode.

The hysteresis circuit may comprise a second transistor with its base coupled to the collector, which when activated switches out part of the further resistance element increasing the current nto the base of the first transistor In embodiments of the invention, the switch controller may be a PWM (Pulse Width Modulator) controller.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described by way of example only and with reference to the drawings in which: Figure 1 is an illustration of a prior art DC to DC converter Figure 2 is an illustration of a first embodiment of the invention; Figure 3 is an illustration of the relevant current and voltage waveforms for the first example embodiment of the invention, Figure 4 is an illustration of a second embodiment of the invention; and Figure 5 is an illustration of the relevant current and voltage waveforms for the first example embodiment of the invention.

DETAILED DESCR'PTION OF EXAMPLE EMBODIMENTS Figure 1 illustrates a known DC to DC converter 100. For the purposes of illustration, a flyback converter is shown, but other topologies of converter, such as a forward converter, would also be acceptable for use in such a ctrcuit The converter accepts an input voltage Vin relative to the OV rail at the input terminal INPUT. The remaining circuitry is, for the purposes of description divided into two sections switching circuitry 102 and convertor circutry 104 The input voltage yin received at the INPUT terminal is switched across the converter circuitry 104 by switching circuitry 1 02. In figure 1, the switching circuitry comprises a Metal Oxide Field Effect Transistor MOSFET) TR1 which is controlled to either be in a cnnducting or non-conducting state As wdl be appreciated by the skilled person, when the transistor TRI in switching circuftry 102 is conducting, the input voltage Vin is applied across the primary windings RI of a transformer TXI in converter circuitry 104 and energy is thereby stored in the transformer in the resulting magnetic field. When the transistor TR1 in switching circuitry 102 is non-conducting, a current is allowed to flow through the secondary windings SI of the transformer TX1 and results in a converted DC voltage being applied between the OUTPUT and RETURN terminals. The converted voltage may then be used to supply br example, transistors in switched-mode power supplies or power electronics devices.

Switching circuitry 102 includes a Pulse Width Modulation (PWM) controller UI which is used to provide a switching signal to the primary windings P1 via MOSFET TR1 As is known in the art, a PWM controller of this kind, may be provided as part of an integrated circuit (IC) TR1 is the primary side switching MOSFET and is responsble for switching the input voltage yin across the primary windings P1 of the transformer TX1 in response to signals output by the PWM controller. The drain of TRI is connected to the primary windings P1 and the source is connected to the DV (ground) power rail, T as Hustratec is ar Enhancement-mode N-channel MOSFET, although othertransistor types can be used.

Converter circtry 104 comprises a flyback transformer TX1 haVing primary windings RI and secondarywindingsSi. The primaryand secondarywindings P1 and Si are wound around a transformer core, for example one made of laminated soft iron. In alternative rrangements it is possible to use other materials for the core, or the core may be absent in which case the wirdings are air-cored. The transformer of figure 1 is isolated but a non-isolated transformer arrangement without this feedback could equally well be used Diode Di and capacitor 03 are the respective output components for the output side The PWM controller Ui illustrated in figure 1 will now be described in more detail. In this example, the PWM controller is provided as an integrated circuit. As will be appreciated by the skifled person, other PWM controllers could be used. The integrated circuit Ui has a number of input terminals or pins that connect to its interior circuitry.

UVLO pn is a Under Voitage Loc'cout Pin, and is used to detect when the votage Vin received at the input terminal is insufficient to reliably operate the controller UI and switching transistor TR1. The input terminal INPUT is fed to the UVLO pin by a voltage civider arrangement oompnsing resistors R2 and R3 connected in series between the high voltage line and DV line. The UVLO pin and the associated internal circuitry in the controller Ui, therefore control the start-up of the device when the voltage Vin exceeds a start-up voltage threshold, and the shut-down when the voltage yin falls below a minimum operational value or shut-down voltage.

The input terminal INPUT or high voltage rail (Vir,) also connects to the Enable and Synchronisation terminal (EN/SYNC) of the PWM controller via series resistor R5 R6 together with diode Dli also form a voftage divider arrangement R3 connected in series between the high voltage line and OV line.

Transistor Q2 also controls the activation of the PWM controller by regulating s connection to the input power line. The Input voltage pin Vin of the PWM Controller is connected to the emitter of transistor 02, while the collector of transistor 02 connects to the high voltage line. The base of the transistor 02 is connected to the midpoint of the voltage divider comprising EQ and R3.

The IC shown has a Gate!Dnve (3&) termInal which connects to the gate of MOSFET TR1. The ground pin (Gnd) is connected directly to ground.

The driving voltage pin Vdr), the current sense input pin (lens), the Vfb pin for output voltage feedback, and the Vc pin which provides an output from the internal voltage error amplifier of the PWM controfler may be connected to further anciHary circuit components, but for simplicity these are riot shown in the diagram. It wifi be appreciated that other IC circuits that may oo usec as WM controllers may have these or different input pins for control and sensing and output.

S As is known in the art, the PWM controller is used to provide a switch signal that controls the energising of the primary coiL During the on cycle of the switching signal, the primary coil of the transformer is connected to the power supply, and the primary transformer is energised as the current and the magnetic flux increase The diode Dl blocks current flow in the secondary coil, and the capacitor discharges to the load. During the off cycle, the primary coil is disconnected, and the current and flux dissipate, causing current slow in the secondary coil to charge the capacitor and supply an output to the load As noted above, the UVLQ pin and the associated internal circuitry in the controfler Ui control the start-up of the device when the voltage Vin exceeds a start-ip voltage threshold, and the shut-down when the voltage Vin falis below a minimum operational value or shut-down voltage. However, such devices having an internal UVL.O function tend to be costly We have appreciated that it would be desirable to provide a low cost undervoltage lockout circuit for a DC to DC converter.

Embodiments of the invention will now be described comprising an undeivoltage lockout circuit UVLC) coupled externally to the PWM controller Ui. A first embodiment is illustrated in Figure 2.

Embodiment 1 A first embodiment of the invention will now be described with reference to Figure 2.

This embodiment comprises a converter 200 having a combined start-up and undervoltage lockout circuit (UVLC) 201 connected to switching circut 202 As MD be described below, the UVLC 201 controls the Switching Circuit 202, so that at start-up operation is prevented until the voltage of the power rail has nsen above a prescribed minimum, herein referred to as the start-up voltage and once operation has begun the switching circuit is turned off when the voltage falls below a minimum operating threshold, herein referred to as an undervoltage lockout threshold or shut-down voltage. The under-voltage is set to be lower than the start-up voltage, so that there is hysteresis in the control of the switching circuit, and as a result, the switching circuit can transition from its activated state to its deactivated state (and vice versa) in a stable manner As before, Switching Circuit 202 is implemented using a switching MOSFET TR1 and a PWM Controller Ui. The drain terminal of the MOSFET TR1 connects to one side of the primary transformer winding P1, while the source of MOSFET TRI connects to the OV voltage rail. As is known in the art, the operation of the switching MOSFET TRI is contro fled by signal output from the PWM controller. SpecificaHy, the Gate Drive terminal (Gdr) of the PWM Controller UI is connected to the gate of the switching MOSFET TR1, so that the MOSFET TR1 can be switched on and off as desired to control the energising of the primary coil P1 The ground terminal of the PWM Controllw Ulis connected to the low voltage rail (OV).

As shown, in Figure 2,the UVLC comprises resistors RI, R5, R8, R9 and R15, Zener Diodes D3 and Dli Transistors 01 07 and 03, and standard Diode 012 Transistor 01 serves as a voltage sense and control transistor and in this example is provided as a PNP transistor. Transistors 02 and 03 are provided as NPN transistors n this example Transistor 02 serves as a switched linear regulator supplying a high voltage signal to the PWM Controller. Transistor 03 serves as a latch transistor, for forcing the voltage sense and control transistor 01 into hard ON and hard OFF modes, while providing a hysteresis function for the control of the swftching circuit 202.

The circuit has two output nodes ON1 and 0N2 connected to the Switching Circuit 202 The EN/Sync terminal of the PWM controller Ui is connected to the output node ON1 of the UVLC, so that the Enable function of the PWM controller UI can be controlled by a first activation signal output from UVLC 201. Additionally, the Vin terminal of the PWM Controller Ui is connected to the emitter of the UVLC transistor 02 via output node 0N2 Output node 2 supplies a second activation signal to the PWM controller to turn it on. The other terminals of the PWM controller may be connected to further components, but for simplicity these are not shown in the diagram. The other terminals may include: lens "Current Sense Input", Vdrv Driving Voltage, Vc output of the voltage error amplifier, and VFB output voltage feedback for example.

The L#VLC 1 receives an -i-V input from a high voftage input line a' input terminal INPUT and a zero volt (0V or ground signal at the low voltage input OV. Transistors 01 and 03 are responsible for controlling the start-up and shut-down of the PWM controller UI at tie desired start-up oltaqe ano urdervoltage, thereby providing an undervoltage lockout function that avoids operation of the controller and switching circuit when the voltage from the high voltage input line is not sufficient. Furthermore, as will be discussed, the operation of Qi and 03 provide for hysteresis in the start-up and shut-down functions, so that the switch over between on and off states of the device is stable, even accounting for supply voltages with ripple or noise The configuration and operation of the transistors QI and 03 will now be described in more detail.

Transistor 01 is connected in a first shunt regulator arrangement between the input and the ground voltage rails. The emitter of transistor 01 is connected to the high voltage Une, whlle the collector is connected to a voltage divider arrangement made up of resistors P9 and Ri 5 in series. The collector of 01 is connected direcfly to resistor P9, white RI 5 is connected to the OV raiL The base of transistor 01 is further connected to a second shunt regulator arrangement provided between the input and the ground voltage rails.

The second shunt regulator compnses resistor P1, Zener diode D3 resistor RB, and standard diode D12 connected in series between the high voltage hne, and the ow voltage line, in the order described. Resistor Ri is provided at the high voltage end of the shunt, Zener diooe 1)3 is reverse biased, and standard diode 12 is forward biased [he base of transistor Oils connected between the Zener diode 03 and the resistor Ri. 01, P9 and P15 are therefore in parallel with Ri, D3, RB and D12.

The collector and emitter terminals of transistor 03 are connected in parallel across standard diode 012, while the base of transistor 03 is connected to an intermediate point between the voltage divider provided by resistors P9 and Ri 5 The emitter of transistor 03 is connected the QV rail, while the collector of transistor 03 is connected to a point intermediate resistor RB and diode D12.

Resistor R5 and Zener diode Dli are connected in series with the collector of transistor 01, in parallel to the resistor R9 and Ri 5, and form an output stage of the UVLC 201 for connection to the PWM Controller UI. Zener diode DII is reverse biased. Output node ON1 is provided intermediate the resistor R5 and the Zener diode Dli and is connected to the EN/Sync terminal of the PWM Controller U 1.

Transistor 02 controls the actvation of the PWM controller bi regulating its connection to the input power hne. The Input voltage pin yin of the PWM Controller is connected to the emitter of transistor 02 via output node 0N2 of the UVLC 201, while the collector of transistor Q2 connects to the high voltage line. The base of the transistor Q2 is connected to the output node ONI of the 201 crcuit The start-up and shut-down operations of the circuit will now be described in more detail.

Start-up During start-up of the DC-DC coneerter, the high voltage rai1 is connected to the power supply and goes live with a quickly rising voltage. The start-up voltage of the UVLC 201 is the input voltage V4-at which the transistor 01 turns on.

In th1s example, as 01 is a °NP transistor, the emitter and base JLnctions are forward biased due to the presence of resistor Ri which lowers the base terminal voltage reDative to the emitter. When the emitter to base voltage drop Vbe of 01 is about 0.6 to 0.7V, the base-emitter diode junction of the transistor will turn on, and the transistor 01

B

begins to operate in its active rode Current therefore flows from the ccl ector of QI to re&stors R9 and R5, and to the base terminal of NPN transistor 03. As 4Il be explained below, the relationship between the base-emitter voltage Vhe and the voltage (+V) received at the input terminal is controlled by the presence of Zener diode D3 and forward diode D12 For example, a start-up voltage of 8V can be set by using a 6 8V Zener diode The start-up voltage for the switching circuit is then given as: VstartupV) = VD3 + Vbe + VD12 Where Vbe is the voltage drop across the base and emitter of the transistor, VD3 is the voftaqe drop across the Zener diode, and V012 is the voltage dron across the forward diode. A start-up voltage of SV would result from: Vsrt.LIp (+V) = 6.BV + 0.6V + 0.6V = SV RB does not factor w'to the above equation, because until the Zener diode begins to conduct there is no current through the resistor. The value of resistor R8 is chosen to limit the current at maximum input voltage. It provides a voltage drop that increases finearly from DV (for an BV input at the Input terminal) to a value of Vinjiiax minus BV (for a maximum input voltage! Vinmax).

Once, transistor 01 tums on, the current flowing through resistor R9 flows Into the base of transistor 03 which causes it to turn on also. Transistor 03 is shown as an NPN transistor, and the base-emitter iunction of transistor 03 is therefore forward biased. The collector emitter junction of transistor 03 is connected in parallel with the standard diode 012, and is also forwait biased so that the tiansistot 03 is driven into saturation The collector voltage of the transistor 03 saturates to a lower voltage than the forward biased diode, and the current into the base of the transistor 01 is therefore increased The reduction is around 0 6V as the forward voltage of the diode 012 is effectively switched out by transistor 03.

Again for the example of an BV undervoltage circuit, the shut down voltage VshutdQ (+V) at the input of transistor 01 is now determined as follows: = V03 ÷ Vbe ÷ VsatQ3 Where V8hUt0Wfl is the voltage at the input of the transistor, Vbe is the voltage drop across the base and emitter junction of the transistor, VD3 is the voltage drop across the Zoner diode, and VsatQ3 is the collector-emitter saturation voltage of Q3. So for example: VShUtdUWfl = 6.8V+ 0.SV ÷ 0.02V = 7.42V This value sets the shut-down or under voltage for the circuit In other words, if the voltage +V at the input were now to fall below 7 42V (not 8V as before), the voltage at the base terminal of 01 would not be sufficient to provide a voltage drop of 0.6V across the base-emitter junction and 01 will turn off.

After start-up however, the reduction in voltage seen at the base terminal of transistor 01 means that the base voltage of 01 is lower than the voltage Ve at its emitter terminal, forward biasing the base-coRector junction and causing 01 to saturate to a hard ON state.

When the transistor 01 is saturated, the coUector current from transistor 01 that flows to the output stage resistor R5 and into Zener diode Dli, is sufficient to activate the PWM Control'er Ui via output node OF'41 and so series as a f rat activation signal for turning on the switching controller. In this embodiment, the current flowing into the output stage comprising resistor R5 and Zener diode Dli, causes the diode Dii to regulate to a voltage level of about 5 1V, whith is suitable to act as TTL logic signal for the controler Ui A 1 OKO resistor and a 51V Zener diode may be used to achieve this. As will be understood by the person skilled in the art, TTL signals are transistor-transistor logic' level signals, recognised by devices comprised of BJTs Depending on the configuration of the PWM controller, in other embodiments, different logic level signals such as CMOS, and ECL Emiller Coupled Logic Devices) logic may be used.

The voltage output at node ON1 is also provided as a base bias voltage to an NPN transistor 02, which acts as a linear regulator providing a higher current input voltage to power the yin pin of Ui The TTL enables gnal provided to the power controller is useful where an auxiliary voltage is used to crow bar the yin pin of UI (not shown in Figure 1).

Without it the power supply would not power off at the under voltage lockout threshold, as it would remain connected to the auxiliary supply.

Shut-down On shut-down of the device, the high voltage rail is assumed to be disconnected from the power supply. As the voltage at the input (+V) falls below the V,hut4on value, (742V in the above example) the current in the base-emitter junction of 01 will quickly reduce. in turn shutting off the current supplied from the coflector of 01 to the transistor 03.

The current flawing into the base emitter of 03 therefore reduces and the base voltage at 03 falls, quickly bringing the transistor Q3 out of saturation and turning it OFF, As the transistor 03 turns OFF, the forward diode Dl 2 is effectively reintroduced or switched back into the potential divider connected to the base of transistor 01 that forms the start-up voltage setting circuit, causing the current into the base of 01 to fall. The voltage drop across the base emitter-junction of 01 is now no longer sufficient for conduction and 01 turns hard OFF.

The start-up voltage is one of two threshold voltages set by the electroncs The other is the shut-down or under-voltage lockout threshold. The start-up voltage is the minimum voltage roquirod by the npu stages for the device to turn on, and adopt a stable mode of operation S milarly, the undervoltage lock out voltage is a shut-down voltage below which the device is quickly powered off. Both voltages are detected in this embodiment by the voltage sense and control transistor Qi in combination with the further resistance element comprising at Feast 03 and D12 The voltage sense and conttl circuit when activated sends a first activation signal to the PWM controller causing it to turn on. At the same time, a second actrvatton signai is sent to the transistor 03 (acting as a hysteresis circuit) causing it to switch out part of the further resistance element, increase the current into the base of 01 and therefore reduce the threshold sensed by the voltage sense and control transistor 01 By using the combination of the transistors Qi and 03 both of these voltage thresholds can be set by the same electronic components.

The operation of the device will now be explained in more detail and with reference to Figure 3 Figure 3A shows the voltage siqnal received at the input power line rising with time, peaking at time t=tmaxl remaining constant until t=tmax2, and subsequently decreasing This pattern of input votage is purely to iflustrate the switchng off of the device, The second and third graphs, Figures 3B and 3C, show the base current at the intermediate point between diode 03 and resistor Ri, and the coflector current for the transistor 01. These signals act as sense signals for determining the timing of the output or control signals in the fourth to sixth gtaphs Figures 3D to 31-Figures 3D, 3E and 3F show respectively the control signal output from transistor 01 to trigger the startup and shutdown of the device, the control signal output to the En/SYNC pin of the controller UI via output terminal ONI, and the control signal output to the yin pin of the controller Ui via output terminal 0N2.

At time t=t0, the input voltage is low, and insufficient to operate the switching circuit, which is locked out of operation. The input voltage continues to rise, until at time t4or., the input voltage received at the input terminal rises above the BV start-up threshold set by the undervoltage lockout circuit. At this time, the start-up function of the undervoltage lockout circuit is activated, and a first activation signal is output from the undervoltage lockout circuit to the EN/Sync pin of the PWM Controler UI This s shown in the fFfth graph by the output at the first output terminal ONI switching at time t=t0frcm an initial value of OV to a high value of 5V. At the same time, a second activation signal is output from the second output terminal 0N2 to the base of 02. This is shown in the sixth graph, which at time ttor switches from an initial value of OV to a high value of 4.4V. As discussed above, the effect of the second activation signal is to supply power to the yin terminal of the PWM Controller and turn on the device, while the effect of the first activation signal is to initiate the PWM Controller oscillator and switching function It will be appreciated that the first acfivation signal could be applred at the same time as the second activation or shghtly later The first and second activation signals are dependent on voltage signal at the coilector of transistor 01. As is shown in Figure 3D, until time t=t01, the emitter to base voltage drop Vbe of transistor 01 is insufficient to turn the transistor on. However, once the emitter to base voltage drop Vbe reaches about 06V to OJV the transistor 01 turns ON and current flows from the collector to resistors R9 and R5, the voltage at the collector of transistor 01 therefore quickly jumps to the value of the input voltage on the input line, and subsequently continues to rise with the increasing input voltage. The reference diode DII however fixes the voltage at the output terminal ON1 to a reference voltage of by.

Consequently as shown in Figures 3E and 3F, the voltage at ONI umps almost instantaneously to the reference value of 5V to provide the first activation signal, while the voltage value at 0N2 jumps almost instantaneously to around 4.4V (the 5V set by the reference diode Dli combined with a dioce drop across transistor 02) to provide the second activation signal, which then remain constant with increasing input voltage. The increasing voltage at the collector of transistor 01 is therefore dropped across the resistor Rb.

Figure 3B shows the current through the reverse biased Zoner diode D3 connected to the base of transstor 01 In this example, diode D3 has a Zener voltage of 6 SV Just prior to time t=t, (at time t=t03 the leakage current through the Zener diode is shown as being non-zero, until at time t=t0 a voltage of 6.SV breakdown occurs and the Zener current begins to increase with increasing voltage. As noted above, the circuit construction ensures that a 6W voltage drop across the Zener diode is reached when the voltage at the input reaches By.

Figure SC shows the collector voltage at the transistor 03. As this is connected across diode D12, this rises to around 500mV as that diode begins to conduct. At time t=t0 as transistor Qi turns on and current flows into the collector of transistor 03, the voltage drops to a minimum.

As shown on the right hand side of Agure 3, after time t=trriax2, tho input voltage begins to decrease, until at time t=t the voltage falls to a value of 742V. At this voltage., the transistor 03 comes out of saturation and turns off. This switches the diode D12 back into the detection part of the stal-up circuit, resetting the detected voltage threshold to the higher value of By. In practice, the voltage provided at the collector of 01, and so to the output nodes ONI and 0N2 connected to the Enable Pin (EN) and the Vn pin begins to fall slightly before t=t,w This is because the transistor 03 has a low voltaqe turn off threshold and does not turn off until 0N41 and 0142 are already Ialiing.

Embodiment 2 A second embodiment of the invention will now be described with reference to Figure 4.

This embodiment also comprises a combined start-up and under voltage lock out circuit (UVLC) 401 connected to switching circuit 402. As will be described below, the UVLC 401 controls the switching circui' 402, so that at start-up operation is prevented until the voltage of the power rail has risen above a prescribed minimum, herein referred to as the start-up voltage, and once operation has begun, the switching circuit is turned off when the voltage fa1ls below a minirrum operating threshold, herein referred to as an under-voltage. The under-voltage is to be lowerthan the start-up voltage, so that there is hysteresis in the control of the switching circuit, and as a result, the switching circuit can transition from its activated state to its deactivated state (and vice versa) in a stable manner.

As before, switching circuit 402 is implemented using a switching MOSFET TRI and a PWM Controller Ui, The drain terminal of the MOSFET TR1 connects to one side of the primary transformer winding P1, while the source of MOSFET TRI connects to the OV voltage rail As F5 known in the art, the operation of the switching MOSFET TR1 is controlled by signal output from the PWM Controller. Specifically, the Gate Drive terminal Gdr of the PWM Controller UI is connected to the gate of the switching MOSFET TR1, so that the MOSFET TR1 can be switched on and off as desired to control the energising of the primary coil P1 -The ground terminal of the PWM Controller Ui is connected to the low voltage rail (OV).

In this embodiment, the under-voltage lockout circuit UVLC 401 comprises a comparator circuit Xl, used instead of the voltage sense and control transistor 01 and latch and hysteresis transistor 03.

As before transistor 02 is an NPN transistor serving as a switched linear regulator supplying a high voltage signal to the PWM Controller. The Input voltage pin Vin of the PWM Controller is connected to the emitter of transistor 02, while the collector of transistor Q2 connects to the high voltage line. The base of the transistor 02 is connected to the output node of the UVLC2 circuit.

The circuit has two output nodes ON1 and 0N2 connected to the Switching Circuit 202 The UV[ C7 receives an +V input from a high voltage input line at input terminal lNi and a zero volt (OV) or ground signal at input terminal INPUT.

The EN/Sync terminal of the PWM controller Ui is connected to the output node ON1 of the UVLC. The Enable functions of the PWM controller Ui can therefore be controlled by the first activation signal output from the UVLC 201 as before. Additionally, the Vin terminal of the PWM Controller Ui is connected to the emitter of the UVLC transistor 02 via output node 0N2. As will be appreciated the other terminals may be connected to ancillary circuits or components (not shown). Other terminals may include: lsns Current Sense Input, Vdrv Driving Voltage, V output of tho voltage error aniplther and Vfb output voltage feedback for example. As is known in the art, the comparator circuit Xl comprises a non inverting input terminal (s), an inverting input terminal (-) an cutout terminal a positive power supply terminal and a negative power supply terminal The precision shunt regulator provides a reference voltage (2.5V in this example) at the inverting input of the comparator circuit Xl, and a regulated power supply to the positive power supply terminal The precision shunt regulator comprises resistors Ri, P4, and PS, precision reference diode D2, and capacitor CI Resistor RI and precision reference diode D2 are connected in series between the inputs terminal INPUT and the OV or ground line. Precision reference diode D2 is in a reverse biased configuration. During start-up the voltage drop across precision reference D2 is biased to 5V by the current flowing through Ri. The voltage at the branch node point A isthereforesetto5V.

Potential Divider circuit comprising resistors R4 and R5 in series is connected between the branch node point A and the OV rail The intermediate point between the resistors P4 and PS is connected to the inverting input terminal of the comparator Xl. As the resistors are equal in magnitude a reference voltage of 2,5V is applied to the inverting irput of the comparator XI ny the potental divider P4 and R5 The negative power supply terminal of the comparator is connected to the OV rail, while the positive power supply input terminal of the comparator is connected to the branch node A output of the divider formed by resistor R 1 and D2 A power supply of 5V is therefore supplied to the comparatorXl.

Gapacitor Cl is provided in parallel with precision reference diode 02, coupled between the OV rail arid the output branch node A between precision reference diode D2 and resistor Ri.

A voltage sense and control circuit is therefore formed by a voltage dMder circuit, comprising resistors R2 and R3 connected in series with each other between the high voltage and the low voltage rails, and the comparator Xl. Resistors R2 and R3 are connected in series between high voitage rail and OV rail. The output of the voltage dMder circuit, the ntermedate point between the resistors R4 and R5, is connected to the non-inverting input terminal of the comparator Xl.

The output of the comparator is connected to output ON1 at which the ENlJSync terminal of the PWM Controller Ui is connected, and to the base of the transistor Q2. Via intermediate branch point B, the output of the comparator is also connected via resistor R6 and standard forward diode 03 to the intermediate point between the resistors R2 and R3, and thereby to the non-inverting input terminal of the comparator. This branch provides a positive feedback signal between the output and the non-inverting input, and therefore configures the:omparator o operate as a Schmidt trigger In trus example, the positive feedback path comprising diode 03 and resistor R6, and the comparator Xl, form the hysteresis circuit.

Start-up During start-up of the DC to DC converter, the high voltage rail is connected to the power supply and goes live with a quickFy rising voltage.

The start-up voltage is determined by the potential divider R2 and R3 applied to the non-inverting terminal of the comparator, as follows: Vrtup= VRa (1 + R21 R3) Where VSthUQ is the desired voltage i+V) at the input line at which the PWM controller is activated, VRS is the voLtage drop across resistor R3, and R2 and R3 are the resistors referred to above. The voltage on resistor R3 is given by: V3 = [VD2*R4] I jR4 + Rb] As before a start-up voltage of BV can be set by using resistor and diode values as follows: (D2) = 5V reference diode, R4 and R5 = IQOkO resistors, R2 = 50k() resistor, R3 = 251<0 resistor. Then, VR3 = [5 1Q0,000J! [100,000 ÷ 100,000] = 2.5V = 2.5 (1 ÷ 55000/ 25000) = SV When the start-up voltage is reached and the voltage sensed at the non-inverting pin, exceeds the reference voltage received at the inverting input, the output of the comparator is driven high by the positive feedback loop, to 5V, the maximum set by the input power supply terminal This provides a TTL voltage signal to EN/Sync pin of the PWM Controller UI.

The output is also received at the base terminal of the transistor 02, which acts as a hrear regulator between the high voftage line connected to input terrnina' l'%ll and the Vin terminal of the PWM controller. As a result, a higher current input voltage to the power the Vin pin of the PWM Controller.

At the same tine a small current flows through resisto R6 and diode D3 which raises the voltage on the non-inverting terminal further. The resistor is chosen so that the value of the current feedback is only small 1-us means that the switch of the comparator to the high voltage is reinforced, and maintained in view of fluctuations in the power supply.

The rise in voltage at the non-inverting terminal also means that once the output of the comparror goes high, the input voltage received at the input has to fail further (by the same amount as the rise due to the positive feedback) for the comparator to detect that the input has fallen below the reference voltage, and to turn off the output. This provides a controllable hysteresis to discnminate against input rpple noise whic-i would normaily cause the circuit to turn on and off intermittently.

The shutdown voltage for the circuit is therefore given by the following expression: = VR3 + R2 ((VR3 / R4) -(V02 -VR3 -V03) / R6) where VR3 = ( VD. R4) / (R4 + R5) As before when using resistor and diode values as follows: (D2) = 5V precision reference diode, R4 and R5 = 100kG resistors, R2 = 50kG resistor, R3 = 25kG resistor R6 = 150kG resistor, and V (forward voltage drop of D3). Then, VR3=(5. 100,000)/(100,000+ 100000)= 25V V3hUt40= 2.5 + 55000 (2.5f25000)-(5-2.5-0.6i 150000)= 7.3V Hysteresis can therefore be provided over a range of values by adjusting the value of R6,

S

S hut-down Thus, on shut-down of the device, the high voftage rail is assumed to be disconnected from the power supply. The voltage at the non-inverting terminal therefore fails, and subsequently drops below the reference value received at the inverting input.

As a result, the output of the comparator reverts to a low signal, and the enabling signal provided to the ENISync input terminal of the PWM controller UI is discontinued.

When the comparator reference voltage is crossed, the feedback s grial to the non-inverting is also disabled, meaning that the small positive contribution to the input voltage at the non-inverting terminal is also disabled, resetting the start-up voltage to the lower level.

The operation of the device will now be explained in more detail and with reference to FigureS As before, Figure SA shows the voltage signal received at the input power line rising with time, peaking at time t=tmaxt remaining constant until ttmax2, and subsequently decreasing. This pattern of input voltage is purely to illustrate the switching off of the devLce As before the time correspording to the start-up and shut-down of the control circuit (t=t0 and t=t0ff respectively are illustrated). The second graph, Figure SB, shows the voltage at the intermediate point between the reference diode 02 and resistor Ri As 02 is a preosion voltage reference dade this quickly goes high with increasing input voltage to its reference value of SV to serve as a power supply for the comparator Xi 2 and the connected voltage divider arrangements.

Figures SC and SD shows the inputs at the non-inverting and inverting input terminals of comparator X1. As shown in Figure SD, The voltage provided at the inverting input of comparator Xi quickly goes high to a steady state value of 2.5V at which it serves as a detection threshold for the comparator Xl In Figure SC, a portion of the input voltage fed back from the auxiliary winding is illustrated determined by the potential divider formed by R2 and R3.. At time t=t0 this signal exceeds the reference voltage received at the inverting inpu' and drives the output of the comparator Xi high to its 5V power rail As noted above, at this time a small current flows back through the resistor R6 and diode D3 raising the signal at the non-inverting pin a little further, and providing hysteresis to discriminate against ripple noise in the circuit. At shutdown, the removal of the feedback I-f signal is illustrated at time t=t when the voltage suppUed at the noninvorting input falls below the reference voltage of 2.5V rec&ved at the inverting input.

Figures 5E and 5F respectivey show the control signs output from output nodes ONI and 0N2 provided to the EN/SYNC pin of the controRer UI and the yin pin of the controflerUl.

The embodiments described therefore provide an under vottage lockout circuit with hysteresis, that consists of low cost components and which takes up very little board space Example embodiments of the invention have been described for the purposes of itlustraion only, and are not intended to limit the scope of the invention as defined by the following claims Moditicators and variations within the scope of the claims will be apparent to the skilled person.

Claims

CLAIMS1. A DC to DC converter having a power input terminal and a power output terminal, a primary transformer coil connected to the power input terminal, and a secondary 6 transformer coil connected to the power output terminal; a switching circuit having a switch and a sw tch controHer the switch controler controlling the switch to supply a periodic signal to energise the primary transformer coil; a uridervoltage lockout circuit having an output cornected to the switching controller, a voltage sense and control circuit, and a hysteresis circuit, the undervoltage lock out circuit receiving a power supply voltage at an input; wherein the voltage sense and control circuit supplies a first activation signal to the switch controller and a second activation signal to the hysteresis circuit when a rising input voltage received from the power supply at start-up of the DC to DC converter is determined to exceed a start-up voltage threshold; a hysteresis cimuit, coupled to the voltage sense and control circuit, which is activated by the second activation signal to modify the voltage being sensed by the voltage sense and control crcuit to estab'ish an undervoltage ockout threshold, the undervoltage lockout threshold controfling shut-down of the device when the voltage received from the power supply is detected by the voltage sense and control circuit as falling below the undervoltage lockout thresbch wherein thc undervoltage lockout threshold is lower than the start-up voltage threshold.
2 The converter o claim 1, wherein the voltage sense and control circuit compnses a comparator having a non-inverting input and an inverting input, a positive power supply input terminal and a negative power supply input terminal; the non-inverting input connected to the power supply voltage, and the inverting input receiving a reference voltage signaL the output of the comparator connected to the switch crtroller to provide the first activation signal, and connected to the non-inverting input via a feedback path to provide a positive feedback signal at the non-inverting input
3. The converter of claim 2, wherein the hysteresis circuit comprises a resistance element in the feedback path.
4. The converter of claim 2, wherein the resistance element comprises a resistor and a diode.
5. The converter of any of claims 2 to 4, comprising a voltage divider arranged between the high voltage input power line and the low voltage power line, wherein the voltage at the intermediate point between in the divider is used to supply a voltage signal to the positive power supply terrrnnal of the comparator, and the reference voltage signal to the inverting input.6 The converter of claim 5, wherein the reference voltage signal is set by a voltage divider arranged between the positive power supply terminal of the comparator and the low voltage rail.7. The converter of claim 5 or6, wherein the voltage divider is a precision shunt regulator comprising a resistor and a diode 8. The converter of claim 1, wherein the voltage sense and control circuit comprises a first transistor having its emitter coupled to the high voltage power line, its base coupled to the low voltage power tine via a further resistance element placed in series between the base the low voltage Ins, and its collector coupled in series with the hysteresis circuit 9. The converter of claim 8, wherein the further resistance element comprises at least a first reverse-biased Zener diode.10. The converter of claim 8, wherein the hysteresis circuit comprises a second transistor wfth its base coupled to the collector, which when activated switches out part of the further resistance element increasing the current into the base of the first transistor.11 The converter of any prereding claim, wherein the switch controier is a PWM (Pulse Width Modulator) controller.