GB2524017A

GB2524017A - Computing system comprising read only memory

Info

Publication number: GB2524017A
Application number: GB1404225.3A
Authority: GB
Inventors: Paul Mangion
Original assignee: Individual
Current assignee: Individual
Priority date: 2014-03-11
Filing date: 2014-03-11
Publication date: 2015-09-16
Anticipated expiration: 2034-03-11
Also published as: GB201404225D0; GB2524017B

Abstract

Disclosed is a read only memory interface. The interface has an N-bit address bus 11, an increment memory interface 12a-n, a decrement memory interface 17a-n, an N-bit primary ROM 14a-b, and an N-bit secondary ROM 16a-b. The address bus is connected to the primary ROM via the increment memory interface, and to the secondary ROM via the decrement memory interface. The increment and decrement interfaces may when they receive an address output different modified addresses for the two ROMs. The memory interfaces may each comprise a pair a N/2 half adders each half adder receiving a higher order bit and a lower order bit and outputting a higher order bit and lower order bit of the modified addresses at the respective carry and sum outputs of the half adders. The N-bit ROMs may comprise two N/2 bit memory modules. There may be half-adders connected between the pairs of N/2 bit memory modules. The increment and decrement interfaces may connect a data bus to their respective ROMs during different time periods of the address cycle.

Description

COMPUTING SYSTEM COMPRISING READ ONLY MEMORY

FIELD OF THE INVENTION

The present invention relates to a computing system comprising read only memory. In particular, the computer system enables the use of read only memory to store a computer operating system.

BACKROUND OF THE INVENTION

Known computing systems often store their operating systems on volatile random access memory (RAM), to provide faster access than what could be achieved with longer term storage solutions such as hard disks, However, when the operating system is stored on a volatile storage medium such as RAM, it is susceptible to modification by computer viruses, which can act to scramble the operating system (O/S) and its kernel, either slowing it down or destroying it altogether.

Such modifications can result in the data at various address locations being erased or replaced with different data, and not only the 0/S but also application software may be affected. Installing the 0/S back to its original state can take a long time, considering that it needs to be programmed once again to locate the memory addresses back to their origins.

It must also be considered that incompatible application software with the same address locations that coincide with the 0/S can significantly slow the 0/S down, Known 16-bit ROM has minimal address locations for an 0/S. i.e. present day ROM can only address certain features of a computer system and almost excludes the 0/S. Interrupt request signals (IRQ5) are one of the essential components required to operate on such a combined address system as well as features of the central processing unit (CPU). The CPU has instant access to ROM, which via ROM can process IRQs and other interfaces of the computer system. Addresses for the Cpu range from encryption of passwords, IRQ, ROM, random access memory (RAM) locations and input and output (I/O) systems.

Presently most of the 0/S is stored on a volatile medium such as a hard disc and attack by external viruses and incompatible software makes it potentially unstable rendering it useless once this happens. As a result of this the operating system of a computer can become very corrupt and functionless, at which point it needs to be scrapped and re-installed, wasting time and money. Application programs run inefficiently when the 0/S becomes corrupt, but with a stable 0/S, programs that are installed after the operating system can remain in a reasonably stable condition.

It is the object of the present invention to improve upon the known art.

SUMMARY OF INVENTION

According to the invention, there is provided a computer system comprising an N-bit address bus, an increment memory interface, a decrement memory interface, an N-bit primary read only memory, and an N-bit secondary read-only memory. The N-bit address bus is connected to the N-bit primary read-only memory via the increment memory interface, and the N-bit address bus is connected to the N-bit secondary read-only memory via the decrement memory interface.

The use of two separate memory interfaces to access two separate memories means that an N-bit address bus can be used to access two separate N-bit ROM memories, effectively doubling the amount of memory that can be addressed. This helps provide enough address space in ROM for the operating system to permanently reside, and since ROM is non-volatile the computer system can ifinction without any fear of the data it holds being modified by external influences such as corrupt data, computer viruses, and incompatible software.

A complete computer 0/S may be addressed and read by the CPU, on system firmware ROM together with (BIOS), driver routines and vital codes of the adjoining hardware with relevant computer programs that are essential to the individual computer system.

Additionally, the use of ROM means that data remains in its originally located address slots, helping improve the stability of the 0/S. Furthermore, the burden of having install an 0/S on a volatile medium each time the computer system is restarted is removed. The speed of program subroutines may also be improved and provide the user with a quicker response in real time and enable multiple programming operations.

The increment memory interface may be configured to receive an address on the N-bit address bus and output a modified address for the N-bit primary read-only memory, and the decrement memory interface may be configured to receive the address and output a modified address for the N-bit secondary read-only memory. The modified addresses enable more addressing capabilities for the computer processor to address data in ROM, and enables primary and secondary ROMs to be addressed and read as one large ROM. Preferably, the modified address for the N-bit primary read-only memory is a different address value to the modified address for the N-bit secondary read-only memory.

Advantageously, the increment memory interface may comprise N12 half adders, each half adder receiving a relatively higher order bit and a relatively lower order bit of the address bus, and outputting a relatively higher order bit and a relatively lower order bit of the modified address for the N-bit primary read-only memory at respective carry and sum outputs of the half adder. The use of half-adders interfaced between RONI modules and the address bus helps increase address and data locations to a larger number, incorporating more space for ROM to have a complete 0/S on a computer system.

The decrement memory interface may also comprise N/2 half adders, each half adder receiving a relatively higher order bit and a relatively lower order bit of the address bus, and outputting a relatively higher order bit and a relatively lower order bit of the modified address for the N-bit secondary read-only memory at respective sum and carry outputs of the half adder. Note the sum and carry outputs in the decrement memory interface are inverted (switched with one another) compared to the sum and carry outputs in the increment memory interface, for example the relatively higher order bits of the modified address for the N-bit primary ROM are generated by the carry outputs of the half adders, whereas the relatively higher order bits of the modified address for the N-bit secondary RONI are generated by the sum outputs of the half adders rather than the carry outputs.

Accordingly, there may be several half adders, which are connected in parallel to each other as a composite module and are coupled to ROM modules. The half adders may be configured in two ways, the first way uses a first interface with ordinary outputs connected to two 16 bit ROM modules, and the second way uses a second interface with inverted outputs connected to two 16 bit ROM modules. The first interface is referred to as the increment memory interface as it will increment addresses and data locations and the second interface is referred to as the decrement memory interface since addresses and data locations are decremented. ROM coupled to the increment interface will be referred to as primary ROM, and ROM coupled to the decrement interface will be referred to as secondary ROM.

The process of incrementing and decrementing addresses opposes one from the other, when the CPU addresses and reads primary ROM, which is coupled to the increment interface comprising the half-adders, and secondary ROM coupled to the decrement interface comprising the half adders with inverted outputs.

The half-adders can process addresses supplied by the address bus according to a binary system known as two's complement, as will be apparent to those skilled in the art. Interfacing the address bus to the ROM via the half adders of the increment and decrement memory interfaces, also isolates the ROM component from the CPU.

The N-bit primary read-only memory may comprise two N/2 bit memory modules, and the N-bit secondary read-only memory may comprise two N/2 bit memory modules, For example, N may be 32, and so each one of the primary and secondary ROMS may be formed by two t6 bit ROM modules, so that there are four 16 bit ROM modules in total, This helps to increase the number of storage locations available in the overall ROM. Clearly, N could alternatively be 16, 64, 128, 256 etc.

D

Furthermore, more pairs of RUM modules could be added to form larger primary and secondary memories as the address bus width is increased. Individual RUM modules may be connected in parallel to a row of half-adders for each of the increment and decrement memory interfaces.

The computer system may further comprise a first additional half-adder connected between the two N/2 bit memory modules of the N-bit primary read-only memory, and a second additional half-adder connected between the two N/2 bit memory modules of the N-bit secondary read-only memory. Then, all of the half-adders of each interface can be coupled together and synchronised electronically to enable more addressing capabilities which can be addressed and read by the CPU.

This helps computer latching of RUM modules and RUMs will be addressed and read as one large RUM. Specifically, each additional half-adder connected between one RUM module to the next RUM module adds another remainder to the binary addition, and changes the most significant bit (msb) first word address and data location automatically from one RUM module to the next adjoining RUM module. The additional half adders encapsulate all the RUM modules of the primary or secondary RUMS as one complete module, increasing speed in the implementation of program subroutines and giving the user quicker responses in real time and multiple programming operations.

The computer system may further comprise an N bit data bus, and a processor connected to the N-bit address bus and the N-bit data bus. The N-bit data bus may be connectable to the N-bit primary read-only memory via the increment memory interface, and the N-bit data bus may be connectable to the N-bit secondary read-only memory via the decrement memory interface.

To help the data from the primary and secondary RUMS to be read out via the N-bit data bus, the increment interface may be configured to connect the data bus to the N-bit primary read-only memory for a first period of time within each address cycle to read data from the N-bit primary read-only memory, and the decrement interface may be configured to connect the data bus to the N-bit secondary read-only memory for a second period of time within each address cycle to read data from the N-bit secondary read-only memory. This timing may be achieved using a quartz crystal or frequency phase shifter Alternatively, to help the data from the primary and secondary ROMS to be read out via the N-bit data bus, the CPU could use an interrupt flag or interrupt request to access the primary and secondary ROMs separately.

Furthermore, in addition to the increment and decrement memory interface modifying the addresses on the address bus, the increment and decrement memory interfaces may modify the data that is read from the primary and secondary memories in just the same way, using further halfadders. Then, the data that is actually stored in the ROM is an encrypted version of the data that is read of out the ROM via the increment and decrement memory interfaces.

Specifically, the increment memory interface may comprise a further 14/2 half adders, each further half adder configured to receive a relatively higher order bit and a relatively lower order bit of data stored in the N-bit primary read-only memory, and to output a relatively higher order bit and a relatively lower order bit of modified data from the N-bit primary read-only memory at respective carry and sum outputs of the further half adder. Therefore, the modified data is the unencrypted data which is receivedbytheCPUviathedatabu& Furthermore, the decrement memory interface may comprise a further N/2 half adders, each further half adder configured to receive a relatively higher order bit and a relatively lower order bit of data stored in the N-bit secondary read-only memory, and to output a relatively higher order bit and a relatively lower order bit of modified data from the N-bit secondary read-only memory at respective sum and carry outputs of the half adder.

The further half adders for modifying the data that is read from the ROMs, may be the same half adders as the half adders for modifying the addresses that are sent to the ROMS, for example if the half adders are switched from supplying an address to receiving data, once the address has been supplied to the ROM.

There are several ways in which the half-adder increment and decrement interfaces can be programmed and the advantage of both interfaces will each create a range address for individual 1/0 ports, starting with a low address and a high address given a particular single address, so one address will result in two different modified address values B and C from the address bus value A, one generated by the increment interface and the other by the decrement interface.

The 0/S software programmer will do the encryption of the software during the pre-burning of the ROM modules, taking into consideration that the 0/S would need to be written then burnt on a pre-programmed ROM, written as it would be on a volatile medium such as a mass storage medium.

The context of programming will depend on the programmer. It is also worth bearing in mind that the stored number A will produce B and C, and an additional D which is a random number generated by the half-adder, formulating A = [(B)+(C)]- [(Pi)+(D2)] or A = (B + C) -2D. This equation can be burnt on a separate ROM and inserted internally or externally to the CPU. The equation is a separate entity to the operating system itself However, other ways of programming the addresses of the half-adder's increment and decrement interfaces are also possible.

BRIEF DESCRIPTION OF DRAWINGS

An embodiment of the invention will now be described with figures from 1 to 12, in which: FIG. 1 shows an overview of the internal computer system hardware connected to firmware ROMs. ROMs coupled to the increment and decrement half-adders, FIG. 2 shows a more detailed picture of the configuration of two 16 bit firmware ROMs connected to the half-adder increment interface.

FIG. 3 shows the configuration of two 16 bit ROMs connected to a half-adder decrement interface.

FIG. 4 shows the half-adder logic gates (this is for reference purpose).

FIG. 5 shows a tmth table for the half-adder and a block diagram (this is for reference purpose).

FIG. 6 shows a typical sequence of a six hexadecimal digital address waveform before and after it passes through the half-adder increment interface.

FIG. 7 shows the half-adder with inverted outputs used for a decrement interface.

FIG. 8 shows a typical sequence of a six hexadecimal digital address waveform before and after it passes through the half-adder decrement interface.

FIG. 9 shows a schematic diagram configuration of the increment interface connected to two 16 bit ROM a-b.

FIG. 10 shows a schematic diagram configuration of the decrement interface connected to two 16 bit RONI a-b.

FIG. shows a truth table of the increment interface, when it increments the binary addresses, including the most significant bit (msb) first word address from one ROM module to the next.

FIG. 12 shows a truth table of the decrement interface, when it decrements the binary addresses, including the most significant bit (msb) first word address from one ROM module to the next.

FIG.13 shows a system memory map of hardware locations.

DETAILED DESCRIPTION

Examples and diagrams of the embodiment, illustrate the practical process of interfacing RUM to the Cpu and for this purpose enabling more RUM locations, which will accommodate a complete operating system (0/5) and relevant data, which correspond to the whole computer system.

FIG. 1 shows a typical computer system with blocks 10, through to 23, connected via a bus system II, 13, 15, 20, 18, 19, which represent this invention and the whole computer system in this scenario includes illustrations of primary and secondary RUM 14a-b, and t6a-b, interfaced to the half-adder increment interface 12a-n and inverted half adder decrement interface l7a-n, to the central processing unit (CPU) 1. Bus 20, is the data bus, which routes data from RUM to RAM and other input and output (I/U) devices 21, 22, 23, to the central processing unit (CPU) 10. Bus 11, is the address bus for the CPU 10 to address all devices. Bus 13, t8, is the address bus which follows on to bus 11 and bus 15, 19, is the data bus which follows on to bus 20, the address and data buses that couple the increment, decrement interface to primary and secondary RUM may not be considered as buses depending on the manufacturing of both interfaces that are connected to RUM.

Primary and secondary RUM 14a-b, ba-b, are configured independently to RAM 21, and the I/U systems 22, 23. RAN'l 21 data is refreshed constantly and the data is considered to be volatile but not in primary and secondary RUM 14a-b, 16a-b, as it is usually burnt on permanently. External data at 23 enters the computer system and input and output systems (110 systems) 22 (the peripheral devices) which have an affect on any volatile data within the system. When the data is then passed again through a half-adder increment interface 2a-n, and decrement interface I 7a-n, it will then be compared to the data in RUM and kept in a particular order. Then when the data is transferred from RUM to the CPU 10, the operating system (0/5) on RUM is untouched by incoming data.

The half-adder increment interface 12a-n and decrement interface 17a-n transfers data via primary and secondary RUM 14a-b, 16a-b to the CPU 10, separating buses 13, 15, 18, and 19 between primary and secondary RUM 14a-b, 16a-b, in order for the CPU 10, to access a large amount of data from RUM that contains the data which comes in the form of the computer U/S. The increment and decrement II) interface 12a-n, 17a-n, are connected separately via bus 11 and 20 to the CPU 10 and other devices as shown in FIG. I, coupled to separate RUM modules i.e. primary RUM I 4a-b, and secondary RUM I Ôa-b.

Buses 13 and 18 are separate address buses to each other that route the addresses from CPU 10, via the increment and decrement interface 12a-n, 1 7a-n, to primary and secondary RUM 14a-b, 16a-b, Buses IS and 19 are also separate data buses that route data to the CPU via the increment and decrement interface 12a-n, 1 7a-n, from primary and secondary RUM 14a-b, 16a-b.

It has to be considered as explained briefly previously that the presence of the secondary and primary RUM interface will not insert data in predicted address locations at the time it is programmed and this must be taken into account when the EPRUM is being programmed.

The solution to this can fomiul ate as; A= [(B) +(C)] -[(Di) + (D2)] or A = (B + C) -2D.

Where A = the CPU address fetch or write at bus 11, B = the address fetch or write at bus 13, C = the address fetch or write at bus 18, and D = the data return at bus 20.

FIG. 2 shows the broken down components of primary RUM I 4a-b, connected to a complete half adder increment interfacel2a-n and shows the bus structure 13, 15, 11 and 20 which connects the half-adder increment 12a-n, routed to primary RUM 14a-b, modules, bus 20 runs to the CPU (the CPU is not shown here) and other devices again not shown here and bus II is the address bus that runs from the CPU.

Each primary RUM 14a-b, stores information of the complete stable computer U/S and relevant data which is in the primary RUM 14a-b, burnt on RUM chipsi4a-b, and RUM interfaced via the half adder increment interface I 2a-n coupled with a

II

bus system 15 and 13. TheCPUisnotshownherebutrunstoandfrombuses 11, and 20, bus 20 being the data bus and lithe address bus.

Taking into consideration that the Cpu bus is 32 bit, in this scenario only two 16-bit ROMs are added to each interface. Should the bus width of the CPU be 64-bit then4ROMscanbeinsertedtoeachinterfaceandastheCPUbuswidthisincreased with future trends then the number of half adders can be increased to fit more ROM modules.

FIG. 3 shows the broken down components of primary or secondary ROM 16a-b, connected to a complete half adder decrement interfacel7a-n and shows the bus stmcture 18, 19, 11 and 20 which connects the half-adder increment 17a-n, routed to primary tOM lóa-b modules, bus 20 runs to the CPU (the CPU is not shown here) and other devices again not shown here and bus 11 is the address bus that runs from the CPU. Each secondary ROM 16a-b, stores information of the complete stable computer 0/S and relevant data which is in the secondary ROM I 6a-b, burnt on tOM chipsl6a-b, and tOM interfaced via the half adder decrement interface 17a-n coupledwithabus system 19 and 15.

There are two primary tOM modules 14a, and 14b, and two secondary tOM modules 16a, and 16b, each one with a 16 bit address bus andl6 bit data bus, making a total of four ROM modules. They are connected to the data bus DO to D3 1 and address bus A0 to A3 1, via the half-adder increment interface and decrement interface. The data is then addressed and fetched by the CPU to and from primaiy ROM I4a-b or secondary ROM ba-b. There may be various ways in which the CPU reads the primary and secondary ROM depending on the stucture of the program.

Primary and secondary tOM data could be read separately as low other bits and high order bits together, high or low depending on what works better, also an interrupt flag or interrupt request could be used to access primary and secondary ROM separately should primary and secondary tOM be configured in 64 bit i.e. extended to 64 bit ROW and read as A0 to A63.

The CPU addresses the location of data that it needs and then reads it via the data bus. During this process the half. adder increment or decrement 12a-n or 1 7a-n, transfers data in a parallel arid sequential order so it can be read as it were on one complete module on primary R01v114a to b, and secondary ROM ha to fr FIG. 4 shows the logic gate circuit ofa half adder 12 with gates; AND gate 1, OR gate 2 and inverter 3, this is one part of the increment circuit, which has been included for reference purpose. This is a configuration of gates that processes digital binary numbers for the half-adder.

Fig. 5 shows a truth table with results of all the combinations given in figure 4 of ones and zeros, the results of columns (a) and (b) in this case a and U for (a) and (b) or U and 1, and a 1 and 1, to give a result of sum (S) and carry (C) on a conventional circuit. The result of l's and U's at addresses (a) and (b) as shown produce an output of S or C to address AU and Al, following on to A2, A3 and as far as A3 I and outwards from DU, Dl as far as D3 I as it would be when all half adders are wired in parallel and interfaced between ROMs and the CPU. Also shown in the form of a block diagram is a single half-adder 12, as previously described in figures 4; this is one part of the half-adder increment interface 12a-n.

FIG. 6 shows a typical six-digit sequential address cycle for that of FIG. 2, before and after the increment process of a typical waveform. The dashed horizontal line separates the waveforms of the first two half adders of the increment interface from one another, The top four waveforms represent the address lines AU and Ad at the inputs aU and bU and outputs S and C of the first half-adder. The lower waveforms represent the address lines A2 and A3 at the inputs aU and bU arid outputs S and C of the second half adder, Further half adders operate on A4 -A3 I. The sequence of cycles before and after a waveform passes through the increment interface, and after it comes out the other end is the sequence of incrementing the binary numbers as they pass through the half-adder increment interface. The data here moves along a notch depending on the result. It can be observed as ones and zeros enter (a) and (b), with the addition of sum (5) and carry (C) from AU onto A3 1 produce a different waveform processed by the half adder, the waveform changes due to the result of S and C, FIG. 7 shows a half adder 17, with inverted outputs, in contrast to that of FIG, 4, Specifically, the outputs S and C of the first half adder shown in Fig. 4 of the increment interface form the address lines AU and Al respectively, whereas the outputs Sand C of the first half adder shown in Fig, 7 of the decrement interface are inverted the other way around to Fig. 4 to form the address lines Al and AO respectively.

Eight of the half adders 17 are grouped together to form the decrement interface 17. Gate 1 is an AND gate, gate 2 is an OR gate and gate 3 is an inverter.

The gates are shown as they would be wired to have inverted outputs and the result of (a) and (b) produce a different output to and from ROM modules as to the conventional half adder result. The configuration of gates 17, are switched around when attached to ROM 16a-b, FIG. 8 shows a typical six-digit sequential address cycle before and after the decrement process. The addition has the same process as the increment interface as in FIG. 2 but inverted. It can be noticed here that the value of the result of the waveform is different to that of FIG, 6 due to inverted outputs.

FIG. 9 shows a detailed schematic diagram of how the two 16 bit ROM firmware, primary ROM 14a-b is interfaced or connected to the conventional half-adders increment interface 1 2 from addresses AU to A31 and data output DO to D3lvia the system bus 11, 13, 15 and 20, each half adder counting 2 bits of binary addresses for a 32-bit address bus and 32-bit data bus. Buses 13 arid 15 may not be considered as buses depending on the manufacture of interfacing.

The vertical jotted lines indicate the composite module of the half adders interface and the arrows drawn across, point to the direction of the buses. There is another half-adder 12i added across one primary ROM 14a, to ROM 14b at address Al 5 and data line Dl 5 increasing the most significant bit (msb) first word CPU address and data location, The purpose of including this half adder is to combine the bus from 16 bits to 32 bits, In this configuration the firmware ROM is latched and connected as one unit component.

The CPU addresses and reads binary data via the half-adders 12a-n, As a result, more ROM data can be addressed and read, and the timing speed in the implementation of program subroutines is increased to give the user a quicker response in real time and multiple programming operations.

Connected via bus 11, through to bus 13, is the address bus, which is data, addressed by the CPU. Data bus 15, through to bus 20, is the data allocated to RAM and other devices (not shown here) and is read by the CPU when it is ready where it is executed and decoded.

FIG.10 shows a decrement half-adder series 17, with inverted outputs as it would be when it is connected or interfaced to two 16 bit ROMs. FIG. 10 also shows secondary RON'I 1 6a-b modules, as opposed to the increment half-adder interface shown in figure 9. The addition of the half adder I 7i decrements' the addresses and data location when read by the CPU in the same manner as figure 8, but the decremented locations of the decrement interface 17, produce opposing results to that of the increment interface.

The CPU (not shown here) will address and read locations on secondary ROM 1 6a-b. The inverted wiring of the decrement interface has the same sequence of the conventional half adders compared to the addresses and data of FIG. 8. The amount of addresses via bus 11 and 8 and the amount of data via bus 20 and 9 are also the same but connected in an inverted fashion for an opposing decrement process to that of half-adder increment interface.

FIG. 11 shows the increment interface tmth table of addresses (a) and (b) vertical input series, addressing the half-adders with outputs sum (S) and carry (C) which follow on to ROM modules as shown in FIG, 9, For this purpose, AU through and up to Al 8, would go onto A3 I with a series of binary ones and zeros, This process addresses the primary ROM modulesl4a-b, data by the CPU. Also included in the increment truth table are addresses Ai6 and A17 coinciding with AU, A2 of the following ROM module due to the connection of ROM a, to b. ROM modules 12i connecting them together as in figure 9. From this it can be observed that the most significant bit (msb) first word address from A14 to A15 has increased at the carry output.

Data out from DO to Dl 5 not shown in figure has the same process of data executed at the sum and carry outputs of (a) and (b) and follows the same order of increment by the interface, with a change of incremented data at D t 5, Dl 6 and Dl 7 again due to the addition of the half adder 12i.

FIG. 12 shows the decrement interface truth table. Due to the half adders having inverted outputs the values of ones and zeros from AU to A18 are opposed to the increment interface truth table shown in figure 11. Binary numbers at junctions (a) and (b) producing a result of a sum (S) and carry (C) at AO, Al and so on to A3 1. The change of decremented values of ones arid zeros at Al 4 and At 5 due to 1 7i decrease the msb first word address again in contrast to the address of the increment interface truth table, A14 and AIS shown in FIG. 11.

FIG. 13 shows the system memory map of the computer referred to in the present invention. The CPU is capable of addressing a 32-bit address bus but altogether addressing twice as much ROM addresses of the following; 112, 113, 114, 115, 116, 117, 118 and 119, memory system with each occupying individually slots of memory. RAM t20 occupies a separate amount of memory.

Following the BIOS 112, the operating system shares space with the kernel 113 since the kernel is the encryption of the operating system. The operating system has spaces 114, 115, the video system operation has space 116 which include driver codes for video and graphics, the sound system operation has space 117, the drives system operation has space 118 and the networks system operation has space t t9. The RAM 120 shares some free space that is temporally freed by the operating system.

Further embodiments falling within the scope of the appended claims will also be apparent to the skilled person.

Claims

CLAIMS1. A computer system comprising an N-bit address bus, an increment memory interface, a decrement memory interface, an N-bit primary read only memory, and an N-bit secondary read-only memory, wherein the N-bit address bus is connected to the N-bit primary read-only memory yia the increment memory interface, and wherein the N-bit address bus is connected to the N-bit secondary read-only memory via the decrement memory interface.
2. The computer system of claim 1, wherein the increment memory interface is configured to receive an address on the N-bit address bus and output a modified address for the N-bit primary read-only memory, and wherein the decrement memory interface is configured to receive the address and output a modified address for the N-bit secondary read-only memory.
3, The computer system of claim 2, wherein the modified address for the N-bit primary read-only memory is a different address value to the modified address for the N-bit secondary read-only memory.
4. The computer system of claim 1, 2, or 3, wherein the increment memory interface comprises N/2 half adders, each half adder receiving a relatively higher order bit and a relatively lower order bit of the address bus, and outputting a relatively higher order bit and a relatively lower order bit of the modified address for the N-bit primary read-only memory at respective carry and sum outputs of the half adder.
5. The computer system of any preceding claim, wherein the decrement memory interface comprises N/2 half adders, each half adder receiving a relatively higher order bit and a relatively lower order bit of the address bus, and outpufting a relatively higher order bit and a relatively lower order bit of the modified address for the N-bit secondary read-only memory at respective sum and carry outputs of the half adder.
6. The computer system of any preceding claim, wherein the N-bit primary read-only memory comprises two N/2 bit memory modules, and wherein the N-bit secondary read-only memory comprises two N/2 bit memory modules.
7, The computer system of claim 6, further comprising a first additional half- adder connected between the two N/2 bit memory modules of the N-bit primary read-only memory, and a second additional half-adder connected between the two N/2 bit memory modules of the N-bit secondary read-only memory.
8. The computer system of any preceding claim, further comprising an N bit data bus and a processor connected to the N-bit address bus and the N-bit data bus, wherein the N-bit data bus is connectable to the N-bit primary read-only memory via the increment memory interface, and wherein the N-bit data bus is connectable to the N-bit secondary read-only memory via the decrement memory interface.
9. The computer system of claim 8, wherein the increment interface is configured to connect the data bus to the N-bit primary read-only memory for a first period of time within each address cycle to read data from the N-bit primary read-only memory, and wherein the decrement interface is configured to connect the data bus to the N-bit secondary read-only memory for a second period of time within each address cycle to read data from the N-bit secondary read-only memory.
10. The computer system of claim 8 or 9, wherein the increment memory interface comprises a further N/2 half adders, each further half adder configured to receive a relatively higher order bit and a relatively lower order bit of data stored in the N-bit primary read-only memory, and to output a relatively higher order bit and a relatively lower order bit of modified data from the N-bit primary read-only memory at respective carry and sum outputs of the further half adder.
11. The computer system of claim 8, 9 or 10, wherein the decrement memory interface comprises a further N/2 half adders, each further half adder configured to receive a relatively higher order bit and a relatively lower order bit of data stored in the N-bit secondary read-only memory, and to output a relatively higher order bit and a relatively lower order bit of modified data from the N-bit secondary read-only memory at respective sum and carry outputs of the half adder. I8
12. The computer system of claim 10 or 11, wherein the address on the N-bit data bus, the modified address for the N-bit primary read-only memory, and the modified address for the N-bit secondary read-only memory are linked according to the equation A = (B + C) -2D, wherein A is the address on the N-bit address bus, B is the modified address for the N-bit primary read-only memory, C is the modified address for the N-bit secondary read-only memory, and D is the modified data.
13. The computer system of any preceding claim, wherein the N-bit primary read-only memory and the N-bit secondary read-only memory are configured to collectively store an operating system of the computer system.
14. A computer system substantially as described herein with reference to the accompanying drawings.