GB2519082A - Reducing parasitic leakages in transistor arrays - Google Patents

Reducing parasitic leakages in transistor arrays Download PDF

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Publication number
GB2519082A
GB2519082A GB1317761.3A GB201317761A GB2519082A GB 2519082 A GB2519082 A GB 2519082A GB 201317761 A GB201317761 A GB 201317761A GB 2519082 A GB2519082 A GB 2519082A
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Prior art keywords
conductors
conductor
drain
source
transistors
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GB201317761D0 (en
GB2519082B (en
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Stephan Riedel
David Gammie
Boon Hean Pui
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Plastic Logic Ltd
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Plastic Logic Ltd
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Priority to GB1317761.3A priority Critical patent/GB2519082B/en
Publication of GB201317761D0 publication Critical patent/GB201317761D0/en
Priority to TW103134869A priority patent/TWI676275B/en
Priority to CN201480055853.3A priority patent/CN105723512B/en
Priority to US15/023,752 priority patent/US9837450B2/en
Priority to PCT/EP2014/071468 priority patent/WO2015052201A1/en
Publication of GB2519082A publication Critical patent/GB2519082A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A transistor array comprising a first conductor layer defining a plurality of source conductors 2,4 and a plurality of drain conductors 6, 8, 10, 12; the source and drain conductors are associated with a respective transistor. A semiconductor layer 26 defines semiconductor channels between said source and drain conductors. A second conductor layer defines a plurality of gate conductors 16 each associated with a respective set of transistors. One or more storage capacitor conductors may be capacitively coupled to the drain conductors of a respective set of transistors. The gate conductor may be used to switch the transistors between on and off states, whilst the storage capacitor conductors are used to reduce the conductivity of one or more portions of the semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor. The aim of this is transistor array is to reduce the parasitic leakage between conductors.

Description

REDUCING PARfi5mc LEAKAGES IN TRANSISTOR ARRAYS Transistor arrays of Increasing density (number of transistors per unit area) are used, for example, for producing increasingly high resolution display devIces. it has been observed that the performance of transistor arrays for e.g. controlling display devices can be affected by leakage currents between conductors not associated with the same transistor via the semiconductor layer that provides the semiconducflng channels for the transistors.
One technique aimed at reducing such leakage currents Involves patterning The semiconductor layer so as to eliminate or reduce leakage paths in the semiconducting layer between conductors not associated with the same transistor.
The inventors have identified the challenge of providing an alternative technique for reducing parasitic leakage currents that either reduces or eliminates the need for patterning the semiconductor layer.
There is hereby provided a method of operating a device comprising an array of transistors, wherein the device comprises: a first conductor layer defining a plurality of source conductors, each source conductor associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors for said array of transistors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to at least a portion of the drain conductors for a respective set of transistors; wherein the method comprises: using the gate conductors to switch the transistors between on and oil states; and using the storage capacitor conductors to reduce the conductivity of one or more portions of the semiconductor layer
I
connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor, According to one embodiment, each drain conductor comprises a pad conductor connected by a line conductor to a drain electrode, and wherein said one or more storage capacitor conductors are configured to overlap with the whole of a perimeter portion of the semiconductor layer at the perimeter of each pad conductor.
There is also hereby provided a device comprising an array of transistors, wherein the device comprises a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; and a semiconductor layer providing the semiconductor channels for said array of transistors; wherein each source conductor is configured to lie between all conducting paths between the group of drain conductors associated with that source conductor and all other source conductors via the semiconductor layer.
According to one embodiment, the group of drain conductors associated with a source conductor extend In a first direction, and each source conductor comprises two line conductors extending In said first direction on opposite sides of saw group of drain conductors associated with the source conductor.
According to one embodiment, each source conductor comprises further conductors connecting said two line conductors in regions between drain conductors associated with the source conductor.
According to one embodiment, the device further comprises a plurality of gate conductors, each gate conductor is capacitatively coupled to the semiconducting channels for a respective set of transistors, and is also capacitativeiy coupled to a portion of the drain conductors for another set of transistors whose semiconducting channels are capacitatively coupled to an adjacent gate conductor; and wherein each source conductor comprises one or more portions extending between the drain conductors of adjacent transistors in the same group of transistors associated with the same source conductor.
According to one embodiment, each source conductorwholly encompasses the drain conductors associated with the source conductor.
There is also hereby provided an apparatus for operating a device comprising an array of transistors, wherein the device comprises: a first conductor layerdefining a plurality of source conductors, each source conductor associated with a respective group of transistors, and a plurahty of drain conductors each associated with a respective transistor; a semiconductor aver defining semiconductor channels between said source and drain conductors for said array of transistors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to at least a portion of the drain conductors for a respective set of transistors; wherein the apparatus is configured to apply different voltages to the gate conductors to switch the transistors between on and off states; and is further configured to apply a voltage to the storage capacitor conductors that reduces the conductivity of one or more portions of the semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
According to one embodiment, each drain conductor comprises a pad conductor connected by a line conductor to a drain electrode, and wherein said one or more storage capacitor conductors are configured to overlap with the whole of a perimeter portion of the semiconductor layer at the perimeter of each pad conductor.
Embodiments of the present invention are described hereunder in detail, by way of example only, with reference to the accompanying drawings, in which: Figure 1 Illustrates a configuration for the source and drain conductors of a transistor array according to an embodiment of the present invention, and illustrates a configuration for the storage capacitor conductors of a transistor array according to an embodiment of the present invention; Figure 2 illustrates a cross-section through line A-A In Figure 1; Figures 3 to 10 Illustrate other configurations for the source and drain conductors of a transistor array according to other embodiments of the present invention; and Figure 11 schematIcally Illustrates apparatus for controlling the voltages applied to the source and gate conductors in any of Figures 1 to 10, and apparatus for generating voltages applied to the common electrode lines in Figures 1 and 2.
Transistor arrays may comprise a patterned conductor layer defining: an array of independent source conductors and an array of Independent drain conductors. Each source conductor defines the source electrodes for a respective column of transistors, and provides a conductive connection between each transistor of the respective line of transistors to a terminal at the edge of the array.
Each drain conductor defines the drain electrode for a respective transistor. The drain conductors may also provide relatively large area conductor pads, which form storage capacitors with other conducting element of the transistor array such as common electrode (COM) lines. Transistor arrays may further comprise an organic semiconductor layer that provides the semiconducting channels between the source conductors and the drain conductors. Transistor arrays may further comprise a further patterned conductor layer defining an array of gate conductors, each gate conductor defining the gate electrode for a respective row of transistors (wherein a row Indicates a line of transistors extending In a direction substantially perpendicular to the columns of transistors mentioned above). A method of operating the transistor array may comprise applying an on-voltage to each of the gate conductors in sequence (whilst applying an off-voltage to all other gate conductors) and whilst a gate conductor is "on" applying respective voltages to the source conductors to achieve the desired electric potential at the drain conductors of the transistors In the row of transistors with which the "on" gate conductor is associated. Ideally, the voltage applied to any source conductor when a gate conductor Is "on" does not substantially affect the electric potenti& at the drain conductors of transistors associated with the other, "off" gate conductors and/or transistors associated with the same on" gate conductor but associated with different source conductors.
Figures 1 and 2 illustrate two examples of techniques for better isolating any transistor from transistor(s) associated with different source conductors and/or gate conductors, Figure 1 schematically illustrates the patterning of two conductor layers of a transistor array separated by a semiconductor layer 26, whIch provides the semiconducting channels of the transistors, and a gate dielectric layer 28 which capacitatively couples the gate conductors to the semiconducting channels. A lower patterned conductor layer Is formed on a substrate (such as a plastic substrate, e.g. PEN or PET) via a planarisation layer 24. The lower patterned conductor layer defines a set of source conductors 2,4 and a set of drain conductors 6, 8, 10 12.
The upper conductor layer defines a set of gate line conductors 16, and a set of COM line conductors 18 arranged in alternating sequence. The gate conductors 16 overlap (via the gate dielectric layer 28) wIth the portions of the semiconductor layer that connect the source and drain conductors where they are In closest proximity to each other.
Each drain conductor for a respective transistor comprises: (a) a drain electrode portion 6c, 8c, bc, 12c in closest proximity (typically less than about ZOmicrons) to the source conductor associated with the transistor; (b) a drain pad conductor 6a. 6b, 6c, 6d providing a relatively large area conductor for good capacitatlve coupling with one of the COM line conductors 18; and (c) a narrow line conductor connecting the drain electrode to the drain conductor pad.
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conductive interlayer interconnects 14 connect each drain pad conductor (via a respective hole 20 In the overlying COM line conductor) to a respective pixel electrode 32 defined by a further patterned conductor layer overlying the upper patterned conductor layer via an Insulator layer 30. The pixel electrodes 32 may be used, for example, to control the output of respective pixel portions of an electrophoretic optical display media (not shown).
Each COM line conductor 18 is configured to wholly overlap with the drain pad conductors for a respective row of transistors, and to also overlap with the whole of the perimeter portions of the semiconductor layer encompassing the perimeter of the drain pad conductors. The operation of the transistor array according to one embodiment of the Invention involves applying simultaneously to all COM line conductors 18 (including those COM line conductors adjacent to any gate line conductor in an on-state) a voltage that significantly reduces via a field effect the conductance of the underlying portions of the semiconductor layer 26. AccordIng to one example, the voltages applied to the COM line conductors are the same as the "off' voltages applied to the gate line conductors.
This reduction in the conductance of these portions of the semiconductor layer serves to better isolate the drain conductor of a transistor from both (a) source conductors other than that associated with the transistor, and also (b) drain conductors for other transistors associated with the same source conductor (but with a different gate conductor). In this example, an "off' voltage Is continuously applied simultaneously to all COM lines 18 as the gate lines 16 are tuned "on" in sequence.
Furthermore, each source conductor comprises (a) two conductor lines 2a, lb. 4a, 4b that (I) extend In parallel on opposite sIdes of the drain conductors of the transistors with which the source conductor Is associated, and (II) connect to the same respective terminal at the edge ot the transistor array; and (b) connecting portions k, 4c that connect the two conductor lines In regions between the drain conductors of the transistors with which the source conductor is associated. In the simple example illustrated in Figures land 2, the connecting portions 2c, 4c are also the portions
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of the source conductors (source electrode portions) that are In closest proximity to the drain conductors. The provision of each source conductor as two conductor lines on either side of the drain conductors of the respective column of transistors serves to better isolate those drain conductors from source conductors associated with other columns of transistors. in more detail, this configuration of the source conductors can, for example, lead to better charging of the drain conductors to the desired electric potential (such as, for example, the electric potential required to switch the respective pixel portion of an electrophoretic display media to a different state), by reducing the leakage of charge from the drain conductor to a neighbouring source conductor (I.e. a source conductor for a neighbouring column of transistors) driven at a different voltage.
Furthermore, the provision of each source conductor for a respective column of transistors as two parallel line conductors connected to the same terminal at the edge of the array and connected to each other at intervals by the connecting portions Zc, 4c has the additional advantage that the source electrodes of each of the column of transistors remain connected to the respective source terminal at the edge of the array even In the event of a failure of one of the two source lire conductors.
Figure 3 schematically illustrates an alternative technique for isolating drain conductors from one another. The transistor array of Figure 3 is partly characterised by the absence oF COM line conductors at the same level as the gate conductors 52. Instead, the required storage capacitance is achieved by configuring the drain conductor 44, 46, 48, 50 for each transistor such that it comprises a drain pad conductor (44a, 46a, 48a, 50a) that is capacitatively coupled to a gate conductor adjacent to the gate conductor associated with the transistor. The drain conductor pad for each transistor is connected via a line conductor to a drain electrode portion 44b, 4Gb in closest proximity (e.g. less than about 20 microns) to the source conductor 40. Similarly to the arrangement shown In Figures 1 and 2, interlayer interconnects 54 connect the drain pad conductors to a respectively overlying pixel conductor via a respective hole in the gate line conductors 52.
In Figure 3, the source conductor 40, 42 for each column of transistors comprises two tine conductors (Ca and 40b, 42a and 42b) extending In parallel on opposite sides of the respective column of transistors with which the source conductor Is associated. This arrangement serves to better isolate each drain conductor from the source conductors associated with adjacent columns of transistors.
In Figure 3, each source conductor 40 for a respective column of transistors is configured to have isolating portions 40c that extend between (I) the drain electrode portion 44b, 46b of a transistor having a semiconducting channel capacitatively coupled with a gate conductor 52, and (ii) the drain conductor pad (for an adjacent transistor In the same column of transistors) capacitatively coupled with the same gate conductor. These Isolating portions 40c extend substantially the whole length of the drain conductor pad In the direction In which the column of transistors extends; and serve to better isolate each drain conductor In that column of transistors from adjacent drain conductors in the same column of transistors.
The configuration schematically illustrated in FIgure 4 is the same as that Illustrated by Figure 3 except that the isolating portions 4Cc, 42c extend from the one of the two source line conductors opposite to the source line conductor that defines the source electrode portions, Ic. the portIons of the source conductor that are in closest proximity to the drain conductors.
In the arrangement schematically illustrated in Figure 5: a lower patterned conductor layer again defines the source and drain conductors for the array of transistors; but the source conductors for each respective column of transistors are configured as relatively wide line conductors 62a, 6Th that define a substantially circular hole for each transistor; and the drain conductor for each transistor is defined as a substantially circular island conductor 64a-64f that lies wholly within the respective hole, and is centred on the centre of the respective hole. The diagonal hashing in Figures Illustrates the location of the annular semiconducting channel for each transistor, Interlayer interconnects 68 provide conductive connections from the drain conductors 64 to a respective overlying pixel
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conductor (not shown) via respective holes In the gate conductors GOa, GOb, 60c. The arrangement shown in Figure 5 also serves to better Isolate the drain conductor pads from both (a) adjacent drain conductors associated with the same source conductor (i.e. drain conductors of transistors in the same column of transistors) and (b) source conductors associated with adjacent columns of transistors.
FIgure 6 schematically illustrates a similar arrangement to that illustrated In Figure 5 except that it employs angular structures. The source conductors 62 defIne substantially square or rectangular holes, and the substantially square or rectangular source conductors each lie wholly within a respective hole.
The arrangement schematically illustrated in Figure 7 Is the same as that schematically illustrated In Figure 5, except that both the holes in the source conductors 62a, 621, and the island drain conductors are configured so as to increase the Wi ratio of the transistors; wherein I. is the channel length (i.e. the shortest distance between the source and drain conductors) and W is the length of the semiconducting channel over which the source and drain conductors are separated by this shortest distance. In Figure 6, the Wi ratio is increased by patterning the Island drain conductors and the portions of the source conductor lines defining the holes such that the island drain conductors include outwardly radially extending projections 72 that extend into spaces defined by similar inwardly radially projections 70 defined by the source conductors.
The arrangement schematically illustrated in Figure 8 is the same as that schematically illustrated In Figure 7, except that both the holes in the source conductors 62a, 6Th and the island drain conductors have a substantially square or rectangular shape instead of a substantially circular shape.
An increase In the Wi ratio is achieved in the same way as in FIgure 8 by means ot complementary projections at the edges of the source and drain conductors.
The arrangements schematically illustrated in Figures 9 and 10 are similar to those Illustrated in Figures 5 to 8, expect that an increase in the WI ratio is achieved by patterning the island drain conductor and the source conductors such that both conductors define interdigitated fingers 74, 76 that mainly extend around the centre of the Island drain conductor.
in each of the arrangements Illustrated in Figures 5 to 10. each drain conductor Is connected to a respective pixel conductor via the interlayer interconnects 68; and In contrast to the arrangement shown In Figures 1 and 3, the pixel conductor associated with each TFT has at least a portion that lies directly above the gate line used to control the conductance of the semiconducting channel of that IFT (e.g. between on and off states). In order to substantially eliminate any capacitative coupling between the pixel conductor and the gate conductor for each itt, a conductive, screening layer (not shown) is provided between the conductive layer defining the gate lines 60 and a top conductive layer defining the array of pixel conductors. The screening layer is a substantially continuous layer, except that it defines holes for the interlayer interconnects 68 between the drain conductors and the respective pixel conductors.
The semiconductor layer 36 may be a continuous, unpatterned layer that extends over the entire footprint of the transistor array, or the above-described techniques can be used in combination with some patterning of the semiconductor layer. For example, the semiconductor layer could be patterned by laser ablation using as a mask the conductor layer that defines the gate conductor lines and/or COM conductor lines. In any case, the above-described techniques make it possible to achieve at least the same level of isolation (reduction of parasitic leakage pathways) with less or no patterning of the semiconductor layer. When the patterning of the semiconductor layer would otherwise be carried out by e.g. laser ablation, the need for less or no patterning of the semiconductor layer 26 can have the advantages of producing less detrimental debris and less variation in the amount of isolation across the transistor array. Furthermore, in the case of a top-gate transistor array, the complete elimination of a semiconductor patterning step can have the advantage of reducing the wait time between deposition of the semiconductor and the deposition of the overlying gate dielectric. This reduction in wait time can lead to better performance by reducing the length of time for which the critical part of the semiconductor layer (he. the part that forms the critical interface with the gate dielectric layer) is potentially exposed to harmful debris, moisture or air.
Figure 11 Illustrates one example of apparatus for controlling the voltages applied to the source conductors and gate conductors. The apparatus Includes a driver Integrated circuit (IC) 80. The single chip driver IC 80 comprises a gate driver block 86, a source driver block 88, a logic block 82 and a memory block 84. The functions of the logic block 82 Include: Interfacing between the driver IC 80 and a main processing unit (MPLfl; transferring data to and from the memory 84; co-ordinating the signals applied by the gate and source driver blocks to the gate and source conductors; and controlling the transfer of output data to the source driver. The driver IC 80 may Include other blocks. Figure 11 also schematically illustrates a high voltage generator 100 for generating a common "off' voltage for applying simultaneously to all CM lines 18 in the devices of Figures 1 and 2. In this example, the COM lines 18 are driven directly from the high voltage power generator.
In addition to the modifications explicitly mentioned above, it will be evident to a person skilled In the art that various other modifications of the described embodiment may be made within the scope of the Invention.
The applicant hereby discloses In Isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skills in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such indivIdual feature or combination of features.

Claims (9)

  1. ClAIMS 1. A method of operating a device comprising an array of transistors, wherein the device comprises: a first conductor layer defining a plurality of source conductors, each source conductor associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors for said array of transistors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to at least a portion of the drain conductors for a respective set of transistors; wherein the method comprises: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more portions of the semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
  2. 2. A method according to claim 1, wherein each drain conductor comprises a pad conductor connected by a line conductor to a drain electrode, and wherein said one or more storage capacitor conductors are configured to overlap with the whole of a perimeter portion of the semiconductor layer at the perimeter of each pad conductor.
  3. 3. A device comprising an array of transistors, wherein the device comprises a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; and a semiconductor layer providing the semiconductor channels for said array of transistors; wherein each source conductor is configured to lie between all conducting paths between the group of drain conductors associated with that source conductor and all other source conductors via the semiconductor layer.
  4. 4. A device according to claim 3, wherein the group of drain conductors associated with a source conductor extend in a first direction, and each source conductor comprises two line conductors extending in said first direction on opposite sides of said group of drain conductors associated with the source conductor.
  5. 5. A device according to claim 4, wherein each source conductor comprises further conductors connecting said two line conductors In regions between drain conductors associated with the source conductor.
  6. 6. A device according to claIm 4, whereIn the device further comprises a plurality of gate conductors, each gate conductor is capacitatively coupled to the semiconducting channels for a respective set of transistors, and is also capacitatively coupled to a portion of the draIn conductors for another set of transistors whose semiconducting channels are capacitatively coupled to an adjacent gate conductor; and wherein each source conductor comprises one or more portions extending between the drain conductors of adjacent transistors in the same group of transistors associated with the same source conductor.
  7. 7. A device according to claim 3, wherein each source conductor wholly encompasses the drain conductors associated with the source conductor.
  8. 8, Apparatus for operating a device comprising an array of transistors, wherein the device comprises: a first conductor layer defining a plurality of source conductors, each source conductor associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors for said array of transistors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to at least a portion of the draIn conductors for a respective set of transistors; wherein the apparatus is configured to apply different voltages to the gate conductors to switch the transistors between on and off states; and Is further configured to apply a voltage to the storage capacitor conductors that reduces the conductivity of one or more portions of the semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.
  9. 9. Apparatus according to claim 8, wherein each drain conductor comprises a pad conductor connected by a line conductor to a drain electrode, and wherein said one or more storage capacitor conductors are configured to overlap with the whole of a perimeter portion of the semiconductor layer at the perimeter of each pad conductor.
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GB1317761.3A GB2519082B (en) 2013-10-08 2013-10-08 Reducing parasitic leakages in transistor arrays
TW103134869A TWI676275B (en) 2013-10-08 2014-10-07 Reducing parasitic leakages in transistor arrays
CN201480055853.3A CN105723512B (en) 2013-10-08 2014-10-07 A method, apparatus and apparatus for reducing parasitic leakage in a transistor array
US15/023,752 US9837450B2 (en) 2013-10-08 2014-10-07 Reducing parasitic leakages in transistor arrays
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US10733930B2 (en) * 2017-08-23 2020-08-04 Facebook Technologies, Llc Interposer for multi-layer display architecture
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US9837450B2 (en) 2017-12-05
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GB2519082B (en) 2019-10-23

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