JP2012009543A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the reliability is improved by relatively reducing the area of a body contact.SOLUTION: A semiconductor device comprises a source region provided between a first drain region and a second drain region. Between the first drain region and the source region, a first body region is formed, and between the second drain region and the source region, a second body region is formed. The semiconductor device further comprises: a plurality of carrier path regions connected to at least one of the first body region and the second body region; and a contact region provided apart from the first body region and the second body region. The carrier path regions are electrically connected between the first or second body region and the contact region. The source region is surrounded by the first and second body regions, the plurality of carrier path regions, and the contact region.

Description

  Embodiments described herein relate generally to a semiconductor device.

  Development of a semiconductor device using an SOI (Silicon On Insulator) substrate in which an insulating layer and a silicon layer are stacked on a silicon substrate is underway. A FET (Field Effect Transistor) provided in a silicon layer on an insulating layer, a so-called SOI layer, has small parasitic capacitance and leakage current, and is excellent in high frequency characteristics. For this reason, it can be applied to, for example, a high-speed logic IC used in a mobile communication system.

  On the other hand, in the FET provided in the SOI layer, it is necessary to consider disadvantageous factors caused by the structure of the SOI substrate that are not found in the FET using the normal silicon substrate. That is, in an FET separated from the substrate with an insulating layer interposed, charges are likely to be accumulated in the body region under the gate, and the threshold voltage may fluctuate, resulting in unstable operation. In order to prevent this, it is necessary to form a body contact electrically connected to the body region on the surface of the SOI layer, and to discharge the accumulated carriers through the electrode connected to the body contact.

  However, providing the body contact on the surface of the SOI layer increases the area of the FET and hinders high integration. In addition, the body contact is a low resistance region in which impurities are doped at a high concentration, which may cause a decrease in the reliability of the FET. Therefore, there is a demand for a semiconductor device capable of relatively reducing the area of the body contact and improving the reliability.

JP 2008-251853 A

  Embodiments of the present invention provide a semiconductor device in which the area of a body contact is relatively reduced to improve reliability.

  A semiconductor device according to an embodiment is a semiconductor device including an insulating layer provided on a main surface side of a semiconductor substrate, and a first conductivity type semiconductor layer provided on an upper side of the insulating layer. The first and second drain regions of the second conductivity type selectively provided on the surface side of the layer, and selectively between the first and second drain regions and on the surface side of the semiconductor layer And a second conductivity type source region provided. A first conductivity type first body region is formed between the first drain region and the source region, and a first conductivity type is formed between the second drain region and the source region. The second body region is formed. A plurality of first conductivity type carrier path regions formed on a surface of the semiconductor layer and connected to at least one of the first body region and the second body region; A contact region of a first conductivity type that is selectively provided on the surface of the semiconductor layer apart from the body region and has a higher concentration of the first conductivity type impurity than the carrier path region. The carrier path region electrically connects the first or second body region and the contact region. The source region is surrounded by the first and second body regions, the plurality of carrier path regions, and the contact region.

It is a schematic diagram which illustrates the unit cell of a semiconductor device. (A) shows the planar arrangement of the unit cell, (b) shows the Ib-Ib cross section shown in (a), (c) shows the Ic-Ic cross section, and (d) shows the structure of the Id-Id cross section. Show. 3 is a schematic view illustrating a part of a planar arrangement of the semiconductor device according to the first embodiment. FIG. 1 is a schematic diagram conceptually showing the arrangement of FETs in a semiconductor device according to a first embodiment. FIG. 3 is a schematic view illustrating the arrangement of a lower layer of the gate electrode in FIG. 2. 1 is a schematic view illustrating a part of a cross section of a semiconductor device according to a first embodiment; (A) has shown a part of Va-Va cross section shown in FIG. 2, (b) has shown a part of Vb-Vb cross section shown in FIG. 1 is a schematic view illustrating a part of a cross section of a semiconductor device according to a first embodiment; 2 shows a state in which wiring is formed on the semiconductor surface shown in FIG. 2 via an interlayer insulating film, (a) shows a part of the Va-Va cross section, and (b) shows a part of the Vb-Vb cross section. Show. 6 is a schematic view illustrating a part of a planar arrangement of a semiconductor device according to a second embodiment; FIG. (A) shows the state where the gate electrode is provided, and (b) shows the semiconductor surface where the gate electrode is removed. It is a schematic diagram which shows notionally arrangement | positioning of FET in the semiconductor device which concerns on 2nd Embodiment. It is a schematic diagram which illustrates a part of planar arrangement of the semiconductor device which concerns on the modification of 2nd Embodiment. (A) shows the state where the gate electrode is provided, and (b) shows the semiconductor surface where the gate electrode is removed. It is a schematic diagram which shows the unit cell of the semiconductor device which concerns on a comparative example. (A) shows the planar arrangement of the unit cell, (b) shows the Xb-Xb cross section shown in (a), and (c) shows the Xc-Xc cross section structure.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof will be omitted as appropriate, and different parts will be described as appropriate. Although the first conductivity type is described as n-type and the second conductivity type is described as p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

The semiconductor device according to this embodiment is manufactured using a semiconductor wafer having an insulating layer 3 provided on the main surface 15 side of the semiconductor substrate 2 and an n-type semiconductor layer 4 provided on the upper side of the insulating layer 3. can do. For example, a so-called SOI wafer in which a laminated structure of a silicon oxide film (SiO ₂ ) and an n-type silicon layer is formed on a silicon substrate can be used.
The insulating layer 3 is not limited to the entire main surface 15 of the semiconductor substrate 2 but may be provided on a part thereof.

  FIG. 1 is a schematic view illustrating an FET 100 of a semiconductor device provided in the semiconductor layer 4. FIG. 1A shows a planar arrangement of unit cells. 1 (b) shows the structure of the Ib-Ib cross section shown in FIG. 1 (a), FIG. 1 (c) shows the structure of the Ic-Ic cross section, and FIG. 1 (d) shows the structure of the Id-Id cross section. ing.

  As shown in FIG. 1A, the gate electrode 7 provided between the source region 5 and the drain region 6 of the FET 100 extends toward the source region 5 at both ends in the channel width direction. A contact region 9 is provided at the tip of the extending portion 7 e of the gate electrode 7.

  In the Ib-Ib cross section shown in FIG. 1B, the active region of the FET 100 is shown. A p-type source region 5 and a p-type drain region 6 are selectively provided in the n-type semiconductor layer 4 provided on the insulating layer 3. The source region 5 and the drain region 6 are provided apart from each other, and an n-type body region 13 is formed therebetween. Furthermore, a gate electrode 7 is provided on the body region 13 via a gate insulating film 8.

  Since the FET 100 is a PMOSFET (positive channel Metal Oxide Semiconductor FET), an inversion channel in which holes are accumulated is formed between the gate insulating film 8 and the body region 13 by a negative gate bias applied to the gate electrode 7. A drain current flows from the drain region 6 to the source region 5. At this time, some of the holes are trapped in the body region 13, and the potential of the body region 13 may change.

  As shown in FIG. 1B, the body region 13 of the FET 100 is surrounded by the insulating layer 3, the source region 5, and the drain region 6. Therefore, the holes trapped in the body region 13 simply have no escape and are likely to accumulate in the body region 13. Therefore, in order to keep the potential of the body region 13 constant and stabilize the threshold voltage, it is possible to provide a carrier (hole) discharge path to discharge holes accumulated in the body region 13 out of the active region. desirable.

  In the FET 100, as shown in FIGS. 1C and 1D, carrier path regions 12 connected to both ends of the body region 13 are provided. Further, the carrier path region 12 is connected to the contact region 9. The carrier path region 12 is doped with an n-type impurity at the same level as the body region 13. On the other hand, the contact region 9 is doped with n-type impurities at a higher concentration than the carrier path region 12.

  For example, as will be described later, the contact wiring 26 can be connected to the surface of the contact region 9 and further electrically connected to the source wiring 23 (see FIG. 6). As a result, holes can be discharged from the body region 13 through the carrier path region 12, the contact region 9, and the source wiring 23.

In this embodiment, the impurity concentration of the carrier path region 12 is, for example, the same level as that of the body region 13, and the body region 13 and the contact region 9 that are provided apart from each other are made to have a low concentration carrier path region. 12 is configured to be electrically connected.
That is, the body contact in the present embodiment is configured by a combination of the carrier path region 12 and the contact region 9.

Next, the effect of providing the body region 13 and the high concentration contact region 9 apart from each other will be described.
For example, in the FET 150 according to the comparative example shown in FIG. 10, the body region 13 that is an active region and the contact region 9 are provided close to each other. Therefore, the hole discharge resistance from the body region 13 to the contact region 9 is small, and holes can be efficiently discharged from the body region 13.

  When the FET 150 having such a configuration is subjected to an NBTI (Negative Bias Temperature Instability) test, changes in the threshold value and the drain current appear relatively early, and it may become apparent that the estimated lifetime is short.

As shown in FIG. 10A, in the FET 150, the gate electrode 7 does not have the extending portion 7e extending to the source side. One end of the contact region 9 provided on both sides of the source region 5 is provided close to the gate electrode 7 located between the source region 5 and the drain region 6.
As shown in FIG. 10B, a body region 13 is formed under the gate electrode 7, and as a result, the contact region 9 and the body region 13 are arranged close to each other.

  The NBTI test is an accelerated test in which a gate voltage higher than the operating condition is applied to the gate electrode of the FET and the environment is maintained in a heated environment. Thereby, data for estimating the lifetime of the FET can be acquired.

For example, in the case of a PMOSFET such as the FET 150, a negative gate voltage is applied to the gate electrode 7 and maintained in a high temperature environment for a predetermined period.
During this time, for example, ionized and positively charged n-type impurities may move from the contact region 9 toward the gate electrode 7 and enter the inside of the gate insulating film 8 to change the threshold voltage.

  The above phenomenon occurs also in the normal operation of the FET, and in the NBTI test, it can be manifested in a short period of time by applying a high gate voltage and maintaining it in a high temperature environment. That is, it is shown that providing the contact region 9 and the gate electrode 7 close to each other is a factor that fluctuates the threshold voltage and may shorten the life of the FET.

  On the other hand, like the FET 100 according to the present embodiment, the movement of the n-type impurity toward the gate electrode 7 is suppressed by separating the contact region 9 doped with a high concentration of n-type impurity from the body region 13. The life of the FET 100 can be extended.

(First embodiment)
FIG. 2 is a schematic view illustrating a part of a planar arrangement of the semiconductor device 200 according to the first embodiment. In the example, a plurality of drain regions 6a and 6b, a source region 5, a gate electrode 7, and a contact region 9 constituting the semiconductor device 200 are efficiently arranged so as not to generate a useless space.

  The semiconductor device 200 according to this embodiment includes a p-type first drain region 6 a and a p-type second drain region 6 b that are selectively provided on the surface of the semiconductor layer 4 provided on the insulating layer 3. And a p-type source region 5 selectively provided on the surface of the semiconductor layer 4 so as to face the drain regions 6a and 6b.

  The drain region 6 a and the drain region 6 b are alternately arranged on the surface of the semiconductor layer 4 in the orthogonal X direction and Y direction. The source region 5 is disposed between the drain region 6a and the drain region 6b.

  A gate electrode 7 is provided between the source region 5 and the drain region 6a. The gate electrode 7 extends from a region sandwiched between the source region 5 and the drain region 6 a along the source region 5 to a position close to the contact region 9.

FIG. 3 is a schematic diagram conceptually showing the arrangement of FETs in the semiconductor device 200.
In this embodiment, the drain region 6 of the FET 100 shown in FIG. 1 is shared, and four FETs 100 are arranged in the X direction and the Y direction. Further, the extending portion 7e of the gate electrode 7 extends in the P direction (see FIG. 4) obliquely intersecting with each of the X direction and the Y direction, and the extending portion 7e and the contact region 9 are connected to the drain region. 6 is shared between adjacent source regions 5.

  As a result, when the four FETs 100 are arranged in a plane, a space is spread by the plurality of source regions 5 and drain regions 6a and 6b, and no useless space is generated. Furthermore, by sharing the extended portion 7e of the gate electrode 7 and the contact region 9 with each source region 5, the chip area can be reduced and high integration can be achieved.

FIG. 4 is a schematic view illustrating the arrangement of the lower layer of the gate electrode 7 in FIG.
An n-type first body region 13 is formed between the drain region 6 a and the source region 5. On the other hand, an n-type second body region 14 is formed between the drain region 6 b and the source region 5.

  A plurality of n-type carrier path regions 12 connected to at least one of the body region 13 and the body region 14 are formed between the source regions 5 arranged around the drain regions 6a and 6b. Further, n-type contact region 9 having an n-type impurity concentration higher than that of carrier path region 12 is provided apart from body regions 13 and 14.

  Carrier path region 12 electrically connects body region 13 or 14 and contact region 9. As a result, body regions 13 and 14, four carrier path regions 12, and two contact regions 9 are configured to surround one source region 5.

  The drain regions 6a and 6b and the source region 5 can be formed, for example, by selectively ion-implanting p-type impurities into the surface of the n-type semiconductor layer 4 (see FIG. 1). At this time, the gate electrode 7 may be used as a part of the mask. As a result, the body regions 13 and 14 are formed under the gate electrode 7 as part of the semiconductor layer 4 sandwiched between the drain region 6a or 6b and the source region 5. The carrier path region 12 is formed between the adjacent source regions 5.

  For this reason, there is no clear boundary between the body regions 13 and 14 and the carrier path region 12. A region in which a drain current flows from the drain region 6a or 6b to the source region 5 through the inversion channel formed under the gate electrode 7 can be the body region 13 or 14. The carrier path region 12 serves as a path for discharging holes accumulated in the body region 13 or 14 to the contact region 9. Therefore, the boundary between the body regions 13 and 14 and the carrier path region 12 shown in FIG. 4 is displayed for conceptually distinguishing the two.

  On the other hand, the contact region 9 can be formed, for example, by ion-implanting n-type impurities into the surface of the semiconductor layer 4. Therefore, contact region 9 is defined as a region into which an n-type impurity is ion-implanted, and can be provided apart from body regions 13 and 14 with carrier path region 12 interposed therebetween.

  The n-type impurity concentration of contact region 9 is formed to be higher than the n-type impurity concentration of carrier path region 12. Thereby, the discharge resistance when discharging holes from the body region 13 or 14 can be reduced. Furthermore, the contact resistance with the contact wiring 26 provided on the surface of the contact region 9 can be reduced, and the occurrence of electric field concentration can be suppressed.

As a result, gate electrode 7 is provided on the surfaces of body regions 13 and 14 via gate insulating film 8 and can extend from the surfaces of body regions 13 and 14 along the surface of carrier path region 12.
Furthermore, the gate electrode 7 can be provided so as to extend from the surface of the body region 13 or 14 to the boundary between the carrier path region 12 and the contact region 9.

Four carrier path regions 12 are connected to the contact region 9 and are electrically shared by the two body regions 13 and the two body regions 14 through the carrier path regions 12.
Thereby, as described above, the area ratio of the contact region 9 can be reduced to reduce the chip area. Furthermore, since the number of contact regions 9 can be reduced by sharing, the wiring pattern connected to the contact regions 9 can be simplified.

  As shown in FIG. 4, the carrier path region 12 extends in the P direction, for example. Therefore, a portion where carrier path region 12 and body region 13 or 14 are connected has an isosceles triangle shape having a width Lp of carrier path region 12 as a base and two sides of gate length Lg.

  On the other hand, for example, as shown in an embodiment described later (see FIG. 7), when the carrier path region 12 and the body region 13 or 14 are orthogonal to each other, the connection portion has a rectangular shape with widths Lp and Lg. Therefore, by configuring the extending direction of the carrier path region 12 so as to obliquely intersect the X direction and the Y direction, the area of the junction portion can be made smaller than when orthogonally crossed.

Furthermore, in the arrangement according to the present embodiment, Lp> Lg, so that the resistance value of the carrier path region 12 can be reduced, and the discharge resistance of holes from the body regions 13 and 14 can be reduced.
The angle θ at which the body regions 13 and 14 intersect with the carrier path region 12 can be set to 45 °, for example.

  FIG. 5 is a schematic view illustrating a part of a cross section of the semiconductor device 200. 5A shows a part of the Va-Va cross section shown in FIG. 2, and FIG. 5B shows a part of the Vb-Vb cross section shown in FIG.

  As shown in FIG. 5A, in the Va-Va cross section, the source region 5 and the drain regions 6 a and 6 b are selectively provided in the semiconductor layer 4 provided on the insulating layer 3. Body regions 13 and 14 are formed between drain regions 6a and 6b.

  A gate electrode 7 is provided on the surface of the body regions 13 and 14 via a gate insulating film 8 to form an active region of the FET. The FET corresponding to each active region shown in FIG. 5A shares the source region 5 and the drain regions 6a and 6b between the adjacent FETs.

  On the other hand, FIG. 5B shows a part of the Vb-Vb cross section along the carrier path region 12. The n-type carrier path region 12 selectively provided in the semiconductor layer 4 on the insulating layer 3 electrically connects the n-type contact region 9 and the n-type body region 13. An extended portion 7 e of the gate electrode 7 is provided on the surface of the carrier path region 12 via the gate insulating film 8.

  FIG. 6 shows a cross section in a state where wiring is formed on the surface of the semiconductor device 200 shown in FIG. FIG. 6A shows a part of the Va-Va cross section of FIG. 2, and FIG. 6B shows a part of the Vb-Vb cross section.

  As shown in FIG. 6A, the semiconductor device 200 includes, for example, a source wiring 23 connected to the source region 5 through a contact hole 27 provided in the interlayer insulating film 22, and a drain through the contact hole 28. A drain wiring 24 connected to the region 6a can be provided.

  Further, as shown in FIG. 6B, a body contact wiring 26 connected to the contact region 9 through the contact hole 29 is provided, and the body contact wiring 26 may be electrically connected to the source wiring 23. .

  A contact layer (not shown) can be formed on the surfaces of the source region 5, the drain regions 6 a and 6 b, and the contact region 9 to form ohmic contacts with each wiring. For example, when the semiconductor layer 4 is a silicon layer, platinum silicide may be formed as the contact layer.

(Second Embodiment)
FIG. 7 is a schematic view illustrating a part of a planar arrangement of the semiconductor device 300 according to the second embodiment. FIG. 7A shows the surface of the semiconductor layer 4 with the gate electrode 7 provided, and FIG. 7B shows the surface of the semiconductor layer 4 with the gate electrode 7 removed.

  As shown in FIG. 7A, the semiconductor device 300 includes a p-type first source region 5a and second source region 5b selectively provided on the surface of the semiconductor layer 4, and source regions 5a and 5b. And a p-type first drain region 6a and a second drain region 6b that are selectively provided on the surface of the semiconductor layer 4.

  The drain region 6a and the drain region 6b are provided in stripes and arranged in parallel. The plurality of source regions 5a and 5b are provided in parallel in the Y direction along the stripe between the drain region 6a and the drain region 6b.

  The gate electrode 7 is provided on the surfaces of the first body region 13 and the second body region 14 formed between the source regions 5a and 5b and the drain region 6a and the drain region 6b via the gate insulating film 8. It has been. Gate electrode 7 extends from the surfaces of body regions 13 and 14 along the surface of carrier path region 12.

  As shown in FIG. 7B, an n-type first body region 13 is formed between the drain region 6a and the source region 5a, and between the drain region 6b and the source region 5b. The n-type second body region 14 is formed.

  A plurality of n-type carrier path regions 12 are formed between the plurality of source regions 5a and 5b provided along the drain regions 6a and 6b, and are connected to at least one of the same n-type body regions 13 and 14. Has been.

  Further, a plurality of n-type contact regions 9 are provided between the body region 13 and the body region 14. Contact region 9 is provided apart from body regions 13 and 14 and is electrically connected via carrier path region 12. The n-type contact region 9 has an n-type impurity concentration higher than that of the carrier path region 12.

  In semiconductor device 300, contact region 9 is provided at an intermediate position between drain region 6a and drain region 6b, and body regions 13 and 14, a plurality of carrier path regions 12, and contact region 9 are formed as source regions. It arrange | positions so that 5a and 5b may be enclosed.

FIG. 8 is a schematic diagram conceptually showing the arrangement of FETs in the semiconductor device 300.
In the present embodiment, the source region 5 of the FET 100 shown in FIG. The extending part 7e of the gate electrode 7 and the contact region 9 are shared between the source regions 5a adjacent to each other in the X direction and between the source regions 5b (see FIG. 7).

  FIG. 9 is a schematic view illustrating a part of a planar arrangement of a semiconductor device 400 according to a modification of the second embodiment. FIG. 9A shows the surface of the semiconductor layer 4 with the gate electrode provided, and FIG. 9B shows the surface of the semiconductor layer 4 with the gate electrode removed.

As shown in FIG. 9A, the semiconductor device 400 is common to the semiconductor device 300 in that the drain regions 6a and 6b are provided in parallel in stripes.
On the other hand, between the drain region 6a and the drain region 6b, a plurality of source regions 5 are arranged along the Y direction in which the drain regions 6a and 6b extend.

  Gate electrode 7 extends in the direction of contact region 9 from the surface of body regions 13 and 14 formed between drain region 6 a and drain region 6 b and source region 5.

  As shown in FIG. 9B, the contact region 9 is provided at an intermediate position between the drain region 6a and the drain region 6b, being separated from the body regions 13 and 14. A plurality of contact regions 9 are arranged spaced apart in the Y direction.

  The carrier path region 12 formed under the extending portion 7e of the gate electrode 7 connects the body region 13 or 14 and the contact region 9, and together with the body region 13 or 14 and the contact region 9, the source region 5 Is enclosed.

  Also in the semiconductor devices 300 and 400 according to the second embodiment, the source wiring 23 and the drain are interposed via the interlayer insulating film 22 provided on the surface of the semiconductor layer 4 as in the semiconductor device 200 shown in FIG. Wiring 24 can be provided. Furthermore, the source region 5 and the contact region 9 may be electrically connected.

  In the first and second embodiments described above, a high concentration contact region spaced from the body region, which is a condition for obtaining the reliability of the FET having the SOI structure, and further, from the surface of the body region to the contact region. An extended gate electrode and a carrier path region formed thereunder are provided. Then, the arrangement of FETs with good space efficiency on the surface of the semiconductor layer is illustrated.

Thereby, the area of the body contact for discharging carriers from the body region in the SOI structure can be relatively reduced. In addition, a highly reliable semiconductor device that can be highly integrated can be realized.
Furthermore, the semiconductor devices 200 to 300 shown in the first embodiment and the second embodiment can be manufactured only by changing the arrangement and shape of each region without changing the conditions of the manufacturing process. .

  The present invention has been described above with reference to the first and second embodiments of the present invention, but the present invention is not limited to these embodiments. For example, embodiments that have the same technical idea as the present invention, such as design changes and material changes that can be made by those skilled in the art based on the technical level at the time of filing, are also included in the technical scope of the present invention.

2 ... Semiconductor substrate, 3 ... Insulating layer, 4 ... Semiconductor layer, 5, 5a, 5b ... Source region, 6, 6a, 6b ... Drain region, 7 ... Gate electrode, 7 ... Extension part, 8 ... Gate insulating film, 9 ... Contact region, 12 ... Carrier path region, 13, 14 ... Body region, 15 ... Main surface, 22 ... Interlayer insulating film, 23 ... source wiring, 24 ... drain wiring, 26 ... body contact wiring, 27, 28, 29 ... contact hole, 100, 150 ... FET, 200, 300, 400: Semiconductor device, L _g: Gate length

Claims (6)

A semiconductor device comprising: an insulating layer provided on a main surface side of a semiconductor substrate; and a first conductivity type semiconductor layer provided above the insulating layer,
First and second drain regions of a second conductivity type selectively provided on the surface side of the semiconductor layer;
A source region of a second conductivity type selectively provided between the first and second drain regions and on the surface side of the semiconductor layer;
A first body region of a first conductivity type formed between the first drain region and the source region;
A second body region of a first conductivity type formed between the second drain region and the source region;
A plurality of first conductivity type carrier path regions formed to connect to at least one of the first body region and the second body region;
The carrier is selectively provided on the surface of the semiconductor layer at a distance from the first and second body regions, and is electrically connected to the first or second body region via the carrier path region. A first conductivity type contact region having a concentration of the first conductivity type impurity higher than that of the pass region;
With
The semiconductor device, wherein the source region is surrounded by the first and second body regions, the plurality of carrier path regions, and the contact region.   The carrier accumulated in the first and second body regions is discharged to a wiring electrically connected to the contact region through the carrier path region and the contact region. 1. The semiconductor device according to 1. A gate electrode provided on the surfaces of the first and second body regions via a gate insulating film;
The semiconductor device according to claim 1, wherein the gate electrode extends from a surface of the first and second body regions along a surface of the carrier path region.   The semiconductor device according to claim 1, wherein the first and second body regions and the carrier path region cross each other at an angle. The first drain region and the second drain region are provided in parallel stripes,
The plurality of source regions are provided in parallel in a direction along the stripe between the first drain region and the second drain region. The semiconductor device described in one.   6. The semiconductor device according to claim 5, wherein the carrier path region is provided between the plurality of source regions and connected to at least one of the first and second body regions.

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