GB2517444A

GB2517444A - Pixel for global shutter operation

Info

Publication number: GB2517444A
Application number: GB1314864.8A
Authority: GB
Inventors: Guy Meynants; Jan Bogaerts
Original assignee: CMOSIS BVBA
Current assignee: CMOSIS BVBA
Priority date: 2013-08-20
Filing date: 2013-08-20
Publication date: 2015-02-25
Also published as: GB201314864D0

Abstract

A pixel for use in an image sensor comprises a photo-sensitive element 11, an input node 12 and a transfer gate TG connected between the photo-sensitive element and the input node that controls the transfer of charge to the input node. A first amplifier 20 has an input connected to the input node 12. A reset switch RS is connected between the input node and an output of the first amplifier for resetting the input node to a predetermined voltage. A feedback capacitance Cfb (that can be either a parasitic capacitance or a capacitive element) is positioned between the input node and the output of the first amplifier. A first sample stage connected to an output node of the first amplifier is selectively operable to sample and store a value of the input node. A second sample stage is connected in cascade with the first sample stage and is selectively operable to sample and store a value of the input node. An output stage comprising a second amplifier outputs a signal from the first sample stage and the second sample stage.

Description

Pixel for Global Shutter Operation

Technical Field

This invention relates to pixels and to image sensors comprising an array of pixels.

Background

M image sensor comprises an array of pixels. The sensor can be operated with a rolling shutter or with a global shutter. For an array with a rolling shutter, image acquisition is briefly shifted in time for evely row of the pixel array. A sub-set of the total set of rows in the sensor array are integrating light dunng the image readout time.

This sub-set of rows can be considered as a window which rolls over the focal plane array, hence the name rolling shutter'. This offset in the image acquisition time between rows leads to deformation of the captured scene and is particu'arly noticeaWe for a scene with moving content and/or where there is movement between the camera and the scene. For a global shutter, all pixels are exposed together (i.e. synchronously) and every pixel in the pixel array captures the scene at the same point in time. Another name for a global shutter is a snapshot shutter. A global shutter is desirable to record fast moving subjects and is advantageous in high speed imaging applications or in machine vision. A global shutter pixel requires a memory element inside the pixel array, to store the captured signal value during the frame readout time. The stored pixel signal values are then read out from the pixel array. row-by-row.

Global shutter configurations have been proposed, for example, in US Patent Application US 2009/0256060 Al. Figure 1 shows a pixel which can form part of an array which is capable of global shutter operation. The pixel comprises two storage elements Csjgnd. C which are used to store the reset and signal level of a sense node ED. Each storage element is shown in Figure 1 as a capacitor. Operation of the pixel will now be described. At the end of the exposure time, the sense node PD is reset and the reset level is sampled on C1 using switches Si and S2 and amplifier Al. Then S2 is opened. and the charge is transferred from the pinned photodiode to the sense node FD using the transfer gate. The voltage on the floating diffusion drops. The new voltage level on the ED is buffered by buffer ampl ifier Al and then sampled on Csjgiai.

This sampling occurs simultaneous'y in all pixels of the pixel array for global shutter operation. For readout, the vakes stored on the sample capacitor Cjg and C1 are read out sequentially, row by row. For this readout, a row of pixels is selected using the read transistor. The voltage stored on Ciset is buffered by amplifier A2 and put on the column output line. This value is sampled in the column amplifier of the image sensor. Then the switch S2 is closed. The charge on both capacitors Csjgnai, Creset iS redistributed and the signal is read out. If both capacitors have equal value, the signal read is A2<(Vjg + Vre)/2. where Vsig and Vres are the voltage levels sampled on and Creset respectively. In the readout circuit, the difference between both sampled pixel values is calculated. k this way, Vsig -V1-is calculated. This signal is free of kTC noise of the sense node Cfd. Operation of this pixel is described in detail in G. Meynants, "Global shutter pixels with correlated double sampling for CMOS image sensors", Journal of Advanced Optical Technologies 2013; VoL 2(2), p. 177-187. A similar pixel configuration is described in CN 102447848A.

Due to the charge redistribution between Csjgnai and Ci-eset, the signal read from a pixel is attenuated. This can be compensated by a gain higher than unity in amplifiers Al or A2. However, it has been found that a value of gain greater than unity can cause a reduction in accuracy.

The present invention seeks to provide an alternative alTangement for a pixel.

Summary

An aspect of the invention provides a pixel comprising: a photo-sensitive element for generating charges in response to incident radiation; an input node; a transfer gate, connected between the photo-sensitive element and the input node, for controlling transfer of charges to the input node; a first amplifier having an input connected to the input node; a reset switch connected between the input node and an output of the first amplifier for resetting the input node to a predetermined voltage; a feedback capacitance between the input node and the output of the first amplifier, wherein the feedback capacitance is a parasitic capacitance or a capacitive element; a first sample stage, connected to an output node of the first amplifier, which is S selectively operable to sample and store a value of an output signal of the first amplifier; a second sample stage which is selectively operable to sample and store a value of an output signal of the first amplifier; and, an output stage comprising a second amplifier, the output stage for outputting a signal from the first sample stage and the second sample stage.

It has been found that the amplifier used within a conventional pixel will amplify its own offset error, in addition to amplifying the wanted signaL Such offset errors can be of the order of 50 mY peak-to-peak (input referred) for the small transistors used as in-pixel amplifiers. This type of offset error is caused by threshold voltage variations. At the output, this error is amplified with the amplifier gain. This limits the available useable swing at the output of the amplifier. An advantage of an embodiment is that an input of the first amplifier can be calibrated in a way that the offset error of the amplifier is not amplified together with a wanted signal.

Advantageously, the first amplifier has a gain of greater than unity (1), i.e. it amplifies a signal received at the input.

Advantageously, the first amplifier comprises a first transistor having an input connected to the input node comprises and a second transistor in series with the first transistor, the second transistor serving as a load for the amplifier, wherein the output node of the amplifier is between the first transistor and the second transistor, the first transistor being connected to a reference voltage input which is variable during an operating cycle of the pixel. The reference voltage input can be variable after resetting the input node. Advantageously, the first transistor, or the first transistor and the second transistor, are NMOS transistors.

Advantageously, the first ampfifier comprises a first transistor in series with a second transistor, wherein the output node of the amplifier is between the first transistor and the second transistor, the input node is connected to an input of the second transistor, and an input of the first transistor is connected to a bias input.

Advantageously, the first transistor and the second transistor are PMOS transistors.

Advantageously, the second sample stage is connected in cascade with the first sample stage. For a cascade configuration, the output stage can be connected to an S output of the second sample stage, or the output stage can be connected to a node between the first sample stage and the second sample stage. Alternatively, the second sample stage can be connected in parallel with the first sample stage. An output stage can be selectively shared by the first and second sample stages for outputting a stored signal from the sample stages.

Advantageously, the first sample stage and the second sample stage each comprise a switch and a storage capacitor.

Another aspect provides an image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixds.

Advantageously, the control logic is arranged to cause the array of the pixel structures to be exposed synchronously.

Advantageously, the control logic is arranged to read a voltage signal from the pixel structures in the array for a first exposure period while the pixel structures are exposed for a second exposure period.

Advantageously, the control logic is arranged to vary a reference voltage input for the first amplifier during an operating cycle of the pixel. The control logic can provide a first reference voltage levd for use when resetting the input node and can provide a second reference voltage level when sampling a reset value of the input node.

The pixel array can be manufactured using a technology such as Complementary Metal Oxide Semiconductor (CMOS). Another aspect of the invention provides a method of manufacturing a pixel structure by forming regions and the epitaxial layer of the pixel structure, and to a method of manufacturing an image sensor comprising an array of the pixel structures.

The preferred features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the invention.

Brief Description of the Drawings

Embodiments of the invention will be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 shows a pixel capable of global shutter operation with two storage S stages in the pixel; Figure 2 shows an embodiment of a pixel according to the present invention; Figure 3 shows an embodiment where the first amplifier is an inverting amplifier comprising NMOS transistors; Figure 4 shows an embodiment where the first amplifier is an inverting amplifier comprising PMOS transistors, and where the feedback reset transistor is NMOS; Figure 5 shows an embodiment where the first amplifier is an inverting amplifier comprising PMOS transistors, and where the feedback reset transistor is PMOS; Figure 6 shows an embodiment where the first amplifier is an operational transconductarice amplifier; Figure 7 shows an alternative form of the sample stages; Figure 8 shows a pixel with a single storage stage; Figure 9 shows signal waveforms for nodes of the pixel of Figure 8; Figure 10 shows another pixel with a single storage stage; Figure 11 shows signa' waveforms for nodes of the pixel of Figure 10; Figure 12 shows an image sensor comprising an array of pixels of Figures 2-7; Figure 13 shows another pixel with two storage stages.

Detailed description

Embodiments of the present invention are described below by way of example only. These examples represent the best ways of putting the invention into practice that are currently known to the Applicant although they are not the only ways in which this could be achieved. The description sets forh the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples.

Throughout this specification, it should be noted that the term "row" and "column" can be interchanged. Also, the term "row" does not imply a particular orientation of the array.

Figure 2 schematically shows a first embodiment of a pixel 10. A full image S sensor comprises an array of the pixels 10 shown in Figure 2, with the pixels typically being arranged in rows and columns. The pixel 10 comprises a photodiode ii (advantageously a pinned photodiode) which is responsive to electromagnetic or particle radiation, although most typically this will be light in the visible band. A transfer gate TG is connected between the cathode of the photodiode 11 and an input node 12. The term "input node" is used in the description of embodiments as the configuration and use of this part of the pixel is different to a conventional pixel with a sense node/floating diffusion. A first amplifier 20 is provided for amplifying the signal from the input node 12. A negative input of the amplifier 20 is connected to the input node 12. A reset transistor RS is connected between the input node 12 and an output of the amplifier 20. The input node 12 can be reset by a reset transistor RS under the control of a reset signal (reset). The amplifier 20 provides gain to the system. A capacitance Cth exists between the negative input and the output node of the amplifier. This capacitance can be a parasitic capacitance which exists between these nodes (i.e. an electncal property ansing from the nodes and the space between the nodes), or it can be a capacitor device which is explicitly provided between these nodes. Operation of the sample switches SI and S2 is similar to the pixel described earlier. Ci.eset stores the reset level of the pixel (i.e. the reset level of the input node 12), Csjgnai stores the signal level after charge transfer from the photodiode ii to the input node. Amplifier 20 advantageously has a gain which is greater than 1. With a sufficiently large open loop gain (>20) the amplifier and feedback capacitor act as a charge sense amplifier and will output a signal equal to q /Cfb where q is the amount of charge transferred from the photodiode and Cfb is the feedback capacitance value.

Under these conditions, the feedback capacitance value is chosen such that the signal swing at the output of the amplifier 20 is as large as possible. This increases the signal swing used on the capacitors Ciset and Csjoiiai. The signal swing at the capacitors is larger than when a source follower is used as the first amplifier (amplifier Al in Figure 1), as described in Patent Application US 2009/0256060 Al. Because of the larger signal swing at the storage capacitors. the total output swing of the pixel is larger. lcTC noise contributions of the sampling capacitors Ciset and Csjai determine the noise levels. With equal capacitor values, this alTangement offers a larger dynamic range due to the larger signal swing, offered by the higher gain of the first amplifier 20. A further advantage of this arrangement is that, due to the feedback provided by the reset transistor RS. the amplifier 20 will not ampfify the offset error at its input.

The operation of the pixel of Figure 2 will now be described. After an exposure period, the input node 12 is reset via the reset transistor RS by enabling the reset line. The input node 12 will move to the operating reference point of the amplifier 20. The operating reference point depends on the amplifier implementation and various examples are described below. Then, the reset transistor RS is opened again. The output of the amplifier is sampled on Creset using switches SI and S2. This sampled value is representative of the reset level of the pixel (dark pixel). There is no gain applied to the reference (reset) value. For an ideal amplifier the reference level is always the same. In reality this is not always so. A small input offset error will be amplified. This input offset error can be for example caused by charge injection when the reset switch switches off When the reset switch switches off, some charge in the switch moves to the amplifier input node and causes a small voltage shift at this input.

This small voltage shift is amplified. The level sampled on Cei does contain this voltage shift, if it occurs, since it samples after that the amplifier switch is opened.

The type of offset error described here is caused by charge injection. This is different to the type of offset error caused by threshold voltage variations. Offset error variation due to threshold voltage variations can be around 50 my to 100 my peak-to-peak between pixels, while the offset due to charge injection is smaller, e.g. maximum 10 my. In embodiments, offset error variation due to threshold voltage variations is not amplified due to the feedback loop between the amplifier output and amplifier input. Also, the offset due to charge injection is [nearly] the same for every pixel.

S2 is opened after sampling of the reset level. Then, the transfer transistor TO is switched on. Charge is fully transfelTed from the photodiode II to the input node 12 and will redistribute between the input capacitance of amplifier 20 and the feedback capacitance CTh. An amount of photocharges, representing an amount of light falling on the photodiode 11, is converted to a voltage level at the output node of amplifier 20.

With the capacitive feedback Cfb, the charge-to-vohage conversion occurs on the feedback capacitor Cfb. The voltage at the output node of amplifier 20 changes. With infinite open ioop gain of amplifier 20, the voltage will change by Q/Cth, where Q is S the amount of charge transferred from the photodiode 11 to the input node 12, and Cfb is the feedback capacitor. With lower open ioop gain of amplifier 20, the amplifier output voltage will change by a lower amount but by an amount which is still sufficient to allow operation of the pixel. The offset error Votet at the input of the amplifier is not amplified because the input levd has been reset by the feedback loop through reset transistor RS. The amplified signal at the outprn node of amplifier 20 is sampled on the capacitor Csignai via the switch SI. At this point in time the capacitors Csignai and Creset each store a sampled value of the pixel. For global shutter operation.

all pixels of the array are exposed together.

The process of reading stored signal values from the pixds then begins. An additional reset of the input node 12 and photodiode 11 can be performed via the reset switch RS and the transfer gate TG. in order to empty the photodiode before the start of a next exposure. When the transfer gate TG is released, the next exposure starts.

Readout of the sampled signals on Cieset and Csjgnai is performed in a similar manner to the operation described above for Figure 1. The values stored on the sample capacitor Csignai and C1-1 are read out sequentially, row by row. For this readout, a row of pixels is selected using the read transistor. The voltage stored on C1-1 is amplified using amplifier A2 and put on the colunm output line. This value is sampled in the column amplifier of the image sensor. Then the switch S2 is closed. The charge is on both capacitors Csignai. C1 is redistributed and the signal is read out. If both capacitors have equal value, the signal read is A2*KVsig + YrcsV2, where Ysig and V are the voltage levels sampled on Csjguai and Creset respectively, In the readout circuit.

the difference between both sampled pixel values is calculated. In this way, Ysig -Yres is calcu'ated.

The second amplifier within each pixel can, for example, be a source follower with gain slightly less than I. Offsets are common mode to the two signals read and are subtracted from the pixel by taking the difference between both samples.

Figures 3 to 6 show some possible implementations of the first amplifier 20.

Figure 3 shows an inverting amplifier implementation, using only N-type metal-oxide-semiconductor (NMOS) transistors. This implementation is advantageous as the use of P-type metal-oxide-semiconductor (PMOS) transistors implies the use of S a n-well implantation and the n-well implantation will compete with the photodiode to collect photocharges from the substrate. A disadvantage of an NMOS inverter configuration as shown in Figure 3 is that the reference level to which the node 12 is reset should be rather low to get enough signal headroom at the output node Va of the amplifier. This conflicts with the requirement that, to guarantee a good charge transfer, the voltage at node 12 should be above the pinning voltage of the pinned photodiode. This pinning voltage is typically around Ito lW. So, the reset level of node 12 should be set to a voltage higher than the pinning voltage, while the output swing of the amplifier formed by transistors 30 and 40 should be maximised. A solution to this is shown in Figure 3 by the use of the REF input. Timing of the pixel is also shown in Figure 3. At the end of the exposure time, the reset transistor RS is closed to enable the feedback. The load transistor 40 is biased to a certain DC level and sets a culTent though the amplifying transistor 30. The current though the both transistors is I. If the culTent I is smat.l enough so that transistor 30 operates in weak inversion, then the gate-source voltnge V.gs of tran&tor 30 is equal to: nkT 1 1; where n is the subthreshold slope factor, k is Bo1tzmans constant, q is the elementaiy charge of the electron, T is the absolute temperature. and Jo is a constant for the transistor which may vary from device to device.

The node REF is set to a first voltage Vren, The vohage at the input node 12 after reset is: nkT el' V12 = + Vr1 = /n q Then the reset switch is opened. This causes a small charge injection at the input node, and a small change at the output. Then REF is set to a lower value Vgn. The difference between V1.0f1 and V12 is amplified by the gain of the inverting amplifier formed by transistors 30 and 40. The level sampled on Creset is: 10.

nfl iN = + A(VT,, Yef2) where A is the gain of the amplifier formed by transistors 30 and 40. After sampling of this voltage the charge can be transferred from the photodiode to the input node 12.

The voltage at the input node 12 is relatively high. This facilitates the charge transport. The charge transfer causes a voltage change QICfd at the node Va if the gain of the amplifier is sufficiently high. Th voltage sampled on the capacitor Csignai is: nkT *tJ\ . Q = lnr) + t1Vref Vre;) + q C;,, With lower amplifier open ioop gain, the swing at the output is smaller but in any case, the charge transferred from the photodiode can cause a large voltage swing at the output of the amplifier. This is sampled on Csjgnai using switch 51.

Figures 4 and 5 shows an alternate configuration using PMOS transistors. The inverting amplifier (20, Figure 2) comprises PMOS transistor 50 and PMOS load transistor 60. As with Figures 2 and 3, there is reset switch RS between the output of the amplifier and the input node 12. A feedback capacitance Cfb exists between the output of the amplifier and the input node 12. As mentioned above, the use of PMOS transistors may cause problems because the underlying n-well junction competes with the photodiode to collect photocharges. Modern CMOS processes have measures to avoid this, such as deep trench isolation. See for example, A. Tournier, et al, "Pixel-to-Pixel isolation by Deep Trench technology: Application to CMOS Image Sensor", International Image Sensor Workshop 2011, Hokka.ido, Japan (available via www.imagesensors.org). The drain of the amplifying transistor 50 is connected to a reference voltage REF. When REF is connected to Vdd, the reference to which the pixel is reset will be approximately one threshold voltage lower than Vdd. This level is suitable for charge transfer when the transfer gate is enabled. It may be advantageous since the pixel may operate without change of the REF voltage, and the connection of REF to VDD saves an interconnect line in the pixel. When charge is transferred, the charge is amplified through the sense amplifier and results in a voltage change at the output of the amplifier of Q/Cfb, if the open loop gain of the amplifier is high. The reset transistor can be PMOS (as shown in Figure 5) or NMOS (Figure 4).

or both in parallel. The pixel amplifying transistor is connected to REF which may, or may not, be equal to the Vdd supply for the source follower SF2. It is also possiNe to change the level on the REF input similar as described for fig. 3 to increase the output swing of the amplifier.

Figure 6 shows an implementation with a 5-transistor operational S transconductance amplifier (OTA). This OTA is formed by an input differential pair of transistors 80, 90 and by load transistors 81, 91. Load transistor 70 controls the culTent through the amplifier. As with previous embodiments, there is reset switch RS between the output of the amplifier and the input node 12. A feedback capacitance Cfb exists between the output of the ampfifier and the input node 12. Operation is similar to earlier described embodiments. The input node 12 is reset to reference level REF when reset is active.

Figure 7 shows another embodiment, which shows an alternative form of the output stages of the pixel. In Figure 7, the second amplifier A2 is connected to the first storage capacitor Csjgnai and to a node between the switches Si and S2. In contrast to the operation described for Figure 2, the signal level is read first and then the sum of signal and reset level is read when S2 is closed. The samples are read from the pixel in reverse order but the operation is the same. Operation during sampling of the signal and reset level is the same as shown in Figures 3-6. Figure 13 shows another configuration in which the two storage capacitors are operated in parallel.

All of the embodiments described above have two sample stages, with each sample stage having a storage node. They are particularly advantageous for global shutter operation with Correlated Double Sampling (CDS) as they provide in-pixel storage of a reset value and a signal value.

Figure 8 shows a pixel with only one storage node after the amplifier 20. This pixel can also be operated as a global shutter. Timing for global shutter operation is shown in Figure 9. First the charge sense capacitor is reset by closing the RS transistor. Then this reset level is sampled on the in-pixel storage capacitor Creset by switch Si. After opening switch 51, the charge can be transferred from the photodiode to the input node. The amplifier 20 will amplify the input signal and create a signal change öV = q1,j I Cffi. at its output, where qpd is the charge transferred from the photodiode to the sense amplifier, and Cib is the feedback capacitor. This charge remains stored on the feedback capacitor until the pixel is read out. For readout, the pixel is accessed by the READ transistor. The reset level stored on C10 is read. Then the switch SI is closed, and the signal V = qpd I Cu-, is read. A new exposure can be started after reading the signals. In pnnciple a new exposure can be started immediately after the falling edge of the pulse on the transfer control line if all charge is transfelTed to the input node. This may not be the case if the charge storage capacitance of the input node is limited. Some charge may remain on the photodiode 11. This is removed by the additional pulse on the transfer control line in combination with the RESET pulse at the right of Figure 9. This happens only after readout of the pixel. This is a so-called triggered global shutter pixel. Its signal must be read before the next exposure can start.

Figure 10 shows an alternative form a pixel with a single storage node which can allow pipelined integration, and has an anti-blooming drain. An additiona' transfer gate TG2 is connected to the photodiode ii. Transfer gate TG2 is used to reset the photodiode II at the start of the exposure, while the signal of the previous exposure is still stored on the feedback capacitance Cfb. Timing is shown in Figure 11. The extra transfer gate T02 also acts as an anti-blooming drain. It is connected to Vab which can be the pixel supply voliage or a dedicated DC voltage. In case when the photodiode is saturated, excess charges are evacuated via TG2. To do this, the low level applied to T02 is typically higher than the low level of TO. Excess charge may not move through TO, otherwise it will disturb the sampled signal stored on Cfb.

Pixels of Figures I to 7 do not need this extra transfer gate for anti-blooming. In that case, the input node 12 and reset transistor RS can effectively evacuate excess charges, in case of saturation, without disturbing the samples stored on the in-pixel capacitors Csignai, Creset.

Other amplifier topologies can be used, such as cascoded amplifiers or f&ded cascode amplifiers. The use of such amplifiers requires more transistors and mixed nmos/pmos transistors but, as the space required by transistors reduces in time, this can be possible in small pixels. The use of 3-D interconnections and multiple layers of silicon circuits on top of each other also allow the use of more complex circuit topologies.

An array of the pixel structures described above can be operated with a global shutter function. Control logic is arranged to cause the array of pixel structures to be exposed synchronously. The control logic can also arranged to read a voltage signal from the pixel structures in the array for a first exposure period whfle the pixel structures are exposed for a second exposure period. Alternatively, all of the pixels may be read before starting to expose pixels for the next exposure period. One signal, S or two signals (reset and signal) may be read from each pixel during readout.

Figure 12 shows an image sensor comprising an array of pixel structures 10 of any of the types descnbed above. Control logic 100 controls operation of the pixel array and output stages 106, 107. Control logic 100 comprises logic 101 for controlling exposure of pixels 10 and logic 102 for controfling readout of pixds 10.

Exposure control logic 101 can comprise line driver circuitry for generating control signals on control lines 103. Readout control logic 102 can comprise row selection/line driver circuitry for generating control signals on control lines 103 to control readout of pixels 10. Control ogic 100 can control: resetting of the pixe's to control the start of an exposure period (including operation of transfer gates and reset switch via control signal RST); operation of transfer gates to transfer charges to the input node; operation of readout switches by a control signal to control readout from pixels.

Example timing schemes for the control signals have been shown, and are known to a person skilled in the art. The pixel array can be read out in a conventional manner, with pixels being scanned on a row-by-row basis. Alternatively, control logic can perform a global shutter function by synchronising operation of the control signals which control respective exposure times of each of the pixels of the alTay. The control logic 50 can be stored in hard-coded form, such as in an Application Specific Integrated Circuit, or it can be stored in some form of reconfigurable processing apparatus, such as a ogic array (programmable array, reconfigurable array) or a general-purpose processor which executes control software. All of the elements shown in Figure 12 can be provided on a single semiconductor device or the elements can be distributed among several separate devices. In the case of a 3D integrated chip the pixel array is provided on a first wafer which is bonded to a second wafer containing control logic. Column output stage 106 can comprise column processing circuitry dedicated to each column, such as: an analog-to-digital converter (ADC), one or more amplifiers, storage to store values in order to perform features such as colTelated double sampling (CDS). An output stage 107 can perform further processing of the signals received from columns of the array.

Figure 13 shows an alternative implementation. The sample stages formed by the switches and the capacitors Crsei and Cjgnai are now connected in parallel at the output node of the first amplifier 20. The reference level is sampled on Crese through S the switch S2a. After charge transfer from the photodiode II through the transfer gate TO, the output signal of the first amplifier is sampled on Csignai through switch Sla. To read out, the signals stored on the capacitors are read through buffer amplifier A2 and the pixel read switch to the column output line sequentially. Switch S2b is used to read the reset level and switch Sib is used to read the signal level. The signal level can be read before or after the reset level. An advantage of this pixel architecture is that there is no capacitive redistribution when the second sample is read from the pixel.

This redistnbution attenuates the signal amplitude as discussed before. The signals read out in the pixel of Figure 13 have a larger amplitude. The implementation requires more control lines and in-pixel switches than the implementations of Figures 1-7 which have two sample stages connected in cascade. Figure 13 shows an output stage (amplifier A2, read switch) which is shared by the sample stages. In an alternative configuration, there can be a dedicated output stage for each sample stage.

Although the photo-sensitive element pinned photodiode) shown in the embodiments is connected to a single transfer gate, there can be two or more transfer gates connected to the photo-sensitive element, as described in EP 2 346 079 Al and US2O I 2/002089A I. Each of the charge storage nodes and/or charge-to-voltage conversion elements can be shielded in the manner described above.

Any range or device value given herein may be extended or altered without losing the effect sought, as will be apparent to the skilled person.

It will be understood that the benefits and advantages described above may relate to one embodiment or may relate to several embodiments. The embodiments are not limited to those that solve any or all of the stated problems or those that have any or all of the stated benefits and advantages.

Any reference to an item refers to one or more of those items. The term "comprising" is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.

The steps of the methods described herein may be camed out in any suitaWe order, or simultaneously where appropriate. Additionally, individua' blocks may be deleted from any of the methods without departing from the spirit and scope of the subject matter described herein. Aspects of any of the examples described above may S be combined with aspects of any of the other examples described to form further examples without losing the effect sought.

It will be understood that the above descnption of a prefelTed embodiment is given by way of example only and that various modifications may be made by those skilled in the art. Although various embodiments have been described above with a certain degree of particularity, or with reference to one or more individual embodiments, those skilled in the art could make numerous alterations to the disclosed embodiments without departing from the invention.

Claims

Claims 1. A pixel comprising: a photo-sensitive element for generating charges in response to incident radiation; an input node; a transfer gate, connected between the photo-sensitive element and the input node, for controlling transfer of charges to the input node; a first amplifier having an input connected to the input node; a reset switch connected between the input node and an output of the first amplifier for resetting the input node to a predetermined voltage; a feedback capacitance between the input node and the output of the first amplifier, wherein the feedback capacitance is a parasitic capacitance or a capacitive element; a first sample stage, connected to an output node of the first amplifier, which is selectively operable to sample and store a value of an output signal of the first amplifier; a second sample stage which is selectively operable to sample and store a value of an output signal of the first amplifier; and, an output stage comprising a second amplifier, the output stage for outputting a signal from the first sample stage and the second sample stage.
2. A pixel according to claim 1 wherein the first amplifier has a gain of greater than unity.
3. A pixd according to claim I or 2 wherein the first amplifier comprises a first transistor having an input connected to the input node comprises and a second transistor in series with the first transistor, the second transistor serving as a load for the amplifier, wherein the output node of the amplifier is between the first transistor and the second transistor, the first transistor being connected to a reference voltage input which is variable during an operating cycle of the pixel.
4. A pixel according to claim 3 wherein the reference voltage input is variaWe after resetting the input node.
5. A pixel according to claim 3 or 4 wherein the first transistor, or the first S transistor and the second transistor, are NMOS transistors.
6. A pixel according to claim 1 or 2 wherein the first amplifier comprises a first transistor in series with a second transistor, wherein the output node of the amplifier is between the first transistor and the second transistor, the input node is connected to an input of the second transistor, and an input of the first transistor is connected to a bias input.
7. A pixel according to claim 6 wherein the first transistor and the second transistor are PMOS transistors.
8. A pixel according to any one of the preceding claims wherein the second sample stage is connected in cascade with the first sample stage.
9. A pixel according to claim 8 wherein the output stage is connected to a node between the first sample stage and the second sample stage.
10. A pixel according to any one of claims 1 to 8 wherein the output stage is connected to an output of the second sample stage.
II. A pixel according to any one of the preceding claims wherein the first sample stage and the second sample stage each comprise a switch and a storage capacitor.
12. An image sensor comprising an array of pixels according to any one of the preceding claims and further comprising control logic which is arranged to control operation of the pixels.
13. An image sensor according to claim 12 wherein the control logic is arranged to reset the input node of the pixel by operating the reset switch.
14. An image sensor according to claim 12 or 13 wherein the control logic is arranged to cause the array of pixels to be exposed synchronously and is arranged to cause, for each of the pixels, the second sample stage to sample a value of the output S signal of the first amplifier after the input node has been reset and the first sample stage to sample a value of the output signal of the first amplifier after charge acquired during an exposure period of the photo-sensitive element has been transferred to the input node.
15. An image sensor according to claim 14 wherein the control logic is arranged to read a voltage signal from the pixel structures in the array for a first exposure period while the pixel structures aie exposed for a second exposure period.
16. An image sensor according to any one of claims 12 to 15 wherein the control logic is arranged to vary a reference voltage input for the first amplifier during an operating cycle of the pixel.
17. An image sensor according to claim 16 wherein the control logic is alTanged to provide a first reference voltage level for use when resetting the input node and to provide a second reference voltage level when sampling a reset value of the input node.