GB2510327A - A protective circuit for switched mode power converters - Google Patents

Abstract

A circuit 20 senses current in a switched mode converter and produces over-current signals which set SR latches 23/24, 25/26, which operate on logic gates 29, 30 to truncate the PWM signal that drives the power switches, the SR latches 23/24, 25/26 being reset by the next change in PWM signal level, to protect the switched mode converter. The circuit applies dead time to the PWM signal after the truncation to form non-overlapping drive signals to the converter switches. The circuit can be used to operate a switched mode power converter in a constant current mode. The dead time generation circuit may be disabled by a re-triggerable mono-stable means 36 if the SR latches are set and the PWM signal is truncated. The over-current threshold may be externally variable.

Description

A protective circuit for switched mode power converters

Field of the invention

This invention relates to a circuit which provides protection against current overload and inductor saturation in switched mode power converters and which can also be used to run switched mode power converters in a constant current mode.

Backciround Switched mode power supplies are of increasing importance in all fields of electronics, power conversion and power distribution. They all rely on the use of inductors and semi-conductor switches, in which the switches are alternatively switched on and off, in which the magnetic flux and stored energy in the inductor are cyclically increasing and decreasing. One side of such a circuit is provided with electrical power and this energy is stored in the inductor, the output side recovers this energy and supplies it to the output circuit.

An increasing proportion of such converters can be described as synchronous' in which at any time there are two active semi-conductor switches (Bipolar transistors, IGBTS or MOSFETS) which are switched on alternately, driven by a non-overlapping PWM waveform, in which one switch is turned on for the first part of the PWM waveform, and the second switch in the second part, in which it is the mark-to-space ratio of the PWM signal that determines the relationship between input and output voltages. Such converters are for instance described in US 3986097, EP 1346459(A2), US2004212357 (Al).

It is common to use micro-processor or micro-controller or dedicated clocked logic (microprocessor will herein be used to describe all such circuits) devices to generate the FWM waveforms and the dead time', which is the short period of time between the mark' and the space' sections of the PWM waveform in which neither switching device is switched on. This dead time is necessary to prevent shoot through' currents which generate unintended and excessive current flows if both switches are conducting simultaneously. Many proprietary control devices offer four logic outputs, constituting two non-overlapping PWM signals, each as its logic true' and logic inverse', so as to be able to drive the semiconductor switches with whichever polarity they require.

In any switched mode circuit it is important that the current does not become excessive in any cycle. It is crucially important that the inductors do not saturate: if they do they lose any effective inductance and current will then rise very rapidly, almost certainly causing failure of the semiconductor switching device unless some other protective mechanism operates to limit current rise.

Protective fuses act far too slowly to be effective at the operating frequency of any practical switched mode device, and fast electronic protective means are normally employed. In a micro- processor driven system, current sensing circuitry can send interrupt signals to the micro-processor which can change the drive signals to the switching devices, causing them to switch off the switch which is driving the increase in current. This can be very effective, however even the fastest interrupt responses require few microprocessor machine cycles to effect a protective drive change so there is some delay, and microprocessors and clocked logic have some other problems.

The principal weakness with micro-processor control is that micro-processors have a number of common failure mechanisms, which can leave the switching devices and the associated power circuit unprotected. These failure modes include failure of the micro-processor clock, software errors that cause program malfunction (often unpredictably and in response to untested data stimuli), and system noise, particularly power supply spikes'. Critically, even the fastest micro-processor re-start sequences take far longer (often tens of milliseconds) than it takes to irreparably damage the power circuits, and so there is little opportunity to recover from a microprocessor error sufficiently quickly to offer effective protection once a failure has occurred.

This Invention This invention relates to a an electronic circuit that uses a combination of analogue circuit elements and simple logic to provide protection to the power components in a switched mode power converter. None of the protective logic is clocked or relies on program code, and so the response is fast, predictable and reliable. This circuit can be constructed using discrete components, or integrated onto an integrated circuit.

This invention will now be described by reference to the attached drawings; Figure 1 shows a basic synchronous Buck' (down converter) circuit, implemented with complementary (N and P channel) MOSFET switches, which, when run in reverse, is also a simple Boost' (up-converter) circuit, as an example of a circuit to which this invention can be applied Figure 2 shows the basic circuitry of this invention Figure 3 shows a current sensing and limit detecting circuit which can be used with the circuit of Figure 2 in the application of Figure 1 Figure 4 shows a timing diagram for the operation of the circuit of Figure 1 in normal operation and in combination with this invention Figure 5 shows a basic synchronous coupled inductor circuit, implemented using N channel MOSFETs, as a second example to which this invention can be applied Figure 6 shows a modified version of the current sensing and limit detecting circuit for use with this invention as applied to the circuit of Figure 5 Figure 7 shows a modified version of the current sensing and limit detecting circuit shown in Figure 3 illustrating how the current limits may be externally and dynamically set so as to operate switched mode converters in a constant current mode Figure 1 shows, by way of example only, a switched mode circuit to which this invention can be applied, a basic synchronous converter, which can be used as a Buck or Boost converter depending on the sense of connection. In this example it will be assumed that this is used as a Buck converter, operation as a Boost converter can be understood by interchanging the terminology input' and output'. This circuit comprises lower and upper terminals 1 & 2 which are the input circuit, capacitor 3 which is a reservoir to provide smoothing to the input voltage, lower and upper MOSFET switches 6 and 8, each with an associated gate driver circuit 5, and upper and lower PWM logic inputs 4 and 7. Inductor 9 connects the switching point 15 of MOSFETs 6 and 8 to reservoir capacitor 12 via current sensing resistor 10. Connections 11 to current sensing resistor 10 provide a connection point for current sensing and limit detection circuitry which is part of this invention, as hereinafter further described. Upper and lower terminals 13 and 14 form the output circuit of the switched mode converter.

The basic circuit of this invention is is shown in Figure 2. The voltage generated across current sensing resistor 10 of Figure 1 passes via connections 11 to a current sensing and limit detecting circuitry 20 which contains an amplifier and comparators. An example of such a circuit is shown in Figure 3 and described below. In Figure 2 comparator output 21 will go to a logic low if the current in the resistor exceeds an upper positive limit, and comparator output 22 will produce a logic low output if it exceeds (in magnitude) a negative limit, ie is numerically less than this limit.

Sense resistor 1 must be in series with the inductor, and in some converter topologies it may be

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high side' at some elevated voltage, in other topologies it may be low side', connected to system ground, or at a potential close to system ground. Thus outputs 21 and 22 may need level translation or isolated transmission through opto-coupler devices: this detail will vary from application to application and is not shown..

Operation of the circuit will be further described with reference to Figure 2. NAND Gates 23 and 24 are cross connected to form an SR latch. Similarly NAND gates 25 and 26 form an SR latch.

Connection 27 is a logic input which accepts a PWM waveform from an external controller. This drives one input to gate 26, and through inverter 28 drives one input to the gate 24. In normal operation, when the current is within bounds, the comparator circuitry holds outputs 21 and 22 high. Thus every PWM cycle, when the PWM signal at input 27 is low, the SR latch comprising gates 25 and 26 is reset so that the output of gate 26 is high. Similarly when the PWM signal at input 27 is high the SR latch formed by gates 23 and 24 is reset by the inverted PWM waveform from inverter 28 such that the output of gate 24 is high. Thus in normal operation the PWM signal from input 27 passes through NAND gates 29 and 30, being first inverted in gate 29 and re-inverted in gate 30.

The current limiting operation can now be described. As will be further described below, the connection of drive signals to MOSFETs is arranged so that MOSFET 8 of Figure 1 is turned on when the PWM waveform is high, and MOSFET 6 is turned on when the PWM waveform is low.

If the current in inductor 9 should rise past a positive limit, then output 21 will go low. This will set the latch formed by gates 25 and 26 and the output of gate 26 will go low. This will disable gate 29, and truncate the high part of the PWM signal at the outputs of gate 29 (where the signal is inverted) and gate 30(where it is re-inverted), which will now turn off MOSFET 8 and turn on MOSFET 6, taking the switching point 15 of Figure 1 low, and causing the current in inductor 9 to start to fall. The latching action of the SR latch formed by gates 25 and 26 ensures that the logic outputs to drivers 5 remain in this state. The SR latch is reset when the incoming PWM signal goes low, however since the same low signal is also driving an input to gate 27, its output will remain unchanged. Note that in the discussion above, the convention is used that an eiioi excursion sets' a latch to denote the error, and the PWM signal resets' it, ready for the next cycle.

In an exactly similar way, if the converter is being used in reverse as a boost converter, and current through inductor 9 were to exceed a limit, then this would cause output 22 to go low, to set the SR latch formed by gates 23 and 24. This would disable gate 30, and change the PWM output to high at the output of gate 30, switching the drives to MOSFETS 8 and 6 and truncating the low part of the PWM wave form.

The outputs of gates 24 and 26 (or equivalently of gates 23 and 25) can be taken to connections and 46 and fed back to the external device that is genelating the PWM waveform to indicate that an ovei-curient condition is occuiring so that the PWM wavefoim is alteied at source, and other action appropriate to the application is taken.

The circuitry so far described is thus effective at truncating a FWM drive waveform such that it is protected against both positive and negative excess current flow. However it is also impoitant that this piotective switching does not act in such a way that both MOSFETs are ever simultaneously turned on. Thus it is necessary that the output of gate 30 drives a dead time generator that produces the signals to the driver 5 and MOSFETs 6 and 8. This is achieved as follows.

The PWM waveform at the output of gate 30 is fed to an SC network and inverter, which acts as a delay to both falling and rising edges of the signal: it is preferable that inverter 34 has Schmitt Trigger inputs with some hysteresis. The PWM signal from gate 30 also passes with little delay through a first input to AND gate 31 and through inverter 32. Similarly the delayed output of inverter 34 passes through inverter 35 and a first input of AND gate 36.

Output gates 37 comprise both AND and NAND gates. The upper pair gates 37 and 38 share inputs, and combine the un-inverted output of gate 30 with a delayed version of itself. AND gate 37 produces a signal that rises on the rise of the delayed signal, and falls on the falling edge of the un-delayed signal. NAND gate 38 produces the inverse logic of this signal.

The lower pair of gates 39 and 40 also share inputs, and gate together a signal which is the inverse of the PWM output of gate 30 with the inverse of itself. Similarly the rising edge of the output of Gate 39 follows the delayed signal, whereas the falling edge follows the un-delayed signal. Gate 40 produces the inverse of this logic signal. Because of the delays applied to the start of each logic output, dead time is generated between the signals.

Not all of the logic outputs from gates 37,38,39,40 will be needed in any application circuit, and might be omitted in a discrete circuit implementation, however they would enable an integrated circuit solution that would be widely applicable.

It will be seen that a second input of AND gates 31 and 36 are connected together, and that the each of these gates enables two of the output gates. So if this common logic connection to the second inputs of gates 31 and 36 is taken low, all the outputs are unconditionally taken to a state that turns off both switching MOSFETS. This can be used as a master enable.

Figure 2 also shows AND gate 48, re-triggerable monostable 36, and external input 47, with the common second inputs of gates 31 and 33 driven from the output of AND gate 48.

Re-triggerable monostable 36 is driven from the external PWM signal. Its function is to provide a ft positive output of duration a little longer than the longest cycle time of the FWM waveform when triggered by the positive edge of the PWM waveform. Since it is re-triggerable it will produce a continuous logic high output all the time the PWM signal is present. However if the PWM signal is not present, the output of monostable 36 will go low, and disable all the MOSFET5. The other input to gate 48 is an optional external enable connection 47, which has to be held high for the switched mode converter to operate. Either or both of these additional elements can be used optionally to give greater control and protection.

Figure 3 shows, by way of example, a circuit 20 for sensing and limit detection of the current.

Connections 11 connect to the current sensing resistor 10. One of connections 11, preferably the one that also directly connects to capacitor 11, goes to the non-inverting input of op-amp 51 and forms a local reference voltage for the circuit. The other connection 11 goes to resistor 50, which is connected to the inverting input to the op-amp 51, and feedback components resistor 52 and capacitor 53. Current sensing resistor 10 is normally of very low resistance, sufficient to produce a signal of typical magnitude 50 my at full current for the circuit. Resistors 50 and 52 set the gain of op-amp 51 so that its output is typically 0.5 to 2 volts for full current in resistor 10. Capacitor 53 limits the bandwidth of the circuit. Connections 56 and 59 go respectively to floating positive and negative supplies for this circuit, the connections are only shown to one of each of the comparators as if they were in a dual circuit package. The output of op-amp 51 goes to the inverting input of comparator 57 and the non-inverting input of comparator 58. Level setting resistors 54 and 55 divide down the floating supply so as to set a threshold voltage which is positive with respect to the local reference at the non-inverting input of comparator 57, and negative with respect to the local reference on the inverting input of comparator 58. The outputs of comparators 57 and 58 are connected respectively via connections 22 and 21 to the inputs of the SR latches. As noted above these connections will need opto couplers or some other means of level translation.

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Figure 4 shows a timing diagram for this circuit. Trace 60 is the waveform that is externally generated and connected to input 27. Trace 61 is the waveform generated at the output of gate 37, and trace 62 is its inverse generated at the output of gate 38. Trace 63 is the waveform generated at the output of gate 39, and trace 64 is its inverse generated at the output of gate 35.

Trace 65 is the resulting waveform generated at the switching point 15 on Figure 1. These descriptions relate to operation without the current tripping the limits.

Trace 66 is the current waveform in inductor 9 and sense resistor 10, as it would be if this invention were not connected in circuit. Dashed line 67 represents a current limit which it can be seen trace 66 exceeds. Trace 68 is the output 21 of the current sensing and limit detecting circuit, and pulse 69 is a low going signal generated by the over current condition.

Trace 70 is the output of gate 30 when this invention is connected in circuit and acts to limit current. It feeds forward through the dead time generation circuitry and would produce a truncated set of signals at the outputs of gates 37, 38, 39, 40. Trace 68 is the modified current signal, now showing that the current in the circuit only just exceeds the limit line 68, just sufficient to initiate the current protection which then sets the opposite MOSFET drive signals so that the current very rapidly starts to decline.

Figure 2 shows the full circuitry for current protection in a bi-directional circuit, however if the switched mode converter circuit is such that current will only flow in one direction, then one or other of comparators 57 and 58 can be omitted, together with one set of resistors 54 and 55, and one of the SR latches formed by gates 23, 24, 25 and 26. The unused input to gate 29 or gate would then need to be tied high, or the gate can be replace by an inverter. Inverter 28 can be omitted if gates 23 and 24 are unused. As above, these would all be retained in an integrated circuit solution so as to have the widest application. in

Figure 5 shows another switched mode topology which this invention can be used with. Figure 5 depicts a synchronous circuit using a coupled inductor. MOSFETs 76 and 77 are alternately switched on with a non-overlapping PWM waveform, using drivers (not shown) to connect the ouputs of gates 37 and 39 to MOSFET Gate inputs 80 and 81 (assuming N channel MOSFETS and non-inverting drivers).

The flux waveform in the coupled inductor 75 increases and decreases in the same way as in the inductor 9 in the circuit of Figure 1, but the current that is coupled to that flux is now carried alternately in the left and right hand circuits, as described in EP 1346459(A2). Current sense resistors 10 can now be in the low side of the circuit, but two are needed. Each connects via connections 11 to an op-amp, and each op-amp is now associated with a single comparator that will produce an output when the current in either circuit exceeds a limit when flowing in the conventional direction, ie from positive to negative through the MOSFET. Each comparator provides one of outputs 21 and 22, connected such as to effect the truncation action of the PWM waveform that is described above. Figure 6 shows a modified current sensing and limit detecting circuit 20 for use with the switched mode circuit of Figure 5.

The circuit of this invention can also be used to advantage with more complex switch mode converter topologies such as that disclosed in US20042 12357 (Al). There would again be two current sensing resistors 10, positioned in the high side as for the circuit of Figure 1. Each sensing resistor would be connected to a current sensing and limit detecting circuit 20, as detailed in Figure 3. In the circuit of US2004212357 (Al) only one pair of switches is actively switching at the PWM frequency, the others are switched permanently on (top switch) and off (bottom switch) so as the route current through the non-converting side. There is therefore a choice as to whether to use one truncating and dead time circuit as shown in Figure 2 per side or to use one circuit with additional routing logic applied to the current limit outputs 21 and 22 arid outputs 41 to 44.

The current limiting ability of this circuit may also be used to run any synchronous switched mode converter in a constant current mode, by intentionally setting the external PWM drive such that it would otherwise run to excess current, and arranging that the current limiting thresholds are externally variable. Figure 7 shows a modified version of the circuit of Figure 3 in which the non-inverting input of comparator 57 is brought out to connection 81, and the inverting input of comparator 58 is brought out to connection point 82. For clarity the local voltage reference is shown brought out to connection 80. A variable voltage source applying a negative voltage to connection 82 with respect to connection 80 will be effective to control positive current through the switched mode supply (from input to output by the conventions of Figure 1). A positive voltage applied to connection 81 with respect connection 80 will be effective in controlling current in the negative direction. As mentioned above, if the current will only ever go in one direction then one comparator and input is not needed.

As also mentioned above, the local reference potential on connection may not be at ground potential, and so level shifting or opto-coupling of these variable voltages may be required, but this is readily achievable by a variety of well known means. i2

Claims (7)

1. Claims 1. A circuit as shown in Figure 2 for truncating a PWM waveform, comprising a current sensing and limit detecting circuit 20 as detailed in Figures 3, 6 or 7, one or more SR latches that are set by over-current signals from current sensing and limit detecting means 20 and reset by the opposite phase of the PWM signal, which combine with gates 29 and 30 to switch the PWM signal to the opposite state as soon as over-current is detected, in which the PWM signal is then further modified so as to apply dead time and produce at least two outputs that form a non-overlapping drive signal pair to drive semi-conductor switches in a synchronous switched mode power circuit.
2. 2. A circuit as in claim 1 which additionally has a re-triggerabie monostable means 36 that enables the dead time generation circuit only when the input PWM signal is active, and which will disable the dead-time circuit in a time a little longer than a PWM cycle if the input PWM signal is lost and sets the drive signals from gates 37,38,39 and 40 such that both semi-conductor switches of the switched mode device are switched off.
3. 3. A circuit as in claim I which additionally has an enable signal taken to an external connection 47 which disables the dead-time circuit immediately when the signal at connection 47 is low and sets the drive signals from gates 37,38,39 and 40 such that both semi-conductor switches of the switched mode device are switched off.
4. 4. A circuit as in claim in which the protective features of claims 2 and claims 3 are combined by the use of AND gate 48
5. 5. A circuit as in any of the claims above where the current sensing and limit detecting means is substantially as shown in Figure 3 or Figure 5 or Figure 7
6. 6. A circuit as in any of the claims above in which the over-current threshold applied to the comparators of current sensing and limit detecting means 20 are made externally variable, as shown in Figure 7 so that the circuit of Figure 2 can be applied to intentionaliy run a switched mode power converter in a constant current regulating mode
7. 7. A circuit as in any of the claims above which has equivalent logic that can be arrived at by the application of De Morgan's theorem or other logical equivalence