GB2504060A

GB2504060A - An attenuation circuit comprising a plurality of attenuation stages provides a controllable DC offset

Info

Publication number: GB2504060A
Application number: GB1208898.5A
Authority: GB
Inventors: Srdjan Milenkovic; Robin Miller; Danny Webster
Original assignee: Lime Microsystems Ltd
Current assignee: Lime Microsystems Ltd
Priority date: 2012-05-21
Filing date: 2012-05-21
Publication date: 2014-01-22
Anticipated expiration: 2032-05-21
Also published as: GB2504060B; GB201208898D0

Abstract

An attenuation circuit, for attenuating a signal whilst providing a controllable DC offset, comprising an input Vin+, Vin-, an output Vout+, Vout-, a common rail VCm and a plurality of attenuation stages 1, 2, 3, 4. Each attenuation stage comprises a switch 8a, 8b, 8c, 8d and a first resistor 5a, 5b, 5c, 5d. First resistors 5a, 5b, 5c are connected at junctions 6a, 6b, 6c of each stage 1, 2, 3 in series to the first resistor 5b, 5c, 5d of a subsequent one of the attenuation stages 2, 3, 4. First resistor 5d of the terminal attenuation stage 4 is connected at a junction 6d of that stage to the output Vout+, Vout-. Second resistors 7a, 7b, 7c, 7d are connected between the junctions 6a, 6b, 6c, 6d of each attenuation stage 1, 2, 3, 4 and the switches 8a, 8b, 8c, 8d. The switches 8a, 8b, 8c, 8d are arranged to selectively connect the second resistors 7a, 7b, 7c, 7d to either the input Vin+, Vin- or the common rail VCm. Each attenuation stage 1, 2, 3, 4 is provided with a current source 10a, 10b, 10c, 10d arranged to selectively apply a constant current signal to the junction 6a, 6b, 6c, 6d of that stage 1, 2, 3, 4.

Description

ATTENUATION CIRCUIT

This invention relates to an attenuation circuit, such as may be used to provide both a controllable attenuation and a controllable DC offset of an input signal.

One of the problems of RF (radio frequency) transmitters using Zero IF (intermediate frequency, also known as homodyne) structures is DC (direct current) offset. The presence of DC offset in the transmitter chain can causc carrier leakage, thereby upsetting the integrity of the transmitted signal.

One method to circumvent this issue is to simply add a DC offset of equal and opposite value to the DC. offset in the signal prior to high frequency up conversion.

The offset must be stable and this is often accomplished by using a digital to analogue converter (DAC). The resolution of the DAC is critical since carrier removal by DC offset cancellation is very sensitive. It is not uncommon to use an eight bit DAC for this purpose.

In some implementations, the amplitude of the signal is matched to the subsequent stage using amplification or attenuation prior to up conversion. The DC. offset is generated in a separate DAC circuit, and then combined with the level-corrected signal in a third, summing circuit. However, this use of three separate circuits is wasteful of valuable space on the integrated circuits used.

According to a first aspect of the invention, there is provided an attenuation circuit for attenuating a signal whilst providing a controllable DC offset, comprising an input, an output, a common rail and a plurality of attenuation stages, each attenuation stage comprising: a switch; a first resistor which is, except in a terminal one of the attenuation stages, connected at a junction of that stage in series to the first resistor of a subsequent one of the attenuation stages, the first resistor of the terminal attenuation stage being connected at a junction of that stage to the output; a second resistor connected between the junction of that attenuation stage and the switch; the switch being arranged to as selectively connect the second resistor to either the input or the common rail; in which each attenuation stage is provided with a current source arranged to selectively apply a constant current signal to the junction of that stage.

Thus, an attenuation circuit is provided that can simultaneously provide a DC offset from the current sources. By selectively applying or not applying current to the junction of each stage, a range of different DC offsets can be providcd, which can be changed dynamically. Because the DC offset is generated in the same components as used to generate the DC offset, the area of silicon used to create this circuit as compared with the embodiment using three separate circuits described above is reduced.

The circuit may comprise an initial attenuation stage comprising a junction, a switch, a first resistor connected between the junction and the common rail and a second resistor connected between the junction and the switch, the switch being arranged to as selectively connect the second resistor to either the input or the common rail, the junction being connected to a terminal of the first resistor of one of the attenuation stages, the terminal being connected to no other junction of the attenuation stages.

The circuit may further be provided with an additional current source arranged to apply a constant current signal to the junction of the initial attenuation stage. Given that the circuit will generate a plurality of discrete DC offsets, this allows that plurality of offsets to be shifted as a whole, typically so that that one of the DC offsets can align with a convenient value, such as nil voltage.

The circuit may be a single-ended circuit, in which a single input signal is received at the input, and thc common rail will typically be held at a defined voltage, which may be ground.

Alternatively, the circuit may be a differential circuit, in which an input signal is received as two complcmcntaiy signals having the same magnitudes but having the opposite polarities. As such, the circuit may comprise a mirror input, which will typically receive same signal as at the input, but inverted, and a mirror output, at which will typically be output thc same signal as at the output, but inverted. Each attenuation stage may thcn comprise: a mirror switch; a first mirror resistor which is, except for a terminal onc of the attenuation stages, connected at a mirror junction of that stage in series to the first mirror resistor of a subsequent one of the attenuation stages, the first mirror resistor of the terminal attenuation stage being connected at a mirror junction of that stage to the mirror output; a second mirror resistor connected between the mirror junction of that attenuation stage and the mirror switch; the minor switch being arranged to as selectively connect the second mirror resistor to either the mirror input or the common rail, iii which the current source of each stage is arranged selectively apply a constant current signal to the mirror junction of that stage.

The initial attenuation stage may comprise a mirror junction, a mirror switch, a first mirror resistor connected between the mirror junction and the common rail and a second mirror resistor connected between the mirror junction and the mirror switch, the mirror switch being arranged to as selectively connect the second mirror resistor to either the mirror input or the common rail, the mirror junction being connected to a mirror terminal of the first mirror resistor of one of the attenuation stages, the terminal being connected to no other junction of the attenuation stages.

Typically, the switch and the mirror switch of each attenuation stage and of the initial attenuation stage will be arranged so as to switch together, such that either the second resistor and the second minor resistor are connected to the common rail or the second resistor and the second mirror resistor are connected to the input and the mirror input resp cc tively.

Each current source may be provided with a current source switch which selectively connects the constant current signal to either the junction or the mirror junction of the attenuation stage of the current source. Each current source may draw the current signal from the common rail.

Each first resistor and second resistor will necessarily have a resistance; the resistance of each second resistor will typically be twice the resistance of the first rcsistor of that stage, (typically apart from the first resistor and the first mirror resistor of the initial attenuation stage, which will have the same resistance as the corresponding second resistor or second mirror resistor); typically, the same will also be true of the first and second mirror resistances. Typically, all of the resistances of the first resistors will be substantially equal, as will all of the first mirror resistances (apart from the first resistor and first mirror resistance of the initial attenuation stage), and all of the resistances of the second resistors will be substantially equal, as will all of the second mirror resistances.

The circuit may be provided with a termination resistor, connected between the output and the con-imon rail, and typically also a mirror termination resistor, connected between the mirror output and the common rail. The resistance of the termination resistor and the mirror termination resistor may be the same as the resistance of the second resistor and the second mirror resistor of the terminal attenuation stage respectively.

As such, the circuit may define an R-2R ladder attenuator, with the added benefit of a controllable DC offset.

Typically, the current signal from each of the current sources may be of equal current, although this is not essential: the current signals can be different, in order to vary the range of DC offsets available.

According to a second aspect of the invention, there is provided a radio frequency transmitter circuit, comprising a signal source, a local oscillator, a mixer and an attenuation circuit according to the first aspect of the invention, in which the signal source is coupled to the input of the attenuation circuit; and the output of the attenuation circuit and the local oscillator are coupled to the mixer.

Thus, this provides a use of the circuit of the first aspect of the invention in a radio frequency transmitter circuit.

The transmitter circuit may comprise a control circuit, arranged to control at least one of the switches, the mirror switches, the current source and the current source switches in order to reduce the DC. offset in a signal received by the attenuation circuit from the signal source.

The circuit may be, or be pail of, a low noise amplifier.

According to a third aspect of the invention, there is provided a method of using an attenuation circuit, the attenuation circuit being in accordance with the first aspect of the invention, the method comprising operating the circuit so as to reduce or minimise the DC offset in a signal applied to thc input of the attenuation circuit.

Thus, the method will provide for control of both the DC offset and the attenuation of the signal, in a circuit that makes efficient use of components.

The step of operating the circuit so as to reduce or minimise the DC. offset may comprise selectively operating the current source switches or the current sources in order to gcneratc a DC offset for the signal. Thc DC offset for thc signal may comprise an inversion of an approximation to the DC. offset in the signal and, as such, may be the closest discrete value of the DC offset achievable with the attenuation circuit to the actual DC offset in the signal, but with the opposite sense.

Typically, the method will also comprise selecting the level of attenuation required for thc signal by operating at lcast onc of thc switches and the mirror switchcs.

There now follows, by way of example only, description of an embodiment of the invention, described with reference to the accompanying drawings, in which: Figure 1 shows a circuit diagram depicting a combined programmable attenuator with variable DC offset according to an embodiment of the invention; and Figure 2 shows a schematic diagram of a radio frequency transmitter circuit using the circuit of Figure 1.

A combined programmable attenuator with variable DC offset according to an embodiment of the invention is shown in Figure 1. Whilst the circuit could equally well be provided as a single-ended circuit, this embodiment is for use with differential signals, and so has two inputs V1± and V, which will be provided with the same signal, but of opposing polarities. Similarly, the circuit is provided with differential outputs Vuat i and The circuit comprises four attenuation stages 1, 2, 3, 4, connected in sequence so providing a four-bit attenuator with 2=1 6 different attenuation values. The stages comprise initial attenuation stage I, intermediate attenuation stages 2, 3 and terminal attenuation stage 4.

Each of the intermediate 2, 3 and terminal 4 attenuation stages coniprises a pair of first resistors Sb, Sb'; Se, Se'; Sd, Sd'. Each first resistor of each pair is connected to one of a pair ofjunctions 6b, 6b'; 6e, 6e'; 6d, 6d' of that stage. Each junction 6b, 6b'; 6c, 6c'of each of the intermediate stages 2, 3 is connected to one of the first resistors Sc, Sc': 3d, 3d' of the subsequent attenuation stage 3, 4, so that each of the pairs of first resistors form a chain of resistors in series. The junctions od, 6d' of the terminal attenuation stage 4 arc each connected to one of the outputs V0_, V0.

Each of the intermediate 2, 3 and terminal 4 attenuation stages also comprises a pair of second resistors 7b, 7b'; 7c, 7c'; 7d, 7d'. Each of the second resistors is connected to one of the junctions 6b, 65': 6c, 6c': 6d, 6d' of that stage 2, 3, 4 and to one of a pair of switches Sb, Sb'; Sc, Sc'; Sd, Sd' of that stage 2, 3, 4. Each switch selectively connects the relevant second resistor either to a common rail V or to one of the inputs V and V. The switches Sb, Sb'; Sc, Sc'; Sd, Sd' of each pair switch together, such that the second resistors of one stage 2, 3, 4 are connected either both to the respective inputs V+ or V or both to the common rail Vc.

The initial attenuation stage I also coniprises a pair of junctions 6a, 6a' and a pair of second resistors 7a, 7a'. Each of the second resistors 7a, 7a' is connected to one of the junctions 6a, 6a' and to one of a pair of switches Sa, Sa'. As with the other stages 2, 3, 4, each of the switches selectively connects the second resistor 7a, 7a' to either the common rail Vcm or to one of the inputs Vj, and A pair of first resistors 5a, 5a' is also provided; however, in this case they each connect one of the junctions 6a, 6a' to the common rail Vc1.

A pair of termination resistors 9, 9' connects the outputs V0+, V0 to the common rail Given that each of the second resistors 7a, 7a'; 7b, 7b'; 7c, 7c'; 7d, 7d', the termination resistors 9, 9' and the first resistors 5a, 5a' of the initial attenuation stage has a resistance of 4.8 kiloohrns, and the remaining first resistors Sb, Sb'; Sc, Sc'; Sd, Sd' have a resistance of 2.4 kiloohms, this arrangement defines a R-2R ladder attenuator, where the expected signal attenuation ranges from 26.6 dB to 4.08 dB depending on the setting of the switches Sa, Sa'; Sb, Sb'; Sc, Sc'; Sd, Sd'. This is a known technology and is well docuniented as a digital to analogue convertor, or as a signal attenuator (see, for example, B. D. Smith, "Coding by Feedback Methods," Proceedings of the I. R. F., Vol. 41, August 1953, pp. 1053-1058., or US Patent 4 491 825).

In order to provide the DC offset, each of the attenuation stages 1, 2, 3, 4 are provided with a current generator lOa, lOb, lOc, lOd each having an associatcd switch ha, ii b, lie, lid. This switch allows a constant current signal, drawn from the common rail Vcm, to be applied selectively to either one junction 6a, 6b, 6c, 6d of that stage or the other junction 6a', 6b', 6c', 6d' or that stage.

In addition, a further current source 12 is provided, which draws current from the common rail V1fl and provides that at the junction 6a on thc V-side of the initial attenuation stage.

When the switches 11 a, 1 ib, 1 Ic, 11 d are not selected (as shown), then the junctions 6a, 6b, 6c, 6d are set to the common mode voltage Vc1,, assuming there is no signal on V1. and V. In this case, the opposing signals at junctions at 6a', 6b', 6c', 6d' are each pulled below the common mode voltage Vc11, in addition to the voltage offset caused by prior and subsequent stages.

For the purpose of further explanation, it is assumed that the constant current signal from cach of the current sourccs ba, lob, lOc, lOd, 12 are all equal and are, for the

S

sake of argument, 1.25 mieroamperes. The resistor values shown are set to provide appropriate network impedance. Using the fact that the ladder is an R/2R network, the value of ft in this case is 2.4 kiloohms. From the prospective of the current source (say lob), then the network looks like 4.5 kiloohms in both directions (towards resistor Sb and towards resistor Sc), and also has R4 in parallel. This is the resistance that the current source is loaded which is 3ft/2 of 1.6 kiloohms.

For the case of switch ha applying the current at junction 6a (but the other switches ii b, lie, lid applying their respective signals to junctions 6b', 6c', 6d'), a 2 niillivolt offset (1.25 RA * .6 kfl) is applied at the junction whilst junction 6a' is set to the common mode voltage, V. This offset signal on Vi is attenuated by 6 dB per stage as expected in a normal R/2R ladder network. As a result, a 0.25 mV offset is obtained at the output Vat i relative to At the same time, junction 6b' has an offset current applied to it, giving a 2 mV offset.

This reflects as an offset of 0.5 rnV at the output Node 6c' also has an offset current applied to it, giving a 2 mV offset. This reflects as an offset of I mV at the output and V0 has an offset current applied to it, giving a 2 mV offset. The total offset at the output of V0 is then 2 + I + 0.5 mV = Vurn -3.5 mY.

The differential voltage between V0 and V01 is then (V-0.25) -(Vcm-3.5) mV = 3.25 mV.

A similar analysis may be conducted for other switch settings.

Note that without further current source, the minimum differential offset occurs when switch lid is switched to junction 6d and switches 1 Ia, 1 Ib, 1 Ic are switched to junctions 6a', 6b', 6c' respectively. This gives: = Vc1 -2 mV Vcrn1 = Vcm -(1 +0.5 + 0.25) mV -V0 = -2 mY + 1.75 mV = -0.25 mY In the opposite condition, S4 switch lid is switched to junction 6d' and switches 1 la, ii b, lie are switched to junctions 6a, 6b, 6e respectively, giving: V0-= V11 -(1 +0.5 + 0.25) mV Vout = Vcm -2 my -= -175 mV + 2 mV = 0.25 mV This shows that a zero offset is not possible. By adding the additional offset from further current source 12, then a fixed offset of 0.25 mV is added to the network, permitting a zero offset case to be set. The penalty for this is loss of symmetry at maximum switch settings, with all the switches set one way or the other as follows: = -(2 +1 +0.5 + 0.25 + 0.25) mV V c-,ut-= VCIT1 V01 -= -4 mV And = -(0.25) mV Vcrn1 = Vcm -(2 +1 +0.5 + 0.25) mV -= 3.5 my Including the fixed offset current then changes the range from -4 to +3.5 mV offset, instead of+ 3.5 mV without it.

The range may be cxtendcd by making any of the currents variable, with the accuracy split between the accuracy of the current scaling and the resistor network. By simply doubling the current in current source lOd, for example, extends the range from -4 to +3.5 mV to -8 to +7.5 mV. Similarly, binary switching this current (by enabling the current source lOd to provide 2"I for integer n) can give a range -16 to + 15.5 mV.

Adding furthcr sections can increase the resolution (-16 to +15.75, -16 to +15.875 ctc). Similarly, binary weighting the current source can extend the resolution of the offset control without affecting the resolution of the signal attenuator.

A radio frequency transmitter circuit which uses the circuit of Figure 1 is shown schematically in Figure 2 of the accompanying drawings. In this circuit, a differential signal is received at input 20 (all inputs, outputs and signals are differential in this embodiment and so will comprise two complementary signals, but for the purposes of description, only a single signal and terminal is shown in each case). This is passed to 21 attenuator circuit according to Figure 1.

The attenuator circuit 21 is controlled by a control circuit 22, which monitors the DC offset and the overall amplitude of the signal, and sets the attenuation (using switches 8a, Sa'; Sb, Sb'; Sc, Sc'; Sd, Sd') and the required DC offset (that is, the closest value of opposite sign to the monitored DC offset achievable, using switches 1 la, 1 ib, lie, 1 id) accordingly. This is achieved using a single circuit 21, rather than the three circuits proposed in the example given above.

The attenuated and DC-offset-corrected signal is passed to a mixer 23, where it is mixed with a signal from a local oscillator 24, so as to up-mix the signal to a higher frequency. This signal is passed to an output 25, where it can be either transmitted or passed through further frequency conversion, amplification or other stages as necessary.

Claims

CLAIMS1. An attenuation circuit for attenuating a signal whilst providing a controllable DC offset, comprising an input, an output, a common rail and a plurality of attenuation stages, each attenuation stage comprising: a switch; a first resistor which is, except in a terminal one of the attenuation stages, connected at a junction of that stage in series to the first resistor of a subsequent one of the attenuation stages, the first resistor of the terminal attenuation stage being connected at a junction of that stage to the output; a second resistor connected between the junction of that attenuation stage and the switch; the switch being arranged to as selectively connect the second resistor to either the input or the common rail; in which each attenuation stage is provided with a current source arranged to selectively apply a constant current signal to the junction of that stage.
2. The circuit of claim 1, comprising an initial attenuation stage comprising a junction, a switch, a first resistor connected between the junction and the common rail and a second resistor connected between the junction and the switch, the switch being arranged to as selectively connect the second resistor to either the input or the common rail, the junction being connected to a terminal of the first resistor of one of the attenuation stages, the terminal being connected to no other junction of the attenuation stages.
3. The circuit of claim 2 may further be provided with an additional current source arranged to apply a constant current signal to the junction of the initial attenuation stage.
4. The circuit of any preceding claim, comprising a mirror input and a mirror output, with each attenuation stage comprising: a mirror switch; a first mirror resistor which is, except for a terminal one of the attenuation stages, connected at a mirror junction of that stage in series to the first mirror resistor of a subsequent one of the attenuation stages, the first mirror resistor of the terminal attenuation stage being connected at a mirror junction of that stage to the mirror output; a second mirror resistor connected between the mirror junction of that attenuation stage and the mirror switch; the minor switch being arranged to as selectively connect the second mirror resistor to either the mirror input or the common rail, in which the current source of each stage is arranged selectively apply a constant current signal to the mirror junction of that stage.
5. The circuit of claim 4 as dependent on claim 2, in which the initial attenuation stage comprises a mirror junction, a mirror switch, a first mirror resistor connected between the mirror junction and the common rail and a second mirror resistor connected between the mirror junction and the mirror switch, the mirror switch being arranged to as selectively connect the second mirror resistor to either the mirror input or the common rail, the mirror junction being connected to a mirror terminal of the first mirror resistor of one of the attenuation stages, the terminal being connected to no other junction of the attenuation stages.
6. The circuit of claim 4, in which the switch and the mirror switch of each attenuation stage are arranged so as to switch together, such that either the second resistor and the second mirror resistor are connected to the common rail or the second resistor and the second minor resistor are connected to the input and the mirror input respectively.
7. The circuit of any of claims 4 to 6, in which each current source is provided with a current source switch which selectively connects the constant current signal to either the junction or the mirror junction of the attenuation stage of the current source.
8. The circuit of any preceding claim, in which each current source draws the current signal from the conimon rail.
9. The circuit of any of claims 4 to 7, or of claim 8 as dependent on claim 4, provided with a termination resistor, connected between the output and the common rail, and a mirror termination resistor, connected between the mirror output and the common rail.
10. The circuit of any preceding claim, iii which the current signal from each of the currcnt sources is of equal current.
11. The circuit of any of claims I to 9, in which the current signals from each of the current sources are not all equal.
12. A radio frequency transmitter circuit, comprising a signal source, a local oscillator, a mixer and an attenuation circuit according to any preceding claim, in which the signal source is coupled to the input of the attenuation circuit; and the output of the attenuation circuit and the local oscillator arc coupled to the mixer.
13. The circuit of claim 12, comprising a control circuit, arranged to control at least one of the switches, the mirror switches, the current source and the current source switches in order to reduce the DC offset in a signal received by the attenuation circuit from the signal source.
14. A method of using an attenuation circuit, the attenuation circuit being in accordance with any of claims I to 11, the method comprising operating the circuit so as to reduce or minimise the DC offset in a signal applied to the input of the attenuation circuit.
15. The method of claim 14, in which the step of operating the circuit so as to reduce or minimise the DC offset comprises selectively operating the current source switches or the current sources in order to generate a DC. offset for the signal.
16. The method of claim 15, in which the DC offset for the signal comprises an inversion of an approximation to the DC offset in the signal
17. The method of claim 16, in which the DC offset for the signal is the closest discrete value of the DC offset achievable with the attenuation circuit to the actual DC offset in the signal, but with the opposite sense.
18. The method of any of claims 14 to 17, comprising selecting the level of attenuation required for the signal by operating at least one of the switches and the mirror switches.
19. An attenuator circuit substantially as described herein with reference to and as illustrated in Figure 1 of the accompanying drawings.