GB2500625A

GB2500625A - Diversity receiver using bit reliability indications when processing three or more copies of a packet

Info

Publication number: GB2500625A
Application number: GB1205357.5A
Authority: GB
Inventors: Mounir Achir; Philippe Le Bars
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2012-03-27
Filing date: 2012-03-27
Publication date: 2013-10-02
Anticipated expiration: 2032-03-27
Also published as: GB2500625B; GB201205357D0

Abstract

A diversity receiver receiving three or more copies of a data unit (e.g. packet) 707 determines respective bit reliability indications for corresponding bits of the received data units 708, each bit reliability indication being indicative of potential corruption of the respective bit by a transmission error. A bit value that is in a minority of the bit values of the corresponding bits is selected in the case where its respective reliability indication is indicative of a better reliability than the others, i.e. a minority bit value is chosen when it is deemed to be more reliable than a majority decision rule. When two copies of a data unit are received 703, a data unit is chosen on the basis of data unit reliability indications 704, 705. The data units are encoded by an error correcting code having a set of parity check conditions, e.g. low-density parity-check code (LDPC), and reliability indications are obtained based on the outcome of verification of the parity check conditions.

Description

METHOD AND DEVICE FOR OBTAINING A DATA UNIT FROM A

PLURALITY OF RECEIVED DATA UNITS

The present invention concerns a method and a device for obtaining a data unit from a plurality of received data units. The invention further relates to a method and device for obtaining a reliability indication of a symbol of a data unit comprising a plurality of symbols.

Communication channels, in particular wireless channels, used to transport data packets are often subject to channel noise and other sources of interference. As a result, errors may be introduced during the transmission of data packets from a transmitter to a receiver. Error detection and error correcting techniques are often employed to enable reliable delivery of digital data over communication channels. Error detection techniques enable errors to be detected, while error correcting techniques are applied to enable recovery of the originally transmitted data. Such techniques include for example encoding schemes such as Low Density Parity Check (LDPC) code, Turbo codes, and the like.

Some error detection and correction techniques add some redundancy (i.e., some extra data) to a data packet, which may be used by a receiving device to verify the reliability of the delivered data packet, and to recover any data containing errors. Error-detection and correction schemes can be either systematic or non-systematic: In a systematic scheme, the transmitter sends the original data, and attaches a fixed number of check bits (or parity data), which are derived from the data bits by some deterministic algorithm. If only error detection is required, a receiver can simply apply the same algorithm to the received data bits and compare its output with the received check bits; if the values do not match, an error has occurred at some point during the transmission. In a system employing non-systematic code, the original message is transformed into an encoded message that has at least as many bits as the original message.

For transmission channel estimation the Shannon theory states that for a transmission channel an encoding scheme exists that enables a given bitrate to be obtained with reliable communication. In general, encoding schemes are evaluated by considering that data bits and parity bits transit through the same channel.

A known simple error detection scheme is the single parity check, which adds an extra bit to a data message. The parity bit may be a 0 or a 1 depending on the number of ones in the message. The additional bit added to each message ensures that the number of is in each transmitted codeword is even.

Assuming that the following message is to be encoded with the single parity check code: 110011. The number of ones is even and thus the parity bit should be 0; the codeword to be sent is theni 100110. It is easy to see that the codeword of the single parity check code satisfies the following condition: cO + ci + c2 + c3 + c4 + c5 + c6 = 0 (where + represents the exclusive Or operation).

One measure of the ability of a code to detect errors is the minimum distance. The Hamming distance between two codewords is defined as the number of bit positions in which they differ. For example, the codewords 1100110 and 0101110 differ in positions 1 and 4 so the Hamming distance between them is 2. The minimum distance of a code, dmin, is defined as the smallest Hamming distance between any pair of codewords in the code. For the even parity code dmin = 2, so the corruption of two bits in a codeword can result in another valid codeword and will consequently not be detected.

LDPC codes are parity-check codes with the requirement that H is low-density, so that the vast majority of the matrix elements are zeros. A parity-check matrix is regular if each bit of a codeword (generally called a variable bit)is included in a fixed number of parity checks, noted Nc, and each parity-check equation contains a fixed number of variable bits, noted Nv. If an LDPC code is described by a regular parity-check matrix it is called a (Nc,Nv)-regular LDPC code otherwise it is an irregular LDPC code.

An LDPC code can be seen as a variable set that satisfies a set of constraints. A graph can be constructed to represent the relationship between the variables and the constraints. Variables will be represented by a circle and constraints by a square.

For example: defining a binary linear code C by its parity check matrix.

1 0 0 1 0 0 1 0 1 0 0 1 0 0 1: C is the set of all binary 6-tuples x=[xl,x2,x3,x4,x5,x6,x7,x81 that satisfies H.xt = 0. Verifying that X belongs to C is equivalent to verifying the condition [xl +x2+x3=0], [x4+x5+x6=0], [xl ÷x4÷x7=0] and [x2+x5+x8=0]. The constraint here is to satisfy several parities. The function associated with the constraint is

the sum in GF(2), i.e. Galois Field.

In wireless mesh networks, made up of source nodes, relay nodes and destination nodes, multiple copies (often referred to as redundant packets) of the same data packet can be received from a transmitter via different radio channels. A single destination node can receive different data packets originating from the same initial data packet with each data packet being protected, for example, by an LDPC code.

A relay node of a wireless mesh network can retransmit the data packet in the same form as it was received by the Amplify and Forward technique. However, some relay nodes may also decode the received data packet in order to correct potential errors introduced in the first stage of the transmission. In such a case, the relay node obtains a new copy of the original received data packet that can be encoded and sent to the destination node; this retransmission method is called the Decode and Forward technique. The "Amplify and Forward" and the "Decode and Forward" techniques can be used to avoid packet losses that may frequently occur in wireless communications.

The destination node may receive several copies of the original packet sent by the source node. Hence, one challenging technical problem is how the source node should process the original packet copies to obtain a data packet containing a minimum number of errors The present invention has been devised to address one or more of the foregoing concerns.

According to a first aspect of the invention there is provided a method of obtaining a data unit from a plurality of received data units, each of the received data units originating from the same initial data unit transmitted over respective transmission paths, the method comprising: in the case where at least three data units are received determining respective bit reliability indications for corresponding bits of the received data units, the corresponding bits being positioned at the same bit position in each of the received data units; each bit reliability indication being indicative of potential corruption of the respective bit by a transmission error; selecting, based on the determined bit reliability indications, a bit value, from among the bit values of the corresponding bits, wherein a bit value that is in minority of the bit values of the corresponding bits is selected in the case where its respective bit reliability indication is indicative of a better reliability than the reliability indicated by the bit reliability indications of the bit values of the other corresponding bits; and providing a data unit in which the bit at the corresponding bit position has the selected bit value.

Such a method enables a decrease in the bit error rate to be obtained compared to known methods.

In an embodiment, a bit reliability indication is determined for each bit of a received data unit for comparison with a bit reliability indication of a corresponding bit of at least one other received data unit.

In an embodiment, a prior step of determining whether the number of data units received is one, two or three is included in order to determine further processing steps.

In an embodiment, in the case where it is determined that one data unit is received, the obtained data unit corresponds to the received data unit.

In an embodiment, in the case where it is determined that two data units are received the method includes determining a respective data unit reliability indication for each received data unit, and selecting, based on the determined data unit reliability indications, a data unit from among the received data unit as the obtained data unit.

In an embodiment, each data unit reliability indication Cq(j) is determined according to the expression: Cq) sum (mod(H. b(1:N,j),2) b(1:N,j) is a column vector; ""takes two values from {1,2,3}; ]" corresponds to the index of the data unit; mod(x,2) is the x modulo 2 value; Cqj) corresponds to the number of false checks; H is the parity check matrix of the used LDPC code.

and the data unit reliability indication with the lowest Cqj'j) is selected.

In an embodiment, in the case where at least three data units are received each bit reliability indication Cqj) for each bit i of packet j is determined according to the expression: parity checkU) = mod(I-I. b(1:Nj), 2) Cq(4j) = sum(H(J) . parity_check(/)) where: parity_check(j) : is the parity check column vector with (N-K) bits this vector equals the null vector if b(1:N,j) is a codeword; H is the parity check matrix (N-K) rows and N columns; Mod(x, 2) is the x value modulo 2; Ht,j) is the columnj of the matrix H; Ht,j) parity_check(j) is an element to element multiplication (H(:,j) and parity check(j) are both column vectors). a

In an embodiment, a step of applying a majority decision rule is included to derive the value of the Rh bit of data unitj if the following condition is not satisfied: (Cq,j) = 0) AND (Cqk) != 0; for anyk!=j) In an embodiment, the value of the Rh bit of data unit j is derived according to the expression: c(i) = roundUbO 1)+bOI, 2) +bO, 3))/3 to provide selected bit value cO) where round(.) is a function for approximating a real value to the nearest integer value.

In an embodiment, the selected bit value cO) = b(i,j) in the case where the condition (Cq,j) = 0) AND (Cq(i,k) 0 is satisfied for anyk!=j).

In an embodiment, each of the plurality of received data units is encoded by means of an error correcting code having a set of parity check conditions, and each reliability indication is obtained based on the outcome of verification of the given parity check conditions on the corresponding data bit.

According to a second aspect of the invention there is provided a network device for obtaining a data unit from a plurality of received data units, each of the received data units originating from the same initial data unit transmitted over respective transmission paths, the device comprising: determining means for determining respective bit reliability indications for corresponding bits of at least three received data units, the corresponding bits being positioned at the same bit position in each of the received data units; each bit reliability indication being indicative of potential corruption of the respective bit by a transmission error; selection means for selecting, based on the determined bit reliability indications, a bit value, from among the bit values of the corresponding bits, the selection means being configured to select a bit value that is in minority of the bit values of the corresponding bits in the case where its respective bit reliability indication is indicative of a better reliability than the reliability indicated by the bit reliability indications of the bit values of the other corresponding bits; and data unit provision means for providing a data unit in which the bit at the corresponding bit position has the selected bit value.

In an embodiment, the determining means is configured to determine a bit reliability indication is determined for each bit of a received data unit for comparison with a bit reliability indication of a corresponding bit of at least one other received data unit In an embodiment, the device includes means for determining whether the number of data units received is one, two or three in order to determine further processing steps.

In an embodiment, the data unit provision means is configured to provide a data unit that corresponds to the received data unit in the case where it is determined that one data unit is received.

In an embodiment, the determining means is further configured to determine a respective data unit reliability indication for each received data unit, in the case where it is determined that two data units are received and the selection means is configured to select, based on the determined data unit reliability indications, a data unit from among the received data unit as the obtained data unit.

In an embodiment, the determining means is configured to determine each data unit reliability indication Cq) according to the expression: Cq) = svm(mod(H. b(1:N,j),2) b(1:N,j) is a column vector; ]" takes two values from {1,2,3}; "j" corresponds to the index of the data unit; mod(x,2) is the x modulo 2 value; Cq(j) corresponds to the number of false checks H is the parity check matrix of the used LDPC code and the data unit reliability indication with the lowest Cq(j) is selected.

In an embodiment, the determining means is configured to determine each bit reliability indication Cq(iJ) for each bit i of packet j, in the case where at least three data units are received, according to the expression: parity_checko) = mod'H. bi1:N,j, 2) Cq(iJ) = sum(H(,j) parity_checkij)) where: parity_check(j) is the parity check column vector with (N-K) bits; this vector equals the null vector if b(1:N,j) is a codeword; H is the parity check matrix (N-K) rows and N columns; Mod(x, 2) is the x value modulo 2; HCj) is the column j of the matrix H; H,j) . parity_check(j) is an element to element multiplication (Ht,j) and parity_check(j) are both column vectors).

In an embodiment, the determining means is configured to apply a majority decision rule to derive the value of the ith bit of data unit j if the following condition is not satisfied: (Cqj) = 0) AND (Cqk) != 0; for any k!=j) In an embodiment, the value of the ith bit of data unit j is derived according to the expression: cU) = raundUbO, 1)+bU,2)+b03))/3 to provide selected bit value cO) where round(.) is a function for approximating a real value to the nearest integer value.

In an embodiment, the selected bit value c(i) = b(i,j) in the case where the condition (Cq('i,j) 0) AND (Cqk) != 0 is satisfied for any k!=j) In an embodiment, each of the plurality of received data units is encoded by means of an error correcting code having a set of parity check conditions, and the determining means is configured to determine each reliability indication based on the outcome of verification of the given parity check conditions on the corresponding data bit.

According to a third aspect of the invention there is provided a method of obtaining a reliability indication of a symbol of a data unit comprising a plurality of symbols, the reliability indication being indicative of potential corruption of the respective bit by a transmission error and the data unit having being encoded by an error correcting code, the method comprising verifying the fulfilment of a set of parity check conditions of the error correcting code by one or more of the plurality of symbols including the said symbol; obtaining, for the said symbol, a reliability indication based on the outcome of the verification of the preceding step.

Such a method provides improved reliability indications for data recovery. Moreover less overhead is required for transmission of reliability indication data. The symbol of the data unit in some embodiments of the invention may be a bit.

In an embodiment, a respective reliability indication is determined for each symbol of the data unit for comparison with a reliability indication of a corresponding symbol of at least one other data unit.

In an embodiment the method includes selecting, for each symbol, based on the reliability indications, a symbol value, from among the symbol values of the corresponding symbols, and providing a data unit in which the symbols have the selected symbol values.

A further aspect of the invention provides a network device for obtaining a reliability indication of a symbol of a data unit comprising a plurality of symbols, the reliability indication being indicative of potential corruption of the respective symbol by a transmission error and the data unit having being encoded by an error correcting code, the device comprising means for verifying the fulfilment of a set of parity check conditions of the error correcting code by one or more of the plurality of symbols including the said symbol; means for obtaining, for the said symbol, a reliability indication based on the outcome of the verification of the preceding step.

In an embodiment the device includes: means for selecting, for each symbol, based on the reliability indications, a symbol value, from among the symbol values of the corresponding symbols, and means for providing a data unit in which the symbols have the selected symbol values.

At least parts of the methods according to the invention may be computer implemented. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit", "module" or "system". Furthermore, the present invention may take the form of a computer program product embodied in any tangible medium of expression having computer usable program code embodied in the medium.

Since the present invention can be implemented in software, the present invention can be embodied as computer readable code for provision to a programmable apparatus on any suitable carrier medium. A tangible carrier medium may comprise a storage medium such as a floppy disk, a CD-ROM, a hard disk drive, a magnetic tape device or a solid state memory device and the like. A transient carrier medium may include a signal such as an electrical signal, an electronic signal, an optical signal, an acoustic signal, a magnetic signal or an electromagnetic signal, e.g. a microwave or RF signal.

Embodiments of the invention will now be described, by way of example only, and with reference to the following drawings in which:-Figure 1 is a schematic diagram of a wireless communication network in which one or more embodiments of the invention may be implemented; Figure 2 is a schematic block diagram of an antenna that may be used in the context of the invention; Figures 3A and 3B are flow charts illustrating steps of a method of encoding and decoding respectively of data packets according to one or more embodiments of the invention; Figure 4 is a flow chart illustrating steps of a method of data packet encoding according to one or more embodiments of the invention; Figure 5 is a flow chart illustrating steps of a method of data packet transmission according to one or more embodiments of the invention; Figure 6 is a flow chart illustrating steps of a method of data packet reception and decoding according to one or more embodiments of the invention; Figure 7 is a flow chart illustrating steps of a method of data packet r decoding according to an embodiment of the invention; and Figure 8 is a schematic block diagram of a network device which may be used in one or more embodiments of the invention.

Figure 1 illustrates a wireless communication network 100 in which one or more embodiments of the invention may be implemented. The wireless communication network 100 comprises a plurality of wireless communication devices.

Wireless communication network 100 comprises a wireless mesh network or a point to point wireless communication network in which several copies of the same original data packet may be transmitted from a network node/device. For example, source node 101 is operable to transmit the same data packet at least three times using different antenna patterns. The data packets 113, 114 and 115 contain exactly the same data but are transmitted respectively with antenna pattern 103, 104 and 105. The transmission is considered to take place within a superframe that starts after a beacon signal 112.

Data packet 113 sent using antenna pattern 103 is reflected by the wall 109 before reaching the receiver node 102. The receiver node 102 picks up the radio signal if there is no shadowing. The same applies to data packets 114 and 115 that are transmitted respectively by the antenna patterns 104 and 105 and reflected by the walls 110 and 111. The receiver node can use an omni-directional antenna operable to receive all the packets in the superframe or can apply a respective antenna pattern may be applied for each packet as illustrated in Figure 1. i.e. the receiver node 102 applies antenna patterns 106, 107 and 108 for the data packets 113, 114 and 115 respectively.

Each data packet sent by the source node 101 may be encoded by applying LDPC channel coding (Low Density Parity Check). At the end of each superirame the destination node 102 receives three copies of the same original data packet and applies a combination scheme in order to generate the original data from the three copies. The aim is to correct the erroneous bits introduced by the radio communication channel. The destination node decodes each data packet after its reception and applies the combination scheme after decoding the third and last packet. Optimal decoding of each packet is obtained by applying the Belief Propagation decoding Algorithm (BPA). In embodiments of the present invention, the combination of the data units (see figure 7) does not use the believe propagation algorithm but uses only the specificity of the LDPC codewords.

Smart antennas provide directional transmissions and/or receptions of radio signals. The directions of transmission are selected based on complex coefficients applied in the antenna that enables some directions to be cancelled and other directions to be amplified. Figure 2 illustrates an example of a smart antenna that may be used in the context of embodiments of the invention. The smart antenna 200 of this embodiment includes five antenna elements 201, 202, 203, 204 and 205. The antenna elements 201, 202, 203, 204 and 205 receive radio signals transmitted from source node 101 and apply respective coefficients values, wi, labelled 206 for the received signals. The different output signals are then summed together by summing device 212. The obtained signal will corresponds to the signal received from the desired directions.

The antenna complex coefficients wi to w5 can be computed by the following equation: W = V.A(A" .A)' where A is a smart antenna matrix and corresponds to (2N÷1).(2N+1) square matrix. (2N+1) is the number of elements of the antenna. The element (i,ki-1) of the matrix, i from ito 2N+1 and k from 0 to 2N is computed according to the following formula: A(i, k + i) = exp(j(k -N)ir. sin(01)) V is a vector that contains (2N+1) elements that take the values 0 or 1. 0 for an unwanted direction, and 1 for a desired direction (directions among the 0, angles).

An example of vector V when N is equal to 2 is: v=(1,o,o,o,o) In the above example, there is one desired direction (0) and all the remaining directions are unwanted (i.e. from 02 toO11). The complex coefficients can be stored within the ROM 840 of the communication device 800 of Figure 8.

An overall method for encoding and transmission of data packets according to at least one embodiment of the invention is illustrated in Figure 3A and an overall method for decoding and combination of data packets according to at least one embodiment of the invention is illustrated in Figure 38.

In step 320 a transmitter of source node 101 applies an LDPC encoding 320 procedure to each data packet to be transmitted. This step will be described in more detail with reference to Figure 4 The LDPC code may, for example, be that specified by the first parity check matrix (with a code rate equal to 1/2) of Figure 167 in document "Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPAN5) Amendment 2: Millimeter wave based alternative Physical Layer Extension. Approved 11 September 2009". In such a case, each codeword contains 672 bits. After computation of the codewords of the data packet, the transmitter applies a repetition code in step 330 by transmitting the same data packet via different directions (using different antenna configurations). Step 330 will be described in more detail with reference to Figure 5. The receiver node 102 receiving a transmitted data packet applies the reverse operation. With reference to Figure 3B the receiver starts by applying a LDPC decoding process in step 360 by using a Believe Propagation Algorithm (BPA). This step will be described in more detail with reference to Figure 6. Next, repetition code' decoding is applied in step 370 by combining the different received copies of the data packet. Step 370 implements method 800 which will be described in more detail with reference to Figure 7.

Figure 4 illustrates a method of LDPC encoding according to an embodiment of the invention. The transmitter of source node 101 applies LDPC encoding to each bit of K bits received in step 420 from an upper layer and generates, in step 430, N bits that form the data packet to be transmitted by applying LDPC encoding. LDPC encoding is known, simple to implement and involves applying a matrix multiplication (Multiplication between the generation matrix of the code and the uncoded word). LDPC encoding function perlorms XOR operations between the bits of the packet to be encoded and the bits of the generator matrix.

Figure 5 illustrates a method for transmitting data packets between network entities according to an embodiment of the invention. Steps of a method of repetition code encoding are illustrated in the flow chart of Figure 5.

In the step 520, the transmitter of source node 101 receives from its LDPC encoder data packets having a length equal to a multiple of N bits (i.e. P.N bits).

The transmitter applies first antenna parameters to transmit a first copy of the P.N bits packet in step 530. The antenna parameters are stored in the ROM 840. In step 540, the transmitter applies second antenna parameters before transmitting a second copy of the data packet of P. N bits via the radio channel.

The second antenna parameters are also stored in the ROM 840. And finally, in step 550, a third copy of the data packet of P.N bits is transmitted through a third channel (spatial diversity).

Figure 6 illustrates a method for receiving and decoding packets in accordance with an embodiment of the invention. The packet reception/decoding procedure is performed in two steps by the receiver device.

In a first step antenna parameters are applied to receive the electromagnetic signal for each copy of the data packet transmitted and the second step is to apply the believe propagation algorithm (BPA) to correct erroneous bits. In step 620 a first set of antenna coefficients of the receiver are applied in order to receive the first copy of the data packet. In step 630 erroneous bits are corrected by applying LDPC decoding. In step 640 a second set of antenna coefficients of the receiver are applied in order to receive the second copy of the data packet. In step 650 erroneous bits are corrected by applying LDPC decoding. In step 660 a third set of antenna coefficients of the receiver are applied in order to receive the third copy of the data packet. In step 670 erroneous bits are corrected by applying LDPC decoding.

Figure 7 illustrates steps of a method of packets combination for decoding the repetition code according to an embodiment of the invention.

In some wireless conditions the receiver typically receives in the three copies of the original data packet with different errors patterns. Different error patterns imply that the three radio links are not correlated and this is one of the best conditions to obtain optimal decoding in some embodiments of the present invention. If only one copy of the data packet is received as detected by testing step 702 then the unique copy of the data packet is send to the upper layer in step 706. No combination is performed and the process can terminate in step 710.

If it is determined in step 702 that more than one data packet copy is received, it is then determined in step 703 if two copies of the data packet have been received. If it is determined in step 702 that two copies of the data packet have been received, a computation of a criterion quality considered as a reliability indication for each copy is performed in step 704. i.e. a criterion quality value is computed for each group of N bits corresponding to data packet copy.

This criterion quality value is computed as follows: Considering b(i,j) as being a vector of N bits corresponding to the data packet copy indexed byj. Knowing that bit index "i' varies from ito N. and "j" take two values from {1,2,3} since only two copies of the data packet have been received.

The criterion quality Cq(j) for the reliability indication is then computed in accordance with the following formula: CqQ) = sum(mod(H. b(1:N,j),2) where: b(1:N,j) isa column vector; mod(x,2) is the x modulo 2 value; Cq(j) corresponds to the number of false checks H is the parity check matrix of the used LDPC code In step 704 the copy indexed by j which has the lowest computed Cq(j), i.e. the best reliability, is selected.

i.e. Selected_copy_index = arg(min(Cq(j))), Selected_copy_index belongs to {1,2,3} When it is determined in step 707 that three copies of the data packet have been received, in step 708 a criterion quality value for each bit of each data packet copy is determined (rather than a criterion quality value for the whole data packet copy as is done when only two data packet copies are received). The criterion quality for each bit i of data packet j is computed as follows: parity_checkU) = mod(H. b(1:N,fl, 2) Cq(i,j) = sum(H(i,J) . parity_checkU)) where: parity_check(j) : is the parity check column vector with (N-K) bits this vector equals the null vector if b(1:N,j) is a codeword; H is the parity check matrix (N-K) rows and N columns; Mod(x, 2) is the x value modulo 2; H(:j) is the column j of the matrix H; H(:,j) . parity_checkQ) is an element to element multiplication (H(:,j) and parity_check'j) are both column vectors).

After computing Cq(i,j) for each bit of each data packet copy, a selection/combination algorithm is applied in step 709 in order to obtain a data unit of N bits for the transmitted data packet. The algorithm entails analyzing the criterion qualities Cq(j) of corresponding bits positioned at the same bit position (i.e. having the same i index) in each of the three received data packet copies.

In step 709 a majority decision rule is applied to derive the value of the ith bit (c(i)) of the data unit if the following condition is not satisfied: (Cq,j) = 0) AND (Cq, k) != 0; for any k!=j) i.e. for any two of the three data packet copies if bit i of one of the two data packet copies is equal to 0 AND corresponding bit i of the other of the two data packet copies is not equal to 0 then the majority decision rule is not applied.

In the case where the condition is not satisfied the majority decision rule enables the value of the ith bit (cifi) to be determined from the following formula: Ca) = roundUbO, 1)+bO,2.)+bU,311/3 where round(.) is a function that approximates a real value to the nearest integer value (ex: round(0.55) = 1 and round(0.45) = 0) When the condition (Cq(i,j) = 0) AND (Cq(i,k) != 0; for any k!=j) is satisfied then in step 709 the value of bit b(i,j) is selected for bit c(i). i.e.: c(i) = b(ij).

Step 709 may be summarized as follows: for i=1:N if (Cq('i,j) = 0) AND (Cqk) != 0; for any k!=j) Ca) = else = round((bO, 1)+bO,2,1+bO,3fl/3); end if end for Select packet C In step 709 the algorithm is applied for the N bits and a group data unit composed of N bits is generated and transmitted to the upper layer in step 706.

Embodiments of the present invention help to reduce the bit error rate obtained from by only using a majority decision rule.

Embodiments of the invention can be implemented on a reprogrammable processing device such as a PC, a DSP or microcontroller and the like, or on a dedicated computation machine (FPGA or ASIC). Figure 8 illustrates the modules of such a device that can be used to perform the functions of the embodiments of the invention described above. Module 813 comprises sub-modules 815, 816 814, and 817 configured to perform processes 400, 500, 600 and 700 of Figures 4 to 7 that correspond respectively to the method for packets encoding (channel coding -815), the method for packets transmission 816, the method for packets reception and channel decoding 814 and the method for packets combination 817.

The device further comprises an interlace between the CPU and the baseband part CPU IF 811, a data memory 812, a radio transmission circuit 818, a radio reception circuit 816, a CPU (Central Processing Unit) 820, a RAM (Random Access Memory) 830, a ROM (Read Only Memory) 840 and radio frequency (RF) transceiver 850.

Although the present invention has been described hereinabove with reference to specific embodiments, the present invention is not limited to the specific embodiments, and modifications will be apparent to a skilled person in the art which lie within the scope cf the present invention.

For instance, while the foregoing embodiment has been described with respect to the transmission of three copies of a data packet, it will be appreciated that embodiments of the invention may be applied in the case where more than three copies of a data packet are transmitted. Moreover, while in the described embodiments reliability indications are determined for data bits it will be appreciated that in other embodiments reliability indications may be determined for other forms of data symbols composing a data package.

Many further modifications and variations will suggest themselves to those versed in the art upon making reference to the foregoing illustrative embodiments, which are given by way of example only and which are not intended to limit the scope of the invention, that being determined solely by the appended claims. In particular the different features from different embodiments may be interchanged, where appropriate.

In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that different features are recited in mutually different dependent claims does not indicate that a combination of these features cannot be advantageously used.

Claims

CLAIMS1. A method of obtaining a data unit from a plurality of received data units, each of the received data units originating from the same initial data unit transmitted over respective transmission paths, the method comprising: in the case where at least three data units are received determining respective bit reliability indications for corresponding bits of the received data units, the corresponding bits being positioned at the same bit position in each of the received data units; each bit reliability indication being indicative of potential corruption of the respective bit by a transmission error; selecting, based on the determined bit reliability indications, a bit value, from among the bit values of the corresponding bits, wherein a bit value that is in minority of the bit values of the corresponding bits is selected in the case where its respective bit reliability indication is indicative of a better reliability than the reliability indicated by the bit reliability indications of the bit values of the other corresponding bits; and providing a data unit in which the bit at the corresponding bit position has the selected bit value.
2. A method according to claim 1 wherein a bit reliability indication is determined for each bit of a received data unit for comparison with a bit reliability indication of a corresponding bit of at least one other received data unit.
3. A method according to claim 1 or 2, further comprising a prior step of determining whether the number of data units received is one, two or three in order to determine further processing steps.
4. A method according to claim 3 wherein in the case where it is determined that one data unit is received, the obtained data unit corresponds to the received data unit.
5. A method according to claim 3 or 4 wherein in the case where it is determined that two data units are received the method includes determining a respective data unit reliability indication for each received data unit, and selecting, based on the determined data unit reliability indications, a data unit from among the received data unit as the obtained data unit.
6. A method according to claim 6, wherein each data unit reliability indication CqQ) is determined according to the expression: Cq(f) = sum(mod(H. b(1:N,j),2) b(1:N,j) is a column vector; mod(x,2) is the x modulo 2 value; Cq(j) corresponds to the number of false checks H is the parity check matrix of the used LDPC code and the data unit reliability indication with the lowest Cq(i) is selected.
7. A method according to any preceding claim wherein, in the case where at least three data units are received each bit reliability indication Cq(j) for each bit i of packet j is determined according to the expression: parity_check(j) = mod(H. b(1:N,j), 2) Cqj) = sum(H(;j) parity_check) where: parity_cbeck(j) : is the parity check column vector with (N-K) bits; this vector equals the null vector if b(1:N,j) is a codeword; H is the parity check matrix (N-K) rows and N columns; Mod(x, 2) is the x value modulo 2; H(:,j) is the columnj of the matrix H; H(:j). parity_check(j) is an element to element multiplication (H(:j) and parity_check(j) are both column vectors).
8. A method according to claim 7 comprising a step of applying a majority decision rule to derive the value of the ith bit of data unit j if the following condition is not satisfied: (Cq(i,j) = 0) AND (Cq(7,k) != 0; for any k!=j)
9. A method according to claim 8, wherein the value of the ith bit of data unit j is derived according to the expression: c(i) = round((bO 1)+b02)+bO,3D/3 to provide selected bit value c(i) where round(.) is a function for approximating a real value to the nearest integer value.
10. A method according to claim 8, wherein the selected bit value c(i) = b(i,j) in the case where the condition (Cq(i,fl = 0) AND (Cq(i,k) != 0 is satisfied for any k!=j).
11. A method according to any preceding claim wherein each of the plurality of received data units is encoded by means of an error correcting code having a set of parity check conditions, and each reliability indication is obtained based on the outcome of verification of the given parity check conditions on the corresponding data bit.
12. A network device for obtaining a data unit from a plurality of received data units, each of the received data units originating from the same initial data unit transmitted over respective transmission paths, the device comprising: determining means for determining respective bit reliability indications for corresponding bits of at least three received data units, the corresponding bits being positioned at the same bit position in each of the received data units; each bit reliability indication being indicative of potential corruption of the respective bit by a transmission error; selection means for selecting, based on the determined bit reliability indications, a bit value, from among the bit values of the corresponding bits, the selection means being configured to select a bit value that is in minority of the bit values of the corresponding bits in the case where its respective bit reliability indication is indicative of a better reliability than the reliability indicated by the bit reliability indications of the bit values of the other corresponding bits; and data unit provision means for providing a data unit in which the bit at the corresponding bit position has the selected bit value.
13. A device according to claim 12 wherein the determining means is configured to determine a bit reliability indication is determined for each bit of a received data unit for comparison with a bit reliability indication of a corresponding bit of at least one other received data unit.
14. A device according to claim 12 or 13 further comprising means for determining whether the number of data units received is one, two or three in order to determine further processing steps.
15. A device according to claim 14 wherein the data unit provision means is configured to provide a data unit that corresponds to the received data unit, in the case where it is determined that one data unit is received.
16. A device according to claim 14 or 15 wherein the determining means is further configured to determine a respective data unit reliability indication for each received data unit, in the case where it is determined that two data units are received and the selection means is configured to select, based on the determined data unit reliability indications, a data unit from among the received data unit as the obtained data unit.
17. A device according to claim 16, wherein the determining means is configured to determine each data unit reliability indication Cq(/) according to the expression: Cq) = sum (mod(H. b(1:N,j),2) b(1 Nj) is a column vector; mod(x,2) is the x modulo 2 value; Cq(j) corresponds to the number of false checks H is the parity check matrix of the used LDPC code and the data unit reliability indication with the lowest Cq(j) is selected.
18. A device according to any one of claims 12 to 17, the determining means is configured to determine each bit reliability indication Cq(j) for each bit i of packet j, in the case where at least three data units are received, according to the expression: parity_check(j) = mod(H. b(1:N,j), 2) Cqj) = sum(H(:j) . parity_check[j)) where: parity_check(j) : is the parity check column vector with (N-K) bits; this vector equals the null vector if b(1:N,j) is a codeword; H is the parity check matrix (N-K) rows and N columns; Mod(x, 2) is the x value modulo 2; H(:j) is the column j of the matrix H; HC,j) . parity_check) is an element to element multiplication (H(:,j) and parity_check(j) are both column vectors).
19. A device according to claim 18, wherein the determining means is configured to apply a majority decision rule to derive the value of the ith bit of data unitj if the following condition is not satisfied: (Cq(i,j) = 0) AND (Cq(k) != 0; for any k!=j)
20. A device according to claim 19, wherein the value of the ith bit of data unitj is derived according to the expression: c('i) = roundabo, 1)+bO,2)+bO,3))/3 to provide selected bit value c(i) where round(.) is a function for approximating a real value to the nearest integer value.
21. A device according to claim 18, wherein the selected bit value c(i) = b(i,j) in the case where the condition (Cq(4ft = 0) AND (Cq(i,k) != 0 is satisfied for any k!=j).
22. A device according to any one of claims 12 to 21 wherein each of the plurality of received data units is encoded by means of an error correcting code having a set of parity check conditions, and the determining means is configured to determine each reliability indication based on the outcome of verification of the given parity check conditions on the corresponding data bit.
23. A method of obtaining a reliability indication of a symbol of a data unit comprising a plurality of symbols, the reliability indication being indicative of potential corruption of the respective symbol by a transmission error and the data unit having being encoded by an error correcting code, the method comprising verifying the fulfilment of a set of parity check conditions of the error correcting code by one or more of the plurality of symbols including the said symbol; and obtaining, for the said symbol, a reliability indication based on the outcome of the verification of the preceding step.
24. A method according to claim 23 wherein a respective reliability indication is determined for each symbol of the data unit for comparison with a reliability indication of a corresponding symbol of at least one other data unit.
25. A method according to claim 23 or 24 further comprising: selecting, for each symbol, based on the reliability indications, a symbol value, from among the symbol values of the corresponding symbols, and providing a data unit in which the symbols have the selected symbol values.
26. A network device for obtaining a reliability indication of a symbol of a data unit comprising a plurality of symbols, the reliability indication being indicative of potential corruption of the respective symbol by a transmission error and the data unit having being encoded by an error correcting code, the device comprising means for verifying the fulfilment of a set of parity check conditions of the error correcting code by one or more of the plurality of symbols including the said symbol; means for obtaining, for the said symbol, a reliability indication based on the outcome of the verification of the preceding step.
27. A device according to claim 26 wherein a respective reliability indication is determined for each symbol of the data unit for comparison with a reliability indication of a corresponding symbol of at least one other data unit.
28. A device according to claim 26 or 27 further comprising: means for selecting, for each symbol, based on the reliability indications, a symbol value, from among the symbol values of the corresponding symbols, and means for providing a data unit in which the symbols have the selected symbol values.
29. A computer program product for a programmable apparatus, the computer program product comprising a sequence of instructions for implementing a method according to any one of claims I to 11 or any one of claims 23 to 25 when loaded into and executed by the programmable apparatus.
30. A computer-readable storage medium storing instructions of a computer program for implementing a method, according to any one of claims 1 to 11 or any one of claims 23 to 25.
31. A method substantially as hereinbefore described with reference to, and as shown in Figures 6 and 7.