GB2500057A

GB2500057A - An N-path filter with variable N

Info

Publication number: GB2500057A
Application number: GB201204179A
Authority: GB
Inventors: Markus Nentwig
Original assignee: Renesas Mobile Corp
Current assignee: Renesas Electronics Corp
Priority date: 2012-03-09
Filing date: 2012-03-09
Publication date: 2013-09-11
Also published as: GB201204179D0

Abstract

Some of the capacitors in an RC N-path bandpass filter (fig. 4) may be omitted (S34) from the switching sequence in order to alter the ratio N between the centre frequency and the clock frequency. In multi-band radio receiver arrangements where the ADC clock is derived from the local oscillator by division by a band-dependent integer, the technique allows a notch filter frequency to be matched to the ADC sampling frequency while using a simple divider chain to derive the ADC and filter clocks from the local oscillator signal. Variation in the gain of the bandpass filter due to variation in N, and hence reduction in the depth of the notch, may be reduced by scaling, dependent on N, the output of the bandpass filter prior to combination with the input signal.

Description

1

METHOD AND APPARATUS FOR ENABLING A FILTER STRUCTURE

Technical Field

The present invention relates to an apparatus and method enabling a filter 5 structure with variable phase number. In particular embodiments, the present invention relates to an apparatus and method enabling a variable phase number in a filter structure such as a transferred impedance filter.

Background

10 Prior art which is related to this technical field can be found in for example specifications describing analog baseband filters.

The following meanings for the abbreviations used in this specification apply:

15

3 GPP

3rd Generation Partnership Project

ADC

Analog-to-Digital Converter

FDD

Frequency Division Duplex

HSDPA

High Speed Downlink Packet Access

LTE

Long Term Evolution

20

RF

Radio Frequency

TI

Transferred Impedance

E-UTRA

Evolved Universal Terrestrial Radio Access

WCDMA

Wideband Code Division Multiple Access

25 In typical wireless receivers, in particular in LTE and (multi-carrier)

HSDPA/WCDMA in frequency division duplex (FDD) bands, where the duplex spacing is close to the analog-to-digital converter (ADC) sampling rate of for example a successive approximation ADC, aliasing is potentially caused.

30 Accordingly, there is a need for innovative filter design which provides enhanced filtering performance.

2

Summary

According to a first aspect of the present invention, there is provided apparatus 5 for use in a communication device, the apparatus comprising a filter frequency generation circuitry comprising n stages, with n being a positive integer of 2 or more, and arranged to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n; and a filter stage selection processor arranged to 10 remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

According to a second aspect of the present invention, there is provided a 15 method comprising consecutively operating n stages of a frequency filter with a filter clock frequency in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n, with n being a positive integer of 2 or more; and selectively removing m of the n stages from the sequence and correspondingly reducing the phases, with m being a positive integer between 1 and n-1, so that the 20 filter frequency is generated at the filter clock frequency divided by n minus m.

In an embodiment, the method is used in a communication device.

Examples of embodiments of the present invention provide an apparatus and a 25 method for suppressing unwanted signal components in receiving signals in wireless communication. In examples, there is provided a filter design that saves current and area and in which an intended filter frequency can be accurately adjusted even in the case of a flexible and/or inappropriate filter clock frequency.

3

Further features and advantages of the invention will become apparent from the following description of preferred embodiments of the invention, given by way of example only, which is made with reference to the accompanying drawings.

5 Brief Description of the Drawings

Fig. 1 shows an equivalent circuit diagram of a an example of a filter structure according to certain embodiments of the present invention;

Fig. 2 shows a schematic block diagram of an example of apparatus according

10 to certain embodiments of the present invention;

Fig. 3 shows a flow chart of an example of a method according to certain embodiments of the present invention;

15 Fig. 4 shows an implementation example of the lower branch of the equivalent circuit shown in Fig. 1 according to certain embodiments of the present invention;

Fig. 5 shows a phase diagram illustrating a clock signal for operating the switches shown in Fig. 4; and

20

Fig. 6 shows an example for illustrating the generation of a filter frequency in dependency on target frequency and available clock frequency to which certain embodiments of the present invention can be applied.

25 Detailed Description

In the following, description is made to what are presently considered to be preferred embodiments of the present invention. It is to be understood, however, that the description is given by way of example only and that the described embodiments are by no means to be understood as limiting the present invention thereto.

30

4

For example, for illustration purposes, in some of the following exemplary embodiments, suppressing unwanted signal components in receiving signals in wireless communication in cellular communication networks as based on for example LTE, LTE-Advanced or WCDMA is described. However, it should be appreciated 5 that these exemplary embodiments are not limited for use among these particular types of wireless communication systems, and according to further exemplary embodiments, the present invention can be applied also to other technical fields in which filtering, such as for example suppressing unwanted signal components in received signals, is to be implemented and optimised. For example, other applications 10 include use in base stations or machine-to-machine communications, such as vending machines or cash registers.

Thus, certain embodiments of the present invention relate to mobile wireless communication systems, such as LTE, LTE-Advanced and WCDMA. In more detail, 15 certain embodiments of the present invention are related to the configuration of an LTE/WCDMA radio receiver and components thereof such as mobile device receiver integrated circuits and/or discrete elements. However, as indicated above, the present invention is not limited thereto, but other embodiments of the present invention are related to general radio receiver equipment.

20

An implementation example according to certain embodiments of the present invention for a transferred impedance filter is shown in Fig. 2.

Specifically, as shown in Fig. 2, the implementation example includes an 25 apparatus for use in a communication device, the apparatus comprising a filter frequency generation circuitry 21 comprising n stages, with n being a positive integer of 2 or more, and arranged to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n; and a filter stage selection 30 processor 22 arranged to remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer between 1 and n-1,

5

so that the filter frequency is generated at the filter clock frequency divided by n minus m.

Another implementation example according to certain embodiments of the 5 present invention includes an apparatus for use in a communication device, the apparatus comprising means for generating a filter frequency 21 comprising n stages, with n being a positive integer of 2 or more, and arranged to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n; and

10 means for selecting a filter stage 22 arranged to remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

15 Still another implementation example according to certain embodiments of the present invention includes an apparatus, comprising a filter frequency generation circuitry comprising n stages, with n being a positive integer of 2 or more, and configured to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the

20 filter clock frequency divided by n, and a filter stage selection processor configured to remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

25 According to certain embodiments of the present invention, the above described implementation examples could be modified as follows, as is apparent from Fig. 2, wherein one or more of the modifications can be freely combined unless explicitly stated as excluding alternatives.

30 The filter frequency generation circuitry 21 can comprise n/2 capacitors and be arranged and/or configured to consecutively connect the n/2 capacitors in a forward

6

direction and to consecutively connect the n/2 capacitors in a reverse direction with an input of the filter frequency generation circuitry 21, each connection action corresponding to one of the n phases and a connection structure corresponding to one such connection action constituting one of the n stages, so that n is a positive integer 5 multiple of 2 and equal to 4 or more, and the filter stage selection processor 22 can be arranged and/or configured to remove connection of a capacitor both in the forward direction and in the reverse direction so that m is a positive integer multiple of 2, and m is between 2 and n-2. (As will be understood, the or each capacitor may in practice be provided by one or more capacitors, in order to obtain the desired capacitance 10 characteristics.)

Further, a scaling factor applying circuitry 23 can be arranged and/or configured to change a scaling factor applied to an output of the filter frequency generation circuitry 21 by being arranged and/or configured to switch transistor pairs 15 of different size in an operational amplifier input in series connection with the output of the filter frequency generation circuitry 21 and/or to switch resistor values of a resistor in series connection with the output of the filter frequency generation circuitry 21.

20 The filter frequency generation circuitry 21 can further be arranged and/or configured to combine four stages to two stages by connecting two of the n/2 capacitors in the forward direction at the same phase and in the reverse direction at the same phase.

25 The apparatus can further comprise a clock divider processor 24 arranged and/or configured to divide the frequency of a source clock in a plurality of division stages each applying an integer divisor, wherein each division stage provides a correspondingly divided source clock frequency; and a filter frequency determining processor 25 arranged and/or configured to determine the filter frequency by dividing 30 the frequency of the source clock by a predetermined target frequency to be filtered, and approximating the thus obtained quotient by selecting one of the divided source

7

clock frequencies as the filter clock frequency and triggering the filter stage selection processor 22 accordingly, including selecting the source clock frequency itself and/or not triggering the filter stage selection processor at all.

5 The filter frequency generation circuitry 21 and the filter stage selection processor 22 as well as selected ones (and indeed all) of the other elements shown in Fig. 2 can be arranged and/or configured for use in a wireless communication system according to the Long Term Evolution and/or the Wideband Code Division Multiple Access specifications.

10

A specific implementation example according to certain embodiments of the present invention includes that any of the above described apparatus is arranged and/or configured for use in a wireless communication device and further comprises wired interface circuitry and wireless transceiver circuitry.

15

A further specific implementation example according to certain embodiments of the present invention includes that any of the above described apparatus is arranged and /or configured for use in a mobile phone and further comprises user interface circuitry and user interface software configured to enable user control through use of a

20 human-machine-interface such as a display.

A still further implementation example of the apparatus according to certain embodiments of the present invention includes that a mobile phone comprises any of the above described apparatus.

25

Fig. 3 shows a schematic flowchart of an example for a method according to certain embodiments of the present invention. That is, as shown in Fig. 3, this example of a method for use in a communication device comprises consecutively operating S33 n stages of a frequency filter with a filter clock frequency (filter clock) in

30 a corresponding sequence of n phases to generate a filter frequency (ffiiter) at the filter clock frequency (ffiiter dock) divided by n, with n being a positive integer of 2 or more,

8

and providing for removing S34 m of the n stages from the sequence and correspondingly reducing the phases, with m being a positive integer between 1 and n-1, so that the filter frequency (ffiiter) is generated at the filter clock frequency (ffiiter dock) divided by n minus m.

5

According to certain embodiments of the present invention, the above described example method could be modified as follows, as is apparent from Fig. 3, wherein one or more of the modifications can be freely combined unless explicitly stated as excluding alternatives.

10

The method can comprise providing n/2 capacitors and consecutively connecting the n/2 capacitors in the forward direction and consecutively connecting the n/2 capacitors in the reverse direction with a frequency filter input, each connection action corresponding to one of the n phases and a connection structure

15 corresponding to one such connection action constituting one of the n stages, so that n is a positive integer multiple of 2 and equal to 4 or more, and providing for removing the connection of a capacitor both in forward and in reverse directions so that m is a positive integer multiple of 2 and m is between 2 and n-2.

20 The method can further comprise changing S35 a scaling factor applied to a frequency filter output by switching transistor pairs of different size in an operational amplifier input in series connection with the frequency filter output and/or switching resistor values of a resistor in series connection with the frequency filter output.

25 The method can further comprise combining four stages to two stages by connecting two of the n/2 capacitors in the forward direction at a same phase and in the reverse direction at a same phase.

The method can further comprise dividing S31 the frequency (fS0Urce) of a

30 source clock in a plurality (l...i) of division stages each applying an integer divisor, wherein each division stage provides a correspondingly divided source clock

9

frequency (fSOurce div 1 ... fsource_div i); and determining S32 a filter frequency (ffiiter) by dividing the frequency (fS0Urce) of the source clock by a predetermined target frequency (ftarget) to be filtered, and approximating the thus obtained quotient by selecting one of the divided source clock frequencies (fsource div 1 ••• fsource div i) as the filter clock 5 frequency (ffiiter dock) and removing m of the n stages from the sequence accordingly, including selecting the source clock frequency (fS0Urce) itself and/or not removing any of the n stages from the sequence at all.

According to certain embodiments of the present invention, one option for 10 performing the above described example method or any of its modifications would be to use the apparatus or one of its modifications described in connection with Fig. 2, which becomes apparent from the embodiments as described herein below.

Certain embodiments of the present invention are described herein below in 15 further detail. Reference is made to implementation examples which depict certain embodiments of the present invention. It is to be noted though that the implementation examples are provided for illustrative purposes only and are not intended to be understood as limiting the invention thereto. Rather, it is to be understood that the features of the implementation examples may be interchanged and 20 mixed as will be understood from the whole of the present specification.

Certain embodiments of the present invention are formed by applying the above described apparatus and/or selected ones of its optional modifications to a transferred impedance notch filter. An equivalent circuit diagram of the principal 25 configuration of a transferred impedance notch filter structure according to certain embodiments of the present invention is shown in Fig. 1. Specifically, according to this basic structure, an input signal is branched into two branches labelled "MAIN" and "AUX", wherein in the MAIN branch, the input signal is transferred to a combining circuitry substantially unchanged (ignoring any amplifying and/or scaling 30 actions or the like), whereas in the AUX branch, the input signal is subjected to a transferred impedance processing by transferring one of N capacitors Ci...Cn via a

10

mixing processor according to a clock signal CLK to the input signal. At the combining circuitry, the unchanged input signal and the processed input signal are combined with opposite phases, whereby a notch frequency (generated in the AUX branch) is applied to the input signal (MAIN branch) so that a frequency to be filtered 5 is removed by the notch in the frequency spectrum.

This transferred impedance (TI) filter requires a clock at n times the notch frequency, where n is a number of phases of the TI filter, wherein an n-phased clock can be easily generated by integer division from a source clock at n times the target 10 clock rate. Certain embodiments of the present invention provide the advantage that they alleviate the problem that such a source clock rate is not available for operation in all radio bands for useful values of n, wherein for example the sampling frequency of an ADC as the target frequency to be filtered is derived from a local oscillator signal by integer division by a band-dependent ratio.

15

According to certain embodiments of the present invention, the transferred impedance notch filter is operated at the same frequency as the ADC, which prevents generation of spurious tones at multiples of the notch frequency, enables reuse of dividers and thus helps to save current and area too, and enables the notch tracking the 20 channel-dependent ADC frequency (+/- 2 %).

Table 1 below depicts some implementation examples of FDD bands where, in typical implementation examples, aliasing occurs (e.g. due to a duplex spacing of 48 MHz and lower). For such cases, certain embodiments of the present invention 25 provide alternatives where n times the desired notch frequency is not available in a related band-/channel combination.

Band

ADC clock division ratio clock division ratio factors

LTE 5 / HSDPA V

20

2*2*5

LTE 6 / HSDPA VI

20

(same as band 5)

11

LTE 8 / HSDPA VIII

20

(same as band 5)

LTE 11 / HSDPA XI

30

3*2*5

LTE 12/HSDPA XII

16

2*2*2*2

LTE 13/HSDPAXIII

16

(same as band 12)

LTE 17

16

(same as band 12)

LTE 18

20

(same as band 5)

LTE 19 /HSDPA XIX

20

(same as band 5)

LTE 20 / HSDPA XX

16

(same as band 12)

LTE 21 / HSDPA XXI

30

(same as band 11)

Table 1

Fig. 4 shows an implementation example of the lower branch of the equivalent 5 circuit shown in Fig. 1 according to certain embodiments of the present invention. Specifically, the node labelled with 410 designates the input of the structure, and the node labelled with 420 designates the output of the structure. Resistors 450a and 450b are connected in series to the transferred impedance structure comprising (as an example) the three capacitors 462, 464, and 466 (as the capacitors Ci...Cn of Fig. 1) 10 and switches 430a...444a, 430b...444b, which are operated according to pulses pi...p6. Note that the structure exemplified in Fig. 4 comprises n=6 stages and is arranged for operation with n=6 phases. Thus, the number of capacitors is n/2=3.

The implementation example of Fig. 4 is driven by the clock signals shown in 15 Figure 5, illustrating a phase diagram of the clock signal for operating the switches 430a.. ,444a, 430b.. ,444b, i.e. a six-phase clock.

Specifically, only one capacitor is connected at any time, forming an RC voltage divider with the resistors 450a, 450b (differential-mode input signal). The 20 pulses pi...p6 corresponding to the respective six phases perform the following connection actions:

pi: 462 (Ci) connected in forward direction

12

p2: 464 (C2) connected in forward direction p3: 466 (C3) connected in forward direction p4: 462 (Ci) connected in reverse direction p5: 464 (C2) connected in reverse direction 5 p6: 466 (C3) connected in reverse direction

Thereafter, the cycle is repeated. Conceptually, the structure can be understood such that Ci "samples" the input signal during phase pi, and "reflects" it back during phase p4. The frequency response is somewhat similar to loading R with

10 a radio frequency "short circuit" delay line of length X./4 at the cycle frequency. For an input signal at the cycle frequency, the "reflected" signal and the input signal add constructively, and a bandpass response results. A notch filter is then constructed by subtracting the output signal of the transferred impedance structure from the filter input signal, e.g. in the input of a subsequent operational amplifier stage.

15

For instance, the implementation example presented in connection with Fig. 4 and 5 operates at six times the ADC sampling rate as the target frequency to be filtered.

20 According to certain embodiments of the present invention, such an n-phase transferred impedance filter (using n/2 capacitors) is operated at n times the clock frequency of the notch for controlling aliasing caused by the switched-capacitor principle of the transferred impedance filter itself.

25 It may be noted that, as indicated above, n times the notch frequency is not always available. For example, if the TI notch tracks the ADC clock frequency (see above Table 1), the greatest common division factor is 2. Thus, to derive the desired number of phases for operation in all bands, certain embodiments of the present invention are applied. That is, according to certain embodiments of the present

30 invention, the number of Tl-stages (phases) is switched depending on an available source clock. According to further embodiments of the present invention, the

13

available source clock depends on an operation band, i.e. is a multiple of the ADC clock, see above Table 1.

Thus, as illustrative implementation examples, in bands 12, 13, 17, 20 a 5 4-capacitor transferred impedance notch filter driven by an 8-phase clock can be used, and in bands 5, 11, 18, 19, 21 a 5-capacitor transferred-impedance notch filter driven by a 10-phase clock can be used. According to certain embodiments of the present invention, the 4-capacitor filter is derived from the 5-capacitor filter by leaving the switches of one "stage" (see e.g. Fig. 4) permanently open.

10

Since changing the number of stages can imbalance the notch filter by for example adding the transferred-impedance bandpass signal to the original signal, according to certain embodiments of the present invention a scaling factor for adding the output signal of the Tl-branch to the input signal of the TI filter can be changed. 15 This can be done, for example, by switching transistor pairs of different size in an operational amplifier input and/or by switching resistor values (e.g. the resistors 450a, 450b in Fig. 4).

In another implementation example according to certain embodiments of the 20 present invention, a fixed notch frequency is used. For example, depending on the channel, a fixed clock can be derived that gives better rejections, while not causing harmonics into the receive band at RF.

Since in typical implementations the highest available "fixed" system clock is 25 rather low (for example 104 MHz), it can thus be necessary to run the Tl-filter at a lower number of phases, compared to when it is clocked by an integer multiple of the ADC frequency.

According to certain embodiments of the present invention this is achieved by 30 changing the clock frequency to another by reconfiguring the n-capacitor switched impedance by operating capacitors in pairs, driven by the same clock phase. Besides,

14

this feature can also enable use of the notch filter in "half-rate mode", when the ADC clock is divided by 2 for power saving purposes.

In accordance with the above description, further implementation examples 5 according to certain embodiments of the present invention comprise re-configuring a clock divider for the TI filter and making adjustments to the scaling factor depending on the band, wherein in some bands at least one of the filter stages remain unused. Accordingly, the filter frequency is accurately controlled by clock division.

10 Still further implementation examples according to certain embodiments of the present invention comprise circuitry and/or a processor or processors arranged to select, based on a reception radio band, a number of phases for a transferred-impedance filter prior to an analog-to-digital converter, to generate the selected number of phase signals by integer division from a local oscillator, and thus to make

15 the cycle frequency of the transferred impedance filter identical to a conversion frequency of the analog-to-digital converter.

While the above described Fig. 1 shows a transferred-impedance notch filter that suppresses unwanted signals near its clock frequency (for example 42 MHz as a

20 typical ADC clock), it is to be noted that the present invention could also be applied to a transferred-impedance peaking filter that amplifies wanted signals near its clock frequency, which is arrived at by combining the signals of both branches (MAIN and AUX) with same phases (i.e. adding the signals) instead of combining them with opposite phases (subtracting).

25

Fig. 6 shows a further implementation example for illustrating the generation of a filter frequency in dependency on target frequency and available clock frequency to which certain embodiments of the present invention can be applied.

30 It is noted that the case that the TI frequency equals the ADC clock as the target frequency is only one example to suppress aliases using the TI structure. Other

15

scenarios where a receiver needs to block out a known target frequency (such as for example a nearby strong unwanted channel that has been detected based on analysing the rate of zero crossings in a baseband signal) are easily apparent to the skilled person.

5

Assume a case where a receiver uses a local oscillator LO, which is typically located at the centre frequency of a received bandwidth. The ADC could be clocked at any frequency in some range (such as 40.. .50 MHz). Harmonics of the ADC clock can end up as spurious tones in the received bandwidth. For example, the 41st 10 harmonic of 50 MHz sampling clock might appear at 2150 MHz, which falls into band 1 (see below Table 2 showing the E-UTRA operating bands taken from 3 GPP TS 36.101, current version 10.5.0, showing the range spanned by bands mentioned herein). ADC clock harmonics are a severe problem, and the solution according to certain embodiments of the present invention is to derive the clock for ADC by 15 integer division from the local oscillator. The most problematic harmonic then falls exactly on top of the LO, where it does no harm. For example, in band 5, an ADC clock division ratio (from Table 1) of 20 is used. It is implemented using integer division by 2, then by 5, then by 2. Further, in band 12, the ADC clock division ratio is 16. Fig. 6 shows the LO clock divider chains for bands 5 and 12. To derive an 20 n-phase clock (for an n-phase TI filter), n times the clock frequency of the TI filter is required. However, as illustrated in Fig. 6, the final division stage, which can at the same time generate the ADC clock and an n-phase clock for the TI filter, uses a different division factor. (For completeness, it may be noted that for reasons outside the framework of the present specification, in the example of Fig. 6 it might not be 25 possible to move the divide-by-5 to the top of the chain in band 5 and use four phases in both cases.)

16

E-UTRA

Uplink (UL) operating band

Downlink (DL) operating band

Duplex

Operating

BS receive

BS transmit

Mode

Band

UE transmit

UE receive

FuL low Fn high

FdL low FdL high

1

1920 MHz

-1980 MHz

2110 MHz

- 2170 MHz

FDD

2

1850 MHz

-1910 MHz

1930 MHz

- 1990 MHz

FDD

3

1710 MHz

-1785 MHz

1805 MHz

- 1880 MHz

FDD

4

1710 MHz

-1755 MHz

2110 MHz

- 2155 MHz

FDD

5

824 MHz

-849 MHz

869 MHz

- 894MHz

FDD

61

830 MHz

-840 MHz

875 MHz

- 885 MHz

FDD

7

2500 MHz

-2570 MHz

2620 MHz

- 2690 MHz

FDD

8

880 MHz

-915 MHz

925 MHz

- 960 MHz

FDD

9

1749.9 MHz

-1784.9 MHz

1844.9 MHz

- 1879.9 MHz

FDD

10

1710 MHz

-1770 MHz

2110 MHz

- 2170 MHz

FDD

11

1427.9 MHz

-1447.9 MHz

1475.9 MHz

- 1495.9 MHz

FDD

12

699 MHz

-716 MHz

729 MHz

- 746 MHz

FDD

13

777 MHz

-787 MHz

746 MHz

- 756 MHz

FDD

14

788 MHz

-798 MHz

758 MHz

- 768 MHz

FDD

15

Reserved

FDD

16

Reserved

FDD

17

704 MHz

-716 MHz

734 MHz

- 746 MHz

FDD

18

815 MHz

-830 MHz

860 MHz

- 875 MHz

FDD

19

830 MHz

-845 MHz

875 MHz

- 890 MHz

FDD

20

832 MHz

-862 MHz

791 MHz

- 821 MHz

FDD

21

1447.9 MHz

-1462.9 MHz

1495.9 MHz

- 1510.9 MHz

FDD

23

2000 MHz

-2020 MHz

2180 MHz

- 2200 MHz

FDD

24

1626.5 MHz

-1660.5 MHz

1525 MHz

- 1559 MHz

FDD

17

25

1850 MHz

-1915 MHz

1930 MHz

- 1995 MHz

FDD

33

1900 MHz

-1920 MHz

1900 MHz

- 1920 MHz

TDD

34

2010 MHz

-2025 MHz

2010 MHz

- 2025 MHz

TDD

35

1850 MHz

-1910 MHz

1850 MHz

- 1910 MHz

TDD

36

1930 MHz

-1990 MHz

1930 MHz

- 1990 MHz

TDD

37

1910 MHz

-1930 MHz

1910 MHz

- 1930 MHz

TDD

38

2570 MHz

-2620 MHz

2570 MHz

- 2620 MHz

TDD

39

1880 MHz

-1920 MHz

1880 MHz

- 1920 MHz

TDD

40

2300 MHz

-2400 MHz

2300 MHz

- 2400 MHz

TDD

41

2496 MHz

-2690 MHz

2496 MHz

-2690 MHz

TDD

42

3400 MHz

-3600 MHz

3400 MHz

- 3600 MHz

TDD

43

3600 MHz

-3800 MHz

3600 MHz

- 3800 MHz

TDD

Note 1: Band 6 is not applicable

Table 2

According to certain embodiments of the present invention, a source clock 5 provides a lower frequency clock (such as ADC clock in Fig. 6) and a higher frequency clock (such as LO clock in Fig. 6), wherein the higher frequency clock is a programmable integer multiple of the lower-frequency clock, and the number of phases in the transferred impedance structure is configured to be equal to the programmable integer multiple.

10

According to further embodiments of the present invention, the TI filter is aimed to be operated as close to a target frequency as possible, by selecting an integer division rate comprising an integer factor from a set of finite factors (e.g. {4, 5} allowing four-phase and five-phase TI filtering in the case of Fig. 6), wherein the 15 selection action substantially minimises a difference between the quotient of a clock frequency divided by the integer division rate and a target frequency, a programmable

18

divider is configured to the selected division rate and a number of output phases equal to the integer factor is generated, and a TI structure is configured to a number of phases equal to the integer factor. Hence, the TI frequency reaches the target frequency with sufficient accuracy for varying input clock frequencies and/or target 5 frequencies.

As indicated above, certain embodiments of the present invention include radio-frequency cellular chipset(s) and equipment such as according to LTE/LTE-Advanced and/or WDCMA, but are not limited thereto.

10

According to the above description, it is thus apparent that exemplary embodiments of the present invention provide, for example from the perspective of a mobile phone, a communication device, a base station transceiver or a component thereof, an apparatus embodying the same, a method for controlling and/or operating 15 the same, and computer program(s) controlling and/or operating the same as well as media carrying such computer program(s) and forming computer program product(s).

For example, described above are apparatus, methods and computer program products enabling a filter structure with variable phase number.

20

Implementations of any of the above described blocks, apparatus, systems, techniques or methods include, as non limiting examples, implementations as hardware, software, for example in connection with a digital signal processor, an instruction set, firmware, special purpose circuits or application logic, general purpose 25 hardware or controller or other computing devices, or some combination thereof. Software or application logic or an instruction set may be maintained on any one of various conventionally available computer-readable media (which shall be understood as anything that can contain, store, communicate, propagate or transport instructions in connection with an instruction execution system). Further, it is to be understood 30 that where reference is made to a processor, such processor is to be understood in its broadest sense and may, for example, additionally comprise or not comprise a

19

memory (e.g., ROM, CD-ROM, etc.), and it may comprise a computer processor (including dual-core and multiple-core processors), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), and/or other hardware components that have been programmed in such a way to carry out the described 5 function.

Further, as used in this application, the term circuitry refers to all of the following: (a) hardware-only circuit implementation (such as implementations in only analog and/or digital circuitry) and (b) to combinations of circuits and software 10 (and/or firmware), such as (as applicable): (i) to a combination of processor(s) or (ii) to portions of processor(s)/software (including digital signal processors(s)), software and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions, and (c) to circuits, such as microprocessors(s), that require software or firmware for operation, even if the software or firmware is not 15 physically present.

This definition of circuitry applies to all uses of this term in this specification including in any claims. As a further example, as used in this specification, the term circuitry would also cover an implementation of merely a processor (or multiple 20 processors) or portion of a processor and its (or their) accompanying software and/or firmware. The term circuitry would also cover, for example and if applicable to the particular claim element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in server, a cellular network device, or other communication device.

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If desired, the different functions discussed herein may be performed in a different order and/or concurrently with each other. Furthermore, if desired, one or more of the above described functions may be optional or may be combined.

30 Although various aspects of the invention are set out in the appended independent claims, other aspects of the invention comprise other combinations of

20

features from the described embodiments and/or the dependent claims with the features of the independent claims, and not solely the combinations explicitly set out in the claims.

5 The above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention are envisaged. It is to be understood that any feature described in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any 10 other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims.

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Claims

1. Apparatus for use in a communication device, the apparatus comprising:

a filter frequency generation circuitry comprising n stages, with n being a 5 positive integer of 2 or more, and arranged to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n; and a filter stage selection processor arranged to remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer 10 between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

2. Apparatus according to claim 1, wherein:

the filter frequency generation circuitry comprises n/2 capacitances and is 15 arranged to consecutively connect the n/2 capacitances in a forward direction and to consecutively connect the n/2 capacitances in a reverse direction with an input of the filter frequency generation circuitry, each connection action corresponding to one of the n phases and a connection structure corresponding to one such connection action constituting one of the n stages, so that n is a positive integer multiple of 2 and equal 20 to 4 or more, and the filter stage selection processor is arranged to remove connection of a capacitor both in forward and in reverse direction so that m is a positive integer multiple of 2, and m is between 2 and n-2.

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3. Apparatus according to claim 1 or claim 2, comprising:

a scaling factor-applying circuitry arranged to change a scaling factor applied to an output of the filter frequency generation circuitry by being arranged to switch transistor pairs of different size in an operational amplifier input in series connection with the output of the filter frequency generation circuitry and/or to switch resistor 30 values of a resistor in series connection with the output of the filter frequency generation circuitry.

22

4. Apparatus according to claim 2, wherein:

the filter frequency generation circuitry is further arranged to combine four stages to two stages by connecting two of the n/2 capacitances in forward direction at 5 a same phase and in reverse direction at a same phase.

5. Apparatus according to any of claims 1 to 4, comprising:

a clock divider processor arranged to divide the frequency of a source clock in a plurality of division stages each applying an integer divisor, wherein each division 10 stage provides a correspondingly divided source clock frequency; and a filter frequency determining processor arranged to determine the filter frequency by dividing the frequency of the source clock by a predetermined target frequency to be filtered, and approximating the thus obtained quotient by selecting one of the divided source clock frequencies as the filter clock frequency and 15 triggering the filter stage selection processor accordingly, including selecting the source clock frequency itself and/or not triggering the filter stage selection processor at all.

6. Apparatus according to any of claims 1 to 5, wherein the filter frequency 20 generation circuitry and the filter stage selection processor are arranged for use in a wireless communication system according to the Long Term Evolution and/or the Wideband Code Division Multiple Access specifications.

7. Apparatus according to any of claims 1 to 6 arranged for use in a wireless 25 communication device and comprising:

wired interface circuitry; and wireless transceiver circuitry.

8. Apparatus according to any of claims 1 to 6 arranged for use in a mobile 30 phone and comprising:

user interface circuitry; and

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user interface software configured to enable user control through use of a human-machine-interface such as a display.

9. A mobile phone comprising apparatus according to any of claims 1 to 6.

5

10. A metho d comprising:

consecutively operating n stages of a frequency filter with a filter clock frequency in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n, with n being a positive integer of 2 or more; and 10 selectively removing m of the n stages from the sequence and correspondingly reducing the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

11. A method according to claim 10, comprising:

15 selectively consecutively connecting n/2 capacitors in a forward direction and consecutively connecting the n/2 capacitors in a reverse direction with a frequency filter input, each connection action corresponding to one of the n phases and a connection structure corresponding to one such connection action constituting one of the n stages, so that n is a positive integer multiple of 2 and equal to 4 or more, and 20 selectively removing the connection of a capacitor both in forward and in reverse direction so that m is a positive integer multiple of 2, and m is between 2 and n-2.

12. A method according to claim 10 or claim 11, comprising:

25 changing a scaling factor applied to a frequency filter output by switching transistor pairs of different size in an operational amplifier input in series connection with the frequency filter output and/or switching resistor values of a resistor in series connection with the frequency filter output.

30

13. A method according to claim 11, comprising:

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combining four stages to two stages by connecting two of the n/2 selectively in forward direction at a same phase and in reverse direction at a same phase.

14. A method according to any of claims 10 to 13, comprising: 5 dividing the frequency of a source clock in a plurality of division stages each applying an integer divisor, wherein each division stage provides a correspondingly divided source clock frequency; and determining a filter frequency by dividing the frequency of the source clock by a predetermined target frequency to be filtered, and approximating the thus obtained 10 quotient by selecting one of the divided source clock frequencies as the filter clock frequency and removing m of the n stages from the sequence accordingly, including selecting the source clock frequency itself and/or not removing any of the n stages from the sequence at all.

15 15. Apparatus for use in a communication device for enabling a filter structure with variable phase number, substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.

16. A method for use in a communication device for enabling a filter structure with variable phase number, substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.

16. A method for use in a communication device for enabling a filter structure 20 with variable phase number, substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.

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Amendments to the claims have been filed as follows

1. Apparatus for use in a communication device, the apparatus comprising:

a filter comprising filter frequency generation circuitry comprising n stages, with n being a positive integer of 2 or more, and arranged to be operated with a filter clock frequency consecutively operating the n stages in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n; and a filter stage selection processor arranged to remove m of the n stages from the sequence and to correspondingly reduce the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

2. Apparatus according to claim 1, wherein:

the filter frequency generation circuitry comprises n/2 capacitances and is arranged to consecutively connect the n/2 capacitances in a forward direction and to consecutively connect the n/2 capacitances in a reverse direction with an input of the filter frequency generation circuitry, each connection action corresponding to one of the n phases and a connection structure corresponding to one such connection action constituting one of the n stages, so that n is a positive integer multiple of 2 and equal to 4 or more, and the filter stage selection processor is arranged to remove connection of a capacitor both in forward and in reverse direction so that m is a positive integer multiple of 2, and m is between 2 and n-2.

3. Apparatus according to claim 1 or claim 2, comprising:

a scaling factor-applying circuitry arranged to change a scaling factor applied to an output of the filter frequency generation circuitry by being arranged to switch transistor pairs of different size in an operational amplifier input in series connection with the output of the filter frequency generation circuitry and/or to switch resistor values of a resistor in series connection with the output of the filter frequency

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generation circuitry and/or to switch resistor values of a resistor of the filter frequency generation circuitry.

4. Apparatus according to claim 2, wherein:

the filter frequency generation circuitry is further arranged to combine four stages to two stages by connecting two of the n/2 capacitances in forward direction at a same phase and in reverse direction at a same phase.

5. Apparatus according to any of claims 1 to 4, comprising:

a clock divider processor arranged to divide the frequency of a source clock in a plurality of division stages each applying an integer divisor, wherein each division stage provides a correspondingly divided source clock frequency; and a filter frequency determining processor arranged to determine the filter frequency by dividing the frequency of the source clock by a predetermined target frequency to be filtered, and approximating the thus obtained quotient by selecting one of the divided source clock frequencies as the filter clock frequency and triggering the filter stage selection processor accordingly, including selecting the source clock frequency itself and/or not triggering the filter stage selection processor at all.

6. Apparatus according to any of claims 1 to 5, wherein the filter frequency generation circuitry and the filter stage selection processor are arranged for use in a wireless communication system according to the Long Term Evolution and/or the Wideband Code Division Multiple Access specifications.

7. Apparatus according to any of claims 1 to 6 arranged for use in a wireless communication device and comprising:

wired interface circuitry; and wireless transceiver circuitry.

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8. Apparatus according to any of claims 1 to 6 arranged for use in a mobile phone and comprising:

user interface circuitry; and user interface software configured to enable user control through use of a human-machine-interface such as a display.

9. A mobile phone comprising apparatus according to any of claims 1 to 6.

10. A method comprising:

consecutively operating n stages of a frequency filter with a filter clock frequency in a corresponding sequence of n phases to generate a filter frequency at the filter clock frequency divided by n, with n being a positive integer of 2 or more; and selectively removing m of the n stages from the sequence and correspondingly reducing the phases, with m being a positive integer between 1 and n-1, so that the filter frequency is generated at the filter clock frequency divided by n minus m.

11. A method according to claim 10, comprising:

selectively consecutively connecting n/2 capacitors in a forward direction and consecutively connecting the n/2 capacitors in a reverse direction with a frequency filter input, each connection action corresponding to one of the n phases and a connection structure corresponding to one such connection action constituting one of the n stages, so that n is a positive integer multiple of 2 and equal to 4 or more, and selectively removing the connection of a capacitor both in forward and in reverse direction so that m is a positive integer multiple of 2, and m is between 2 and n-2.

12. A method according to claim 10 or claim 11, comprising:

changing a scaling factor applied to a frequency filter output by switching transistor pairs of different size in an operational amplifier input in series connection with the frequency filter output and/or switching resistor values of a resistor in series

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connection with the frequency filter output and/or switching resistor values of a resistor of the frequency filter.

13. A method according to claim 11, comprising:

14. A method according to any of claims 10 to 13, comprising:

dividing the frequency of a source clock in a plurality of division stages each applying an integer divisor, wherein each division stage provides a correspondingly divided source clock frequency; and determining a filter frequency by dividing the frequency of the source clock by a predetermined target frequency to be filtered, and approximating the thus obtained quotient by selecting one of the divided source clock frequencies as the filter clock frequency and removing m of the n stages from the sequence accordingly, including selecting the source clock frequency itself and/or not removing any of the n stages from the sequence at all.

15. Apparatus for use in a communication device for enabling a filter structure with variable phase number, substantially in accordance with any of the examples as described herein with reference to and illustrated by the accompanying drawings.