GB2498945A

GB2498945A - Improved loop filter for phase locked loop (PLL)

Info

Publication number: GB2498945A
Application number: GB201201604A
Authority: GB
Inventors: Peter Hunt; Joaquim Machado; Andrew Pickering
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2012-01-31
Filing date: 2012-01-31
Publication date: 2013-08-07
Also published as: GB201201604D0

Abstract

In the prior art (fig.1) the choice of loop filter damping resistor and VCO Kv results in a compromise between random jitter, tuning range and stability. The present invention overcomes these limitations by providing a VCO with two independent control nodes connected to the filter. The present loop filter / VCO circuit comprises a damping resistor connected between a relatively high kv input node and a relatively low kv input node, and a loop filter capacitor coupled in series with the damping resistor. The relatively high Kv input node is at the junction between the damping resistor and the loop filter capacitor. This is a low-noise, stable node with a slow response to loop adjustment, and gives the PLL a wide tuning range without producing excess jitter. Signals from the two input nodes are combined in a transistor circuit (fig.3) which supplies the control input of a Voltage Controlled Oscillator. The invention reduces the effect of thermal noise generated in a resistor in the PLL loop filter.

Description

1

IMPROVED LOOP FILTER FOR PLL FIELD OF THE INVENTION

The present invention relates to phase locked loop circuits, and more particularly, to an improved loop filter design for phase locked loops (PLLs) that have a high frequency-to-control voltage ratio (Kv) voltage controlled oscillator VCO.

BACKGROUND OF THE INVENTION

Phase locked Loops (PLLs) that have a wide tuning range need to employ voltage controlled oscillators (VCOs) with a high frequency-to-control voltage (Kv) ratio. The frequency response of a PLL is controlled by the loop filter which is usually a network of analogue components including resisitors. The thermal noise in these components is converted to clocking jitter in proportion to the Kv (frequency-to-control ratio) of the VCO. This then poses a limitation on the performance of high Kv VCOs..

Figure 1 shows a typical passive Loop filter consisting of a Loop Capacitor, a damping resistor and a bypass capacitor (often known as the third order pole or anti-ripple capacitor). This is part of the phase correction loop with the intended mode of operation being that: 1) the charge pump produces a charge output proportional to the phase error in the loop, 2) the Loop Filter performs a charge to voltage conversion and frequency shapes the response to the phase correction voltage Vctrl, and 3) the VCO then speeds up or slows down to produce the required phase correction..

The unintended action of the loop filter is the thermal (often named Johnson) noise produced by the damping resistor modulating the Vctl node resulting in frequency modulation in the VCO. This creates random jitter.

The choice of the damping resistor and VCO Kv results in a compromise between random jitter, tuning range and stability.

2

SUMMARY OF THE INVENTION

The present invention mitigates against such performance limitations of PLLs having high Kv VCOs.

The present invention is based on the concept of producing a VCO with two independent control electrodes which have different Kv, called Kv_high Kvjow. There are several preferred ways the VCO can be implemented, with a preferred embodiment being described further below.

According to a first aspect of the invention there is provided an improved loop filter comprising a frequency dependent potential divider having a relatively high Kv input node and a relatively low kv input node; and a loop filter capacitor coupled in series with the frequency dependent potential divider, wherein the relatively high kv input node lies on the coupling between the frequency dependent potential divider and the loop filter capacitor.

Preferably, the relatively low kv node is coupled to the gate of a first transistor, and the relatively high kv node is coupled to the gate of a second transistor. The sources of the first and second transistors are coupled together, and the drains of the first and second transistor are coupled to a common node, that is couplable to a control input of a voltage controlled oscillator.

According to a second aspect there is provided a phase locked loop circuit comprising the loop filter of the first aspect.

Specific embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a simplified circuit diagram of a typical passive loop filter used in PLL circuits with high Kv VCOs;

Figure 2 shows a simplified circuit diagram of a loop filter demonstrating the principles of the present invention; and

Figure 3 shows a simplified circuit diagram of an improved loop filter according to a preferred embodiment of the present invention.

3

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

A loop filter according to a preferred embodiment of the present invention is shown in Figure 2 whereby the VCO input Vctrl and Vctrl2 are the low Kv input and the high Kv input, respectively.

The high Kv input is connected to the junction between the damping resistor and the loop filter cap. This is a low noise stable node with a slow response to loop adjustment, and gives the PLL a wide tuning range without producing excess jitter.

The low KV input is connected to the active end of the damping resistor and performs the high speed correction. In order to maintain the same loop characteristic it is often necessary to increase the damping resistor value compared to the single VCO input configuration. However the resistor noise Kv product is lower which reduces the jitter.

A factor of 2 improvement in jitter has been demonstrated without an increase in loop filter area.

The are several possible ways in which a split Kv VCO may be implemented. One commonly used implementation is a PMOS current starved ring as shown in Figure 3. The Kv of each electrode is proportional to the gain of the PMOS and the summing point for the two Kv contributions is in the PMOS drain connections.

However, the present invention is not restricted to this particular VCO implementation, and other ways are contemplated by the present invention.

Example improvement factor achieved by this invention

Assuming the least aggressive implementation of the invention where Kvjow = Kv_high, then to maintain the same PLL bandwidth it is necessary to increase the damping resistor by a factor of 2. This increases the thermal noise from the damping resistor; however the overall jitter associated with the damping resistor is decreased by a factor of V2.

4

For PLLs based on high Kv VCOs the random jitter associated with the damping resistor is usually the largest single jitter contribution, thereby making the improvement very significant.

More aggressive Kv ratios have been successfully demonstrated.

5

Claims

1. A loop filter circuit comprising:

a frequency dependent potential divider having a relatively high Kv input node and a relatively low kv input node; and a loop filter capacitor coupled in series with the frequency dependent potential divider, wherein the relatively high kv input node lies on the coupling between the frequency dependent potential divider and the loop filter capacitor.

2. A loop filter according to claim 1, wherein the frequency dependent potential divider comprises a a damping resistor.

3. A loop filter according to claim 1, wherein the frequency dependent potential divider comprises a pair of resistors.

4. A loop filter according to claim 3, wherein the pair of resistors are of substantially equal size.

5. A loop filter according to any one of claims 1 to 4,

wherein the relatively low kv node is coupled to the gate of a first transistor, and the relatively high kv node is coupled to the gate of a second transistor,

wherein the sources of the first and second transistors are coupled together, and the drains of the first and second transistor are coupled to a common node, the common node couplable to a control input of a voltage controlled oscillator.

6. A Phase Locked Loop circuit comprising:

a loop filter according to any one of claims 1 to 5; and a voltage controlled oscillator operable to receive at least one of a relatively low kv signal from the low kv input node, and a relatively high kv signal from the high kv input node.

6

7. A Phase Locked Loop circuit comprising:

a loop filter according to any one of claims 1 to 4; and a voltage controlled oscillator having a first control input for receiving a relatively low kv input signal from the low kv input node, and a second control input for receiving a relatively high kv input signal from the high kv node.

8. Subject matter of the foregoing description in any novel or inventive combination thereof.

9 The subject matter of the statements of invention characterized by the features recited therein.