GB2498942A

GB2498942A - Multiplexing streams on to faster serial lanes for power saving, wherein stream synchronisation characters are replaced with stream identifiers

Info

Publication number: GB2498942A
Application number: GB201201589A
Authority: GB
Inventors: Iain Robertson; Richard Williams; Benjamin Kerr
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2012-01-31
Filing date: 2012-01-31
Publication date: 2013-08-07
Also published as: GB201301765D0; GB2500969A; GB201201589D0

Abstract

The invention notes that higher speed serial links have higher power draws than lower speed serial links, but that the power draw on a fully loaded higher speed link is lower (Fig. 3b) than on multiple lower speed links (Fig. 3a) providing the same overall bandwidth. The invention discloses lane bonding circuitry to aggregate/multiplex multiple streams on to the faster serial lane to reduce total power draw. The invention discloses overwriting sync words/alignment markers in at least one of the streams in order to allow the streams to be identified and distinguished. The streams may be CPRI (Common Public Radio Interface) channels. The alignment markers may be K28.5 comma markers. The invention may be implemented as a data conversion gasket between an ASIC core and a high speed serial link.

Description

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IDENTIFICATION OF DATA STREAMS IN AGGREGATED SERIAL LINKS

FIELD OF THE INVENTION

The present invention relates to high-speed serial links, and more particularly, to improvements in conveying and identifying data streams in aggregated high-speed serial links which enable a reduction in power consumption.

BACKGROUND OF THE INVENTION

As the volume of data consumed by individuals increases due to the explosive growth of video applications and wireless internet access there is a need to provide faster and more efficient serial links for data transfer between components in network equipment.

This problem is found in many situations, including systems in which a SerDes or Serializer/Deserializer is utilised, and has driven the data rates offered by SerDes technology from about 5Gbps offered in 2007 to around 25Gbps being offered today. With this increase in maximum data rate comes an increase in power consumption. More power is consumed when transferring data at a data rate of 5Gbps between devices capable of transferring data at a data rate of 25Gbps than when transferring data at a data rate of 5Gbps between devices that are not capable of transferring data at higher rates.

The inventors have realized, however, that when this power consumption is normalized to the amount of data transferred there is found to be a power advantage. For instance, 5Gbps of data can be transmitted and received by expending about 60mW, whereas 25Gbps of data can be transmitted and received by expending about 250mW. Since the amount of power consumed by a networking system is a significant constraint, the availability of high speed but power efficient SerDes offers a benefit for users of more moderate speeds in areas where the highest speeds are not available, either due to the communication medium being

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used, or, due to the existence of interoperable communication standards.

SUMMARY OF THE INVENTION

In accordance with the present invention, however, it is possible to combat this effect by allowing high speed data links to be used in lieu of lower speed data links and thereby gain a power advantage in the system overall. This is because there is more throughput of data for a similar amount of power consumed.

In accordance with the present invention, an apparatus and method have been devised to identify the data streams without affecting anything except for the SerDes link which is doing the aggregation or lane bonding, and separation.

According to the present invention there is provided lane bonding circuitry for combining data streams and routing them onto at least one relatively fast data lane of a plurality of data lanes of a high-speed serial link, comprising: circuitry for changing markers in at least one of said data streams being a predetermined data stream for alignment at higher layers, said circuitry operable to replace markers in said predetermined data stream with unique markers for identifying said predetermined data steam from the or another data stream with which it is combined and transmitted on said relatively fast data lane.

Further aspects of the present invention further are as set forth in the accompanying claims.

Preferably the circuitry further comprises a bypass path along which at least one data stream is able to travel at its original data rate and/or without aggregation with another data stream.

An advantage of the invention is that it allows high speed data links to be used in place of lower speed data links, thereby providing a power advantage in the system overall.

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Another advantage of the present invention is that is simple to implement and robust.

Further advantages that are realised in respect of the invention are a reduced silicon area and a reduction in the board resources consumed, since it is possible to reduce the number of serial links employed in a system.

Examples of the invention will now be described, with reference to the accompanying drawings, of which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a block diagram of a lane bonding IP in accordance with a preferred embodiment of the invention;

Figure 2 is a high level block diagram showing SerDes Lane Bonding IP ASIC Integration in accordance with a preferred embodiment of the invention;

Figure 3a is a high level block diagram showing a conventional serial link scheme; and

Figure 3b is a high level block diagram showing transmitter-side and receiver-side lane bonding IPs used with SerDes circuits for data aggregation and separation in accordance with a preferred embodiment of the invention, and the power saving to made over the conventional system and scheme shown in Figure 3a.

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

Data links between the receiver-side and transmitter-side of a serial link are more efficient if the data rate is larger, i.e. if there is a greater throughput of data in the same period of time. Currently there is a trend to use faster serial links such as SerDes that operate at fast data rates, however these serial links also need to be able to accommodate slower rate data streams from other applications/devices and from legacy devices. Therefore there is latency in the serial link, or a waste of resources in that a similar amount of power is used for

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streaming data at a slow rate as is consumed when streaming at a fast rate. Hence it would be more efficient if data were steamed at a faster rate.

In many systems, as shown in Figure 3a, data streams enter the system at a low speed, for instance a common rate used in wireless infrastructure products is 4.9152Gbps and the data is transmitted using a protocol such as the CPRI protocol. This is determined by the equipment that is attached to the system. Once the 4.9152Gbps data streams are in the system they are transferred between different components. In conventional systems, as shown in Figure 3a, the data streams are separately routed around the system with each data stream using its own set of serial links.

However, it is possible over short links to aggregate streams together and transmit, for instance, two streams over a single serial link capable of transmitting data at 9.8304Gbps, as illustrated in Figure 3b. To allow this to be done seamlessly the data streams must be identified so that each data stream can be routed to the correct end point. It is not desirable to insert extra information in the data streams, or to alter the communication protocols that are conveying the data streams. Therefore a method according to the present invention has been devised to identify the data streams without affecting anything except for the SerDes link that is doing the aggregation and separation.

Each data stream contains special markers to align the data at the protocol level. In the case of the CPRI protocol 8b/10b data encoding is used and the special marker is a bit pattern known as K28.5. In the method of the present invention, here the transmitter of the aggregated data stream finds the K28.5 markers in a predetermined data stream and changes them to another suitable marker, for instance the K28.0 markers. At the receiver the K28.0 is found and this identifies the data stream that is carrying it as the predetermined data stream. The K28.0

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pattern is substituted for the K28.5 pattern and the data is passed to the correctly identified end point.

In the embodiment of Figure 3b, each J1 chip connects to 3 T1 chips, and the power saving for this configuration is approximately 0.5W calculated as follows using values from Table 1 given above:

1 x J1 and 3 x T1 = 53.6W without aggregation, and

53.1W with aggregation.

In general any number of data streams can be aggregated and transmitted over a single link that is capable of transmitting the aggregated data rate. The individual streams do not need to have the same rates nor be using the same communication protocols. One of the data streams is predetermined as the data stream where a unique signature of the data stream can be exchanged for another unique signature. When this new unique signature is found at the receiver of the aggregated data streams all the data streams can be separated and routed to the correct end points. The new unique signature is exchanged for the original one in the predetermined data stream.

Examples of preferred combinations of aggregated data streams transmitted using the lane bonding IP of the present invention implemented as implemented in two types of SerDes IP blocks, are given in Table 1, together with indications of the power savings that can be achieved.

TABLE 1

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Rate (Gbps) 4 lanes 3 lanes 2 lanes 1 lanes

Houdini B8

1.2288

560

450

335

220

2.4576

595

475

355

235

3.072

650

515

385

255

4.9152

500

375

250

6.144

680

545

405

270

9.8304

765

605

<450}

290

Rincewind B8 1.2288 275 220 165 105

2.4576 <295> 235 175 115

3.072 320 255 190 125

4.9152 Cfjo) 245 185 120

6.144 335 270 200 1.3Q

9.8304 340 270 C^OO) <130>

The technique employed by the present invention affords a number of advantages over conventional schemes for transmitting data over high speed serial links. Firstly, by combining the data lanes of the SerDes link, a reduction in power is achieved without needing to change supported features. Furthermore, the SerDes lane bonding IP can be implemented as simple logic typically of the order of a few hundred gates, that can be added to the chip for it to function in this way. This enables future systems to achieve a reduction in power consumption in a simple and efficient manner.

In a preferred embodiment, at the transmitter-side, the SerDes lane bonding IP for aggregating the data streams may be implemented as a data conversion gasket that can be coupled between the protocol block(s) and the SerDes macro.

Preferably at the receiver-side, the data segregation IP for segregating the received data steams also may be implemented as a data conversion gasket, i.e. a circuit block that can be coupled between the SerDes macro and the protocol block(s).

The transmitter-side and the receiver-side data conversion gaskets are provided with a bypass so as to retain the original functionality, and data streams and rates of the ASIC generating the data stream(s) . In this way current systems are still

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supported as no change is required to the transmitter-side circuitry, the data channels, or the receiver-side circuitry. A single control bit from the protocol block is used to switch the data conversion gasket between data aggregation/segregation mode and the bypass mode.

Furthermore, transmit lane bonding and receive lane bonding operate independently, so it is possible to have bonded lanes in the transmit direction, whilst bonding may not be operating in the receive direction.

In addition, if an incompatible SerDes lane configuration is enabled, then lane bonding will be automatically disabled. Moreover, lane bonding can be enabled by default, and will then occur for all SerDes lanes whose configuration is compatible with lane bonding. An IEEE1500 interface is provided to allow the status of lane bonding to be observed, and to disable lane bonding globally, or on a per-lane basis.

Preferably, the data conversion gaskets will use and provide current clocks, and take care of 8b/10b disparity and aggregation / segregation.

A preferred embodiment of the present invention, according to a first aspect, comprises a SerDes lane bonding IP as illustrated in the block diagrams of Figures 1, 2 & 3b. The SerDes lane bonding IP operates by examining the SerDes lane configuration, and automatically multiplexing lanes operating in sub-rate modes (half-rate, quarter-rate or eighth-rate) into master lanes operating at a higher data-rate. In all bonding scenarios, the lane bonding IP does not operate the master lanes at a rate greater then that achievable at full-rate.

The lane bonding IP uses a unique signature or identification marker for identifying data belonging to each particular data stream, and adds this to each data stream before it is aggregated with other data streams at the transmit multiplexer and routed over the required data lanes or channels.

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The receiver-side de-multiplexer recreates the original input data, allowing the lane bonding function to appear transparent to the ASIC core logic.

In order to recover the original lane order data prior to de-multiplexing, the receiver must examine the receive data to determine how to de-multiplex the data. To prevent receive bit-errors from disturbing the receive de-multiplex alignment, the receiver implements a state-machine to control the demultiplexer alignment. The receiver implements hysteresis to ensure that single bit errors in the alignment character will not cause the alignment to jump incorrectly. The alignment state-machine is re-started if the lane configuration is changed, and the force_align control can be used to re-start the alignment state-machine if incorrect alignment is observed in the protocol layer.

Preferably, the SerDes lane bonding IP is implemented as a hard-IP macro. The lane bonding IP's SerDes interface is intended to connect by abutment directly onto the SerDes core-side interface, and will also connect to the SerDes VDD & VSS power supplies.

Figure 2 shows how the SerDes lane bonding IP would be integrated into an ASIC solution with a SerDes. The SerDes lane bonding IP is placed across the core-side SerDes interface, and connects directly to the SerDes core-side interface. The SerDes lane bonding IP then presents a replica SerDes core-side interface to the ASIC core-logic. All SerDes signals not used by the SerDes lane bonding IP will be buffered through the IP. The SerDes REFCLK signals are also routed over the IP without buffering.

The SerDes lane bonding IP will introduce an additional latency in both transmit and receive directions. This latency is incurred even when lane-bonding is disabled globally, or on a per-lane basis.

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In a preferred embodiment, the SerDes lane bonding IP will utilize ATPG DFT to test the logic. ATPG test vectors will be applied using the IEEE1500 interface. Additional DFT coverage of the SerDes Lane Bonding IP can only be achieved when used in conjunction with the SerDes WS_EXTEST DFT mode. When the SerDes is operated in this mode, many of the combinational feed-through paths from the ASIC core, through to the SerDes can be tested.

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Claims

1. Lane bonding circuitry for combining data streams and routing them onto at least one relatively fast data lane of a plurality of data lanes of a high-speed serial link, comprising:

circuitry for changing markers in at least one of said data streams being a predetermined data stream for alignment at higher layers, said circuitry operable to replace markers in said predetermined data stream with unique markers for identifying said predetermined data steam from the or another data stream with which it is combined and transmitted on said relatively fast data lane.

2. Data stream aggregation circuitry for transmitting data over a serial link, comprising:

alignment circuitry operable to change markers in at least one of said data streams being a predetermined data stream for alignment at higher layers, said circuitry operable to replace markers in said predetermined data stream with unique markers for identifying said predetermined data steam from the or another data stream with which it is combined and transmitted on said relatively fast data lane.

3. Circuitry according to claim 1 or 2, implemented as a hard IP macro.

4. Circuitry according to any one of claims 1 to 3, wherein the lane bonding circuitry is implemented as a data conversion gasket couplable between the ASIC core and the high speed serial link.

5. Circuitry according to any one of claims 1 to 4, further comprising a bypass path along which at least one data stream is

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able to travel at its original data rate and/or without aggregation with another data stream.

6. Data separation circuitry for separating received, aggregated data streams and routing them onto correct end points, comprising:

identification circuitry for identifying unique markers in data received from a relatively fast data path, said markers indicating the alignment of separate data streams in the received data; and circuitry for routing each identified said separate data streams onto an appropriate data path associated with the type of identified data stream.

7. The data separation circuitry according to claim 6, wherein the data separation circuitry is implemented as a data conversion gasket couplable between the high speed serial link and ASIC core.

8. A transmitter-side circuit comprising the lane bonding circuitry of claims 1 to 5.

9. A receiver-side circuit comprising the data separation circuitry of claims 6 & 7.

10. A SerDes circuit comprising:

the transmitter-side circuit of claim 8; the receiver-side circuitry of claim 6 or 7; and a high speed serial link coupled between the transmitter-side circuitry and the receiver-side circuitry, said high speed serial link comprising a plurality of data lanes at least one of which is a relatively fast data lane onto which said aggregated data steams are routed.

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11. A SerDes circuit according to claim 10, wherein said plurality of data lane of the high-speed serial link, comprises at least one relatively fast data lane and at least one relatively slow data lane.

12. Subject matter of the foregoing description in any novel or inventive combination thereof.

13. The subject matter of the statements of invention characterized by the features recited therein.