GB2497664A

GB2497664A - Substrates for preparing polycrystalline diamond

Info

Publication number: GB2497664A
Application number: GB201222329A
Authority: GB
Inventors: Timothy Mollart; Quanzhong Jiang; Christopher Rhys Bowen; Duncan William Edward Allsopp; Michael John Edwards
Original assignee: Element Six Ltd
Current assignee: Element Six Ltd
Priority date: 2011-12-16
Filing date: 2012-12-12
Publication date: 2013-06-19
Anticipated expiration: 2032-12-12
Also published as: GB201222329D0; WO2013087707A1; GB2497664B; GB201121659D0

Abstract

A composite substrate comprising a silicon wafer 10 and a silicon oxide layer 12 is provided with a bonding layer 14 on which a polycrystalline diamond layer 16 is grown. The composite wafer is removed using preferential etching which does not etch the bonding layer or the diamond layer. The bonding layer may be a different material to silicon or silicon dioxide or it may be silicon having a different crystal orientation to the underlying silicon portion of the composite wafer. An edge etch stop may be provided around edge regions of the bonding layer attached to the polycrystalline diamond layer (see figure 3). In an alternative method a doped, electrically conductive region is provided in a portion of the substrate to be removed and an electrically resistive layer is bonded to the polycrystalline diamond layer and the doped, electrically conductive portion of the substrate is removed by electrochemical etching or electrochemically assisted etching.

Description

SUBSTRATES FOR SEMICONDUCTOR DEVICES

Field of Invention

The present invention relates to the manufacture of substrates for semiconductor devices.

Background of Invention

Optoclectronic, high power, and high frequcncy devices are increasingly being fabricated using wide band gap compound semiconductor materiak such as gallium nitride, aluminium nitride, and silicon carbide. Such semiconductor materials are frequently grown heteroepitaxially in thin film form onto a suitable substrate which provides a template for crystal growth. Typical substrates include sapphire, silicon carbide, and silicon. For semiconductor devices such as microwave amplifier circuits, the substrate should be electrically insulating for the device to function.

A well known problem in semiconductor devices is that of heat dissipation. High temperatures oftca limit the performance and/or lifetime of such devices. This is a particular problem in semiconductor devices which operate at high power and/or high frequency such as microwave amplifiers, power switches and optoelcctronic devices.

It is therefore desirable to be able to spread any heat generated by component devices to reduce temperatures and thus improve device performance, increase device lifetime, andlor increase power density. Accordingly, it is desirable to utilize a substrate material with a high thermal conductivity to spread the heat generated by a device, lowering the power density and facilitating dissipation via a heat sink thus improving device performance, increasing lifetime, and/or enabling an increase in power density.

Diamond has unique properties as a heat spreading material, combining the highest room temperature thermal conductivity of any material, with high electrical resistivity and low dielectric loss when in an intrinsic undoped form. Thus diamond is utilized as a heat spreading substrate for semiconductor components in a number of high power density applications. The advent of large area polycrystallinc diamond produced by a chemical vapour deposition (CVD) technique has expanded the applications for diamond heat spreaders via an increase in area and a reduction in cost. The majority of favourable thermal, dielectric and insulating properties of diamond are not dependent on the single crystal structure of naturally occurring or synthetic single crystal diamond materiaL Accordingly, polycrystalline CVD diamond wafers have been developed and are commercially available in sizes that enable them to be directly integrated with the fabrication processes of wide band gap semiconductors as a substrate material.

In light of the above, it is evident that for thin film compound semiconductor materials, an ability to integrate diamond as a carrier substrate coukl greatly improve thermal performance. For high power devices, the challenge is to position an active region of a device in as close proximity as possible to the heat spreading diamond substrate, since any intermediate carrier substrate material such as sapphire, silicon, or silicon carbide acts as a thermal barrier.

Compound semiconductor materials can be grown directly on a polycrystalline diamond substrate using, for example, a metal organic vapour phase epitaxy (MOYPE) technique. However, semiconductor material grown in such a manner will itself be polycrystalline, the crystals being distributed over a range of crystallographic orientations relative to the plane of the substrate. Such a polycrystalline layer of semiconductor material will tend to have relatively low charge mobility and thus will not provide good device performance for many proposed applications, particularly those which require high charge (electron and/or hole) mobility characteristics such as a high electron mobility transistor (HEMT) used in microwave frequency amplifier circuits. As such, it is desirable to provide a method which allows the formation of a monocrystalline semiconductor layer.

US 7,595,507 and US 2010/0001293 disclose methods of forming semiconductor device substrates which comprise growing diamond over a monocrystalline silicon carbide layer. US 2009/0272984 also discloses a method of forming a semiconductor device substrate comprising diamond and silicon carbide. Such composite diamond-silicon carbide substrates can be used to form semiconductor devices. When forming such dcviccs, the mono-crystalline silicon carbide layer can be used to grow a monocrystalline semiconductor layer thereovcr.

US 2006/0 113545 discloses substrate structures comprising silicon-diamond-silicon multilaycr structures. One problem with using silicon is that it offers relatively poor thermal and resistivity properties compared to silicon carbide. As such, it is desirable to make the silicon layer very thin such that the polycrystalline diamond will be disposed close to the active semiconductor components to effectively dissipate heat generated during operation.

Various prior art documents disclose methods of growing polycrystalline diamond on a substrate, reducing the thickness of the substrate to form a thin single crystal layer disposed on the polycrystalline diamond, and then growing active semiconductor layers on the thin single crystal layer. Examples of such prior art documents are briefly discussed below.

WO 2005/122284 and WO 2006/100559 disclose growth of polycrystalline diamond material on a silicon wafer followed by thinning of the silicon wafer by grinding or lapping to achieve a thin layer of silicon disposed on the polycrystalline diamond material.

EP0442304 discloses growth of polycrystallinc diamond material on a silicon wafer.

It is described that a thin layer of single crystal silicon carbide forms at an interface between the silicon and diamond material during growth. The document suggests that the silicon wafer can be removed to leave the thin layer of silicon carbide adhered to the polycrystalline diamond material and this thin layer of silicon carbide can be used as a growth surface for fabrication of semiconductor layers. The present inventors consider that this is incorrect as they have found that while a thin layer of silicon carbide does form at the interface between the silicon and diamond materials, this layer is amorphous and found the latter not suitable for fabricating single crystal semiconductor materials thereon by cpitaxial growth.

W02005/074013 and US 2009/0272984 disclose ion implanting a buried Si02 layer into a silicon carbidc wafer, growing polycrystallinc diamond material on the wafer, and then removing the bulk of the silicon carbide wafer by using the implanted Si02 layer as a release layer.

US 7.595,507 discloses ion implanting a buried 5i02 layer of 100 nm to 200 nm thickness into a silicon wafer, growing polycrystalline diamond material on the wafer, and then removing the bulk of the silicon wafer using a wet etch with the thin buried Si02 layer acting as an etch stop to achieve a thin layer of silicon disposed on the polycrystalline diamond material.

US 7,695,564 discloses a similar method which comprises ion-implantation of oxygen into a silicon wafer to form a wafer comprising a bulk silicon wafer layer of an unspecified thickness, a buried oxide layer having a thickness of approximately 100-nm, and a silicon overlay structure having a thickness of 50-500 nm. A polyerystalline diamond film of approximately 200 to 1500 micrometers is grown on the silicon overlayer. The bulk silicon wafer layer and the buried oxide layer are then removed to leave a composite structure comprising the polycrystalline diamond film and the silicon overlayer. A number of different methods are described for removing the silicon to form a diamond substrate with a thin silicon overlayer including: (1) selectively dissolving the buried oxide layer; (2) wet etching the bull silicon layer followed by wet etching of the buried oxide layer; (3) lapping and polishing the bulk silicon layer followed by wet etching; or (4) lapping and polishing the bulk silicon layer followed by dry etching. The finished silicon-on-diamond substrate consists of an approximately 50 to 200 nm thick monocrystalline silicon film which is epitaxially thsed to an approximately 300 to 1500 micrometer thick polycrystalline diamond substrate.

While it would seem to be simple in principle to apply any of the aforementioned techniques to thin down a substrate wafer after polyerystalline diamond growth thereon to achieve a polycrystalline diamond wafer with a thin layer of the substrate wafer adhered thereto, in practice a problem exists with known prior art techniques.

Namely, as the substrate wafer is thinned down cracking occurs in the thin layer such that although a thin layer is achieved it is not of high quality. This is problematic because the quality of the thin layer will affect the quality of the semiconductor layers epitaxially grown thcreover to form an electronic device and this detrimentally affects device performance. In particular, the present inventors have found that as the single crystal layer adhered to the polycrystalline diamond material is thinned to a depth of less than 100 m cracks begin to form in the thin layer of single crystal material. One contributing factor to cracking is mechanical damage caused by grinding, lapping, and polishing techniques. As such, it can be advantageous to use an etching technique as described in several of the previously discussed prior art documents to avoid the possibility of mechanically introducing damage into the thin layer of single crystal material. Furthermore, etching can produce a uniformly thick layer of single crystal material even if the composite wafer structure is slightly bowed.

However, one problem with such etching techniques is to achieve efficient removal of the bulk of the substrate wafer without removing portions of the thin layer of substrate wafer material adjacent the polycrystallinc CVD diamond material. In this regard, etching of major faces of the thin layer of substrate wafer material adjacent the polycrystalline CYD diamond material can be prevented by the presence of the polycrystalline CVD diamond on one major face and an etch-stop layer such as SiO2 on the opposite major face of the thin layer of substrate wafer material as described in the prior art. However, the present inventors have found that such an etch stop layer does not prevent significant etching of the thin layer of substrate wafer material adjacent the polycrystalline CVD diamond material at exposed edge regions.

It is an aim of certain embodiments of thc present invention to solve the aforementioned problem.

Summary of Invention

According to a first aspect of the present invention there is provided a method of manufacturing a composite substrate for a semiconductor device, the method compnsing: selecting a substrate wafer comprising at least a layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon;

S

growing a first polycrystallinc diamond layer on thc substrate wafer using a chemical vapour deposition technique to form a composite comprising the substrate wafer bonded to the polycrystalline diamond layer via said layer; and removing a portion of the substrate wafer material using an etching technique to form a composite substrate comprising the polyerysta!line diamond layer directly bonded to said layer of substrate wafer material, wherein said layer of substrate material has a thickness of no more than 100 urn, wherein the etching technique is configured to preferentially remove the portion of substrate material relative to said layer of substrate wafer material bonded to the polycrystalline diamond layer, said etching technique comprising one or more of: selecting an anisotropic etchant which etches the portion of substrate material at a faster rate than said layer of substrate wafer material bonded to the polycrystalline diamond layer; providing an edge etch stop around edge regions of said layer of substrate wafer material bonded to the polycrystal line diamond layer; and providing a doped, electrically conductive portion of the substrate to be removed and an electrically resistive layer bonded to the polycrystalline diamond layer and removing the doped, electrically conductive portion of the substrate by electrochemical etching or electrochemical assisted etching.

Brief Description of thc Drawing

For a better understanding of the present invention and to show how the same may be carried into effect, embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 illustrates a prior art method of fabricating a thin silicon-on-diamond composite substrate; Figure 2 illustrates a method of fabricating a thin silicon-on-diamond composite substrate according to a first embodiment of the present invention; Figure 3 illustrates a method of fabricating a thin silicon-on-diamond composite substrate according to a second embodiment of the present invention; Figure 4 illustrates a method of fabricating a thin silicon-on-diamond composite substrate according to a third embodiment of the present invention; Figures 5(a) and 5(b) illustrate a prior art method of fabricating a thin silicon-on-diamond composite substrate; Figures 6(a) to 6(c) illustrate a method of fabricating a thin silicon-on-diamond composite substrate according to an embodiment of the present invention; and Figure 7 illustrates a composite substrate comprising a compound semiconductor layer disposed thereon.

Detailed Description of Certain Embodiments

Figure 1 illustrates a prior art method of fabricating a silicon-on-diamond composite substrate. A substrate wafer is provided comprising a handling wafer 2, an etch stop layer 4, and a thin layer of single crystal material 6. The handling wafer 2 and the thin layer of single crystal material 6 may be formed of a silicon wafer while the etch stop layer 4 may be formed of an implanted Si02 layer. A layer of polycrystalline C'VD diamond material S is grown over the substrate wafer to produce a layered structure as shown in Figure 1(a).

As illustrated th Figure 1(b), the silicon material is then etched away by immersing the layered structure in an etch bath. A chemical etchant may be used to selectively etch away the handling wafer without etching the etch-stop layer. An example of such an etchant is EDP (an aqueous solution of ethylene diamine and piyocatcchol.

However, one problem with this method is that the etchant also etches exposed edge regions of the thin layer of single crystal material 6 as illustrated by the arrows shown in Figure 1(b) which indicated areas where the silicon material is being etched away.

After removal of the handling wafer the Si02 layer can then be removed using an etchant which preferentially etches the Si02 without etching the thin layer of single crystal silicon material adjacent the polycrystalline diamond layer. An HF acid etchant is suitable for this purpose. The resultant silicon-on-diamond layered structure is illustrated in Figure 1(e). As can be seen, at edge regions of the polycrystalline CVD diamond layer the silicon material has been removed due to etching of the thin layer of silicon at edge regions. This edge removal reduces the area of the silicon-on-diamond substrate fabricated using prior art techniques and any edge removed regions must be cut away to form the final product as illustrated in Figure 1(d). As such, prior art methods can result in a significant quality of polycrystalline CVD diamond material being discarded. The reduction in area of the resultant silicon-on-diamond substrate is disadvantageous for end uses. Furthermore, the loss of polycrystalline CVD diamond material during the fabrication process is inefficient.

Accordingly, the present inventors have found that even if an etch stop layer is provided within a layered substrate wafer this does not prevent significant etching of a thin layer of substrate wafer material adjacent polycrystalline CVD diamond material at exposed edge regions when fabricating a silicon-on-diamond substrate. The present inventors have solved this problem by providing an etching technique configured to preferentially remove a portion of substrate material relative to a layer of substrate wafer material bonded to the polycrystallinc diamond layer. A number of possible configurations have been conceived including one or more of: (1) selecting an anisotropic etchant which etches the portion of substrate material at a faster rate than the layer of substrate wafer material bonded to the polycrystalline diamond layer; (2) providing an edge etch stop around edge regions of the layer of substrate wafer material bonded to the polycrystalline diamond layer; and (3) providing a doped, electrically conductive portion of the substrate to be removed and an electrically resistive layer bonded to the polycrystalline diamond layer and removing the doped, electrically conductive portion of the substrate by elcctrochemical etching or elcctrochemically assisted etching.

In one arrangement an anisotropic etchant can be selected which can etch the handling wafer at a considerably faster rate than the first layer of single crystal material adjacent the polycrystafline CYD diamond. The handling wafer may be formed of a different material to the layer of single crystal material adjacent the polycrystalline CYD diamond layer or otherwise formed of the same material but which presents different crystallographically orientated surfaces to the anisotropic etchant and the anisotropic etchant is selected to etch the handling wafer at a faster rate than the layer of single crystal material adjacent the polycrystalline CVD diamond layer due to the aforementioned difference in material or crystallographic orientation.

Such an etchant can avoid undue edge etching of the first layer of single crystal material during removal of the handling wafer. For example, KOI-I solution etches a {l00} oriented silicon handling wafer (i.e. a silicon handling wafer having (100) major faces) approximately 400 times faster than a silicon layer having {1 11 oriented major faces adjacent the polycrystalline CVD diamond layer. Accordingly, if 111} oriented silicon is used for the thin layer of material adjacent the polyciystallinc CVD diamond and (100) oriented silicon is used for the handling wafer, then an anisotropic etch can be applied such that the handling wafer is removed without significantly etching away the edges of the (111) oriented silicon adjacent the polycrystallinc CVD diamond.

Such a method is illustrated in Figure 2. A substrate wafer is provided comprising a handling wafer 10 formed of {]00} oriented silicon, an etch stop layer 12 formed of Si02, and a thin layer of single crystal material 14 formed of {I 11} oriented silicon.

A layer of polycrystalline CVD diamond material 16 is grown over the substrate wafer to produce a layered structure as shown in Figure 2(a).

As illustrated in Figure 2(b), the silicon material is then etched away by immersing the layered structure in an etch bath. An anisotropic chemical etchant may be used to selectively etch away the handling wafer without etching the etch-stop layer 12 or the thin layer of single crystal material 14 by selecting a suitable ctchant and suitable materials for the layered substrate wafer. In this instance, if a (100} oriented silicon material is selected for the handling wafer 10 and a {1 11} oriented silicon material is selected for the thin layer of single crystal material 14 then KOH etchant can be used to remove the handling wafer without any significant loss of the thin layer of single crystal material 14 due to edge etching at exposed areas.

After removal of the handling wafer the Si02 layer can then be removed using an etchant which preferentially etches the SiO without etching the thin layer of single crystal silicon material adjacent the polycrystallinc diamond layer. An HF acid etchant is suitable for this purpose. The resultant silicon-on-diamond layered structure is illustrated in Figure 1(c). No or very little exposed edge regions arc obtain such that the thin layer of silicon covers substantially all of a major face of the polycrystalline CVD diamond layer.

Alternatively, the above described problem of edge etching can be solved by providing an etch stop around the edges of the first layer of singk crystal material.

For example, one advantageous method involves overgrowing the CYD diamond material around the sides of the substrate wafer such that edge grown CYD diamond material masks the edges of the first layer of single crystal material and functions as an etch stop during subsequent processing of the substrate wafer.

Such a method is illustrated in Figure 3. A substrate wafer is provided comprising a handling wafer 20, an etch stop layer 22, arid a thin layer of single crystal material 24.

A layer of polycrystallinc CVD diamond matcrial 26 is grown over the substrate wafer to produce a layered structure as shown in Figure 3(a). The polycrystalline C'VD diamond material is overgrown down side edges of the substrate wafer at least as far as the etch stop layer 22 so as to mask the edges of the thin layer of single crystal material 24 and thus form an edge etch stop 28 for the thin layer of single crystal material 24.

As illustrated in Figure 3(b), the handling wafer 20 is then etched away by immersing the layered structure in an etch bath. The cdgc etch stop 28 prevents edge etching of the thin layer of single crystal material 24.

After removal of the handling wafer 20 the etch stop layer 22 can then be removed using an etchant which preferentially etches the etch stop layer 22 without etching the thin layer of single crystal silicon material 24 adjacent the polycrystallinc diamond layer as illustrated in Figure 3(c). Finally, the edge etch stop 28 can be removed by cutting to form a silicon-on-diamond composite substrate as shown in Figure 3(d).

Alternatively, the edge etch stop 28 can be removed prior to etching of the etch stop layer 22 to achieve the same structure.

Alternatively still, the above described problem of edge etching can be solved by heavily doping the handling wafer such that it is electrically conductive while providing a first layer of single crystal material which has a high electrical resistivity.

The conductive handling wafer can then be removed by electrochemical etching without removal of the electrically resistive first layer of material.

Such a method is illustrated in Figure 4. A substrate wafer is provided comprising a handling wafer 32 formed of an electrically conductive material and a thin layer of single crystal materia' 34 formed of an electrically insulating material (or at least significantly less conductive than the material of the handling wafer). For example, such a layered structure may be formed of a handling wafer of highly doped silicon with a thin layer of un-doped material. A layer of polycrystalline CYD diamond material 36 is grown over the substrate wafer to produce a layered structure as shown in Figure 4(a).

The conductive handling wafer 32 can then be removed by electrochemieal etching without removal of the more resistive thin layer 34 to form a silicon-on-diamond composite substrate as shown in Figure 4(b).

All three of the solutions illustrated in Figures 2 to 4 share the common concept of providing an etching technique configured to preferentially remove a portion of substrate wafer material relative to a layer of substrate wafer material bonded to the polycrystalline diamond layer. This differs from the provision of a single etch stop layer within the substrate wafer which does not prevent edge etching of the layer of substrate wafer material bonded to the polycrystalline diamond layer.

The materials and layer structure of the substrate wafer can be selected to optimize preferential removal of a portion of substrate wafer material relative to a layer of substrate wafer material bonded to the polycrystallinc diamond layer. The substrate wafer may comprise a handling wafer, an etch stop layer, and a layer of single crystal material adjacent the polycrystalline CVD diamond layer. Suitable materials for the handling wafer include silicon, silicon carbide, or a nitride with silicon being preferred. The handling wafer may be formed of a material which etches at a faster rate than the layer of single crystal material adjacent the polycrystalline CVD diamond layer. For example, the handling wafer may have a different crystallographic orientation to the material of the layer of single crystal material adjacent the polycrystalline CYD diamond layer to achieve preferential etching. As described previously, this may be achieved by providing a handling wafer formed of oriented silicon, providing a layer of ill) oriented silicon adjacent the polycrystalline CVD diamond layer, and using an etchant such as KOH which etches {100 oriented silicon at a much faster rate than {1 11} oriented silicon. This requirement is not essential if an edge etch stop is provided. However, even when an edge etch stop is used it may be desirable to provide a handling wafer which has a faster etch rate such that the process can be implemented more quickly saving time and thus increasing efficiency of the production process.

The etch stop layer should be formed of a material which is not etched by etchants suitable for etching the handling wafer and the layer of single crystal material adjacent the polycrystalline CVD diamond layer. For example, if silicon is used for the handling wafer and the layer of single crystal material adjacent the polyerystalline CVD diamond layer then Si02 is suitable for the etch stop layer.

The layer of single crystal material adjacent the layer of CVD diamond material may have a thickness of: 75 urn or less; 50 tim or less; 30 um or less; 20 um or less; 10 jim or less; 5 jim or less; 3 jim or less; 2 jim or less; or 1 jim or less, Ideally this layer should be as thin as possible such that after growth of a compound semiconductor thereon the distance between the polycrystalline CVD diamond material and the compound semiconductor is minimized to ensure good heat dissipation. However, the layer must still provide a good quality single crystal growth surface to ensure good quality epitaxial growth of the compound semiconductor.

In relation to thc above, it has bccn found to be advantagcous to form the first laycr of single crystal material to a thickness greater than 10 am or 20 am. For example. if the single crystal material is silicon then the first 10 to 20 nm of silicon at the diamond interface tends to be amorphous silicon carbide formed during CVD diamond growth.

As such, if the substrate wafer is processed to a depth less than 10 nm, the resultant film may be amorphous silicon carbide rather than single crystal silicon as desired. In this regard, it should be noted that when we refer to a silicon layer directly bonded to a CYD diamond layer, it will be understood that the interface between the silicon and the CYD diamond layer may comprise a very thin layer of amorphous silicon carbide formed during CYD diamond growth on the silicon.

The layer of single crystal material should be formed of a material which is suitable for epitaxial growth of a compound scmiconductor thcrcon. Examples includc silicon, silicon carbide, or a nitride such as aluminium nitride. One possible arrangement utilizes a high electrical resistivity 111) oriented silicon material for this layer as this material can aid in preventing electrical shorting in a device structure while also providing a good growth surface for epitaxial growth of a compound semiconductor. In addition, such a layer may be used in combination with a {100} oriented silicon handling wafer and an etchant such as KOH to achieve preferential etching of the handling wafer relative to the layer of single crystal material adjacent to the CYD diamond layer.

In addition to the above, the materials and layer structure of the substrate wafer can be selected to manage thermally induced stresses and cracking. In this regard, as the substrate wafer is thinned down cracking can occur in the thin layer which remains adhcred to the CYD diamond material such that although a thin layer is achicvcd it is not of high quality. This is problematic because the quality of the thin layer will affect the quality of the semiconductor layers epitaxially grown thereover to form an electronic device and this detrimentally affects device performance. In particular, the present inventors have found that as the single crystal layer adhered to the polycrystallinc diamond material is thinned to a depth of less than 100 xm cracks begin to form in the thin layer of singlc crystal material. While it was initially thought that such cracking may be a result of mechanical damage caused by grinding, lapping, and polishing techniques, it has been found that this same problem occurs when using etching techniques such as those described above.

The present inventors believe that the aforementioned problem of cracking of the single crystal diamond material as the material is thinned to less than 100 irn is a result of thermally induced stress generated by the CVD diamond growth process and caused by a mismatch in thermal expansion coefficient between the polycrystalline diamond material and the single crystal wafer material. For example, silicon has a much higher thermal expansion coefficient than diamond such that on cooling after CYD diamond growth the silicon wafer Si contracts more than the polycrystalline diamond D causing bowing as illustrated in Figure 5(a). During processing to thin the silicon wafer, as the layer of silicon reaches a thickness of approximately 100 jim the composite tends to flip to bow the other way such that the thin silicon layer Si is placed in tension as illustrated in Figure 5(b). This tension tends to cause the thin silicon layer to crack C. The present inventors have found that the thin silicon layer can be made more resistant to cracking under the tensioning mechanism illustrated in Figure 5(b) if a relatively thick layer of Si02 is introduced into the silicon wafer prior to CYD diamond growth thereon. While not being bound by theory it is postulated that this reduction in cracking may be due to the relatively thick Si02 layer functioning as a crack stop and/or the relatively thick Si02 layer functioning to pre-compress the thin overlying layer of single crystal silicon material during CVD diamond growth due to its lower thermal expansion coefficient such that it is more resistant to tensile stress induced during processing of the silicon wafer to achieve a thin layer. In either case, it is important that the Si02 layer should have a thickness sufficient to fulfil either or both of these functions.

This is illustrated in Figure 6. As shown in Figure 6(a) bowing of the substrate after CYD diamond growth thereon can still occur as described previously. Furthermore, as described previously, during processing to thin the silicon wafer, as the layer of silicon reaches a thickness of approximately 100 im the composite tends to flip to bow the other way such that the thin silicon layer Si is placed in tension as illustrated in Figurc 6(b). However, even if cracks C form in the silicon handle wafer thesc cracks are prevented from propagating into the thin silicon layer adjacent the CVD diamond material by the relatively thick Si02 layer. Further processing can remove the remaining silicon and the Si02 layer thus leaving a thin silicon layer adhered to the CYD diamond material without any significant cracking. As illustrated in Figure 6(c).

For example, if a very thin layer of Si02 is provided then this layer will not provide sufficient compression to the thin layer of single crystal material during CYD diamond growth and/or not provide a sufficient barrier to crack propagation into the thin layer of single crystal material adjacent the polycrystalline diamond layer during processing. Common ion implanted Si02 buried oxide layers are usually of the order of 100 to 200 nm. While such layers arc sufficient to ftinction as effective etch stops or release layers as described in the prior art, it is believed that such thin layers are insufficient to generate the pre-compression and/or crack stop functionality required to prevent cracking of the thin layer of single crystal material adjacent the polyciystallinc diamond layer during processing due to the tension mechanism as described herein.

As such, it is believed that it is important to select a substrate wafer with a relatively thick layer of Si02 disposed adjacent to the thin layer of single crystal material adhered to the polycrystallinc CYD diamond material. While such substrates are commercially available, known as silicon-on-insulator or SOl, substrates with thicker layers of Si02 are more expensive and thus only tend to be selected when it is considered that a thicker layer of Si02 is essential for a particular application.

Furthermore, forming a thicker layer of buried Si02 generally requires a higher implantation dose leading to increased damage of the thin layer of silicon. As previously described, it is desirable to provide a high quality thin layer of silicon to grow better quality compound semiconductor layers thereon. Accordingly, it is counter-intuitive that selecting a silicon-on-insulator substrate with a relatively thick layer of Si02 would be beneficial to achieve this function as substrates with thicker layers of Si02 formed by ion implantation would tend to have a higher degree of implantation damage. In practice, if has been found that any decrease in the quality of the thin layer of silicon due to ion implantation damage is far outweighed by the benefits of alleviating cracking due to the tension mechanism as described herein.

In light of the above, it has been found to be advantageous to provide a substrate wafer comprising a silicon handling wafer, a relative thick layer of Si02 which ifinctions both as an etch stop and as a crack stop, and a thin layer of silicon on which CVD diamond growth is performed.

Further to the above, the present inventors have realized that the prc-compression and/or crack stop mechanisms as described can be implemented using materials other than silicon and Si02. The key feature is the provision of an etch stop layer which is at least 0.5 urn thick and which is formed of a material which has a lower thermal expansion coefficient and/or is formed of a material which has a higher fracture strength that that of the thin layer of single crystal material adhered to the CVD diamond.

The etch stop layer of material may have a thickness of: 0.5 jim or more, 0.75 jim or more; 1.0 p.m or more; 2 p.m or more; or 4 p.m or more. The thickness of this layer is advantageously sufficient to act as a suitable crack-stop and/or function to pre- compress the thin overlying layer of single crystal material. However, if the pre-compression mechanism is dominant then it is envisaged that thermal mismatches between the etch stop layer and the overlying layer of single crystal material could potentially increase the problem of cracking, for example during heat-up of the substrate wafer prior to CYD diamond growth thereon. The most preferable thickness for the etch stop layer will to some extent depend on the particu'ar combination of materials and layer thicknesses used for the various layers within the substrate wafer and the thickness of the CYD diamond layer grown thereon. However, it has been found that for certain combinations of materials such as silicon and Si02 a thickness of the etch stop layer no more than 5 p.m or 10 p.m is sufficient.

To increase the effect of pre-comprcssion it may be advantageous to form the etch stop layer of material having a lower thermal expansion coefficient than the CYD synthetic diamond material. Alternatively, or additionally, to improve the etch stop layer's functionality as a crack-stop is can be advantageous to form the layer of an amorphous material. In this regard, it may be noted that Si02 can fulfil both these requirements.

As previously mentioned, in practice it can be convenient to provide a substrate wafer which further comprises a handling wafer on which the etch stop layer is disposed.

However, if such a handling wafer is provided then it must be appreciated that the handling wafer will itself contribute to stress within the thin layer of single crystal material adhered to the CYD diamond. That is, if the handing wafer is made too thick or too thin then thermally induced strain can lead to cracking of the thin layer of single crystal material. As such, the handing wafer, and preferably the substrate wafer as a whole, may have a thickness in a range: 0.3 mm to 2.0 mm; 0.3 mm to 1.8 mm; 0.3 mmto 1.5 mm; 0.3mm to 1.3 mm; 0.3mm to 1.0 mm; or 0.5mm to 0.8 mm.

Such thicknesses arc suitable for a substrate wafer having a diameter in a range: 20 mmto 160mm; 4Ommto 140mm; 60mmto 120mm; 80mmto 120mm; or90mm to 110 mm. However, it is also envisaged that larger diameter substrate wafers may be used, for example, having a diameter of 20mm to 320 mm, 20mm to 260 mm, or mmto 210 mm.

The handling wafer will generally be formed of a material which has a thermal expansion coefficient larger than the material of the etch stop layer and similar or the same as the thin layer of single crystal material adhered to the CYD diamond. Such a handling wafer may be formed of silicon, silicon carbide, or a nitride. The material of the handling wafer may have a different crystallographic orientation to the material of the first layer. For example, in one arrangement the handling wafer may be formed of [100) oriented silicon. This material is less expensive that the 111} oriented silicon material which is preferred for the thin layer of single crystal material adhered to the CVD diamond. The material of the handling wafer may also have a lower electrical resistivity than preferred materials used to fabricate the thin layer of single crystal material adhered to the CVD diamond, the preference for high electrical resistivity not being required for the handling wafer as it does not form part of the final device structure.

The abovc described substrate wafer structures arc suitable for growing polycrystalline diamond to sufficient thickness for thermal substrate applications. For example, polycrystalline diamond grown to a thickness in the range: 25 jim to 150 jim jim to 130 jim; 70 jim to 130 jim; 80 jim to 120 jim, or 90 jim to 110 jim.

However, as the thickness of the polycrystalline diamond material is increased, thermal expansion coefficient mismatches can lead to the increased risk of cracking within the first layer of single crystal material of the substrate wafer during processing. As such, in one arrangement it can be advantageous to first grow a thin layer of CYD diamond material, process the substrate wafer to achieve a thin layer of single crystal material, and then proceed with a thrther CVD diamond growth step to increase the thickness of the CVD diamond material by growing a second layer of CVD diamond material over the First layer of CVD diamond material. The second layer of polycrystalline diamond layer may be grown to a thickness equal to or greater than: 25 jim; 50 jim; 75 m; 100 jim; 200 jim; 300 m; or 400 jim and optionally equal to or less than: 1mm; 750 jim; 500 jim 400 jim; or 300 jim. The two layers of CVD diamond material may be distinguishable in the final substrate structure. For example, an interface between the two layers may be discernible by the presence of a layer of defects indicating that CVD growth has been performed in two steps.

Furthermore, the two layers of CYD diamond material may be grown under different synthesis conditions and thus have different characteristics such as different thermal conductivities. In such circumstances, it may be advantageous for the first layer of CVD diamond material to have a higher thermal conductivity than the second layer of OlD diamond material as the first layer will be located closest to active compound semiconductor components of the end device. For example, the first layer of diamond material may have a thermal conductivity equal to or greater than 600 Wm'K1, 800 Wm1IC1, 1000 Wni'1C1, 1200 Wm1K', or 1400 Wnt'K1. Such high quality polycrystalline diamond material can be fabricated using a microwave plasma method as opposed to a hot filament method. Accordingly, it may be advantageous to fabricate one or both layers of polycrystalline diamond material by a microwave plasma method.

Using the above described methodology it is possible to fabricate a composite substrate comprising a layer of polycrystalline OlD diamond material with a thin, high quality, relatively crack free, layer of single crystal material directly bonded thereto which is suitable for epitaxial growth of a highly quality compound semiconductor. For example, the layer of single crystal material may be substantially crack free over at least a central region thereof, wherein the central region is at least 50%, 60% 70%, 80%, 90%, or 95% of a total area of layer of single crystal material, and wherein the central region has no cracks which extend greater than 2 mm in length.

A better performance semiconductor device can be fabricated using such a composite substrate due to the improved nature of the growth surface while at the same time providing good thermal contact between the active device layers and the polycrystalline CVD diamond by locating the two very close together. An example of a portion of such a device structure is illustrated in Figure 7 which illustrates a layer structure comprising a polycrystalline CVD diamond substrate D, a thin layer of single crystal silicon Si, and a layer of compound semiconductor material SC, such as a nitride compound semiconductor comprising alloys of gallium and/or aluminium and/or indium with nitrogen, epitaxially grown over the thin layer of single crystal silicon.

The layer of single crystal compound semiconductor may have a charge mobility no less than 1000 cm2V's', 1200 cm2V's4, 1400 cm2V's1, 1600 cm2V'c', 1800 cm2V or 2000 cm2V's'. While such charge mobilitics of compound semiconductor layers have previously been achieved on non-diamond substrates and may be achieved on diamond substrates when the semiconductor layer is not in good thermal contact with the diamond substrate layer, the combination of a relatively thick, high thermal conductivity diamond layer in combination with a high quality, low strain compound semiconductor layer, with both layers disposed in very close proximity to provide good thermal contact has proved difficult to date for the reasons explained in

this specification.

While this invention has been particularly shown and described with reference to preferred embodiments, it will be understood to those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as defined by the appendant claims.

The work leading to this invention has received fbnding from the [European Community's] [European Atomic Energy Community's] Seventh Framework Programme ([FP7/2007-2013] [FP7!2007-2011j) under grant agreement n° [214610].

Claims

<claim-text>Claims 1. A method of nmnufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising at least a layer of single crystal material suitable for cpitaxial growth of a compound semiconductor thcreon; growing a first polycrystalline diamond layer on the substrate wafer using a chemical vapour dcposition technique to form a composite comprising thc substrate wafer bonded to the polycrystalline diamond layer via said layer; and removing a portion of the substrate wafer material using an etching technique to form a composite substrate comprising the polycrystallinc diamond layer directly bonded to said laycr of substrate wafer material, wherein said layer of substrate material has a thickness of no more than 100 urn, wherein the etching technique is configured to preferenlially remove the portion of substrate material relative to said layer of substrate wafer material bonded to the polycrystalline diamond layer, said etching technique comprising one or more of: selecting an anisotropic ctchant which etches the portion of substrate material at a faster rate than said layer of substrate wafer material bonded to the polycrystalline diamond layer; providing an edge etch stop around edge regions of said layer of substrate wafer material bonded to the polycrystalline diamond layer; and providing a doped, electrically conductive portion of the substrate to be removed and an electrically resistive layer bonded to the polycrystalline diamond layer and removing the doped, electrically conductive portion of the substrate by electrochemical etching or electrochemically assisted etching.</claim-text> <claim-text>2. A method according to claim 1, wherein the substrate wafer comprises a handling wafer, an etch stop layer, and a layer of single crystal material adjacent the polycrystalline CVD diamond layer.</claim-text> <claim-text>3. A method according to claim 2, wherein the handling wafer is formed of a different material to the layer of single crystal material adjacent the polycrystalline DID diamond layer or otherwise formed of the same material but which presents different crystallographically orientated surfaces to the anisotropic etchant and the anisotropie etchant is selected to etch the handling wafer at a faster rate than the layer of single crystal material adjacent the polycrystal line CVD diamond layer due to the aforementioned difference in material or crystallographic orientation.</claim-text> <claim-text>4. A method according to any one of claims 2 or 3, wherein the handling wafer has a thickness in a range: 0.3 mm to
2.0 mm; 0.3 mm to 1.8 mm; 0.3 mm to 1.5 mm; 0.3 mm to 1.3 mm; 0.3 mm to 1.0 mm; or 0.5mm to 0.8 mm.</claim-text> <claim-text>5. A method according to any one of claims 2 to 4, wherein the material of the handling wafer has a thermal expansion coefficient larger than the material of the etch stop layer.</claim-text> <claim-text>6. A method according to any one of claims 2 to 5, wherein the material of the handling wafer has an electrical resistivity lower than the material of the layer of single crystal material adjacent the polyctystalline CYD diamond layer.</claim-text> <claim-text>7. A method according to any one of claims 2 to 6, wherein the material of the handling wafer has a different crystallographic orientation to the material of the layer of single crystal material adjacent the polycrystalline C'VD diamond layer.</claim-text> <claim-text>8. A method according to any one of claims 2 to 7, wherein the handling wafer is formed of silicon, silicon carbide, or a nitride.</claim-text> <claim-text>9. A method according to any one of claims 2 to 8, wherein the handling wafer is formed of silicon having (100 oriented major faces.</claim-text> <claim-text>10. A method according to any one of claims 2 to 9 wherein the etch stop layer has a thickness of: 0.5 um or more; 0.75 jim or more; 1.0 jim or more; 2 mor more; or 4 um or more.</claim-text> <claim-text>11. A method according to any one of claims 2 to 10. wherein the etch stop layer has a thickness of: 10 jim or less; or 5 jim or less.</claim-text> <claim-text>12. A method according to any one of claims 2 to 11, wherein the etch stop layer is formed of a material having a lower thermal expansion coefficient and/or a higher fracture strength than the layer of single crystal material adjacent the polycrystalline CVD diamond layer.</claim-text> <claim-text>13. A method according to any one of claims 2 to 12, wherein the material of the etch stop layer has a lower thermal expansion coefficient than the polycrystalline CYD diamond.</claim-text> <claim-text>14. A method according to any one of claims 2 to 13, wherein the etch stop layer of material is formed of an amorphous material.</claim-text> <claim-text>15. A method according to any one of claims 2 to 14, wherein the etch stop layer of material is formed of Si02.</claim-text> <claim-text>16. A method according to any preceding claim, wherein the layer of single crystal material bondcd to the polycrystalline diamond material after etching has a thickness of: 75 um or less; 50 um or less; 30 jim or less; 20 jim or less; 10 m or less; 5 jim or less; 3 jim or less; 2 jim or less; or I jim or less.</claim-text> <claim-text>17. A method according to any preceding claim, wherein the layer of single crystal material bonded to the polycrystalline diamond material after etching has a thickness of: 10 nm or more; or 20 nm or more.</claim-text> <claim-text>18. A method according to any preceding claim, wherein the layer of single crystal material adjacent the polycrystalline CYD diamond layer is formed of {111} oriented silicon.</claim-text> <claim-text>19. A method according to any preceding claim, wherein the anisotropic etchailt is KOH solution.</claim-text> <claim-text>20. A method according to ally preceding claim, wherein the edge etch stop is formed by overgrowing the CVD diamond material around sides of the substrate wafer such that edge grown CYD diamond material masks the edges of the layer of single crystal material adjacent the polycrystalline CYD diamond layer and functions as an etch stop during subsequent processing of the substrate wafer.</claim-text> <claim-text>21. A method according to any preceding claim, wherein the substrate wafer has a diameter in a range: 20 mm to 320 mm; 20 mm to 260 mm; 20 mm to 210 mm; 20 mmtol60mm;4Ommtol4Omm;60mmtol20mm;80mmtol2Omm;or90mm to 110mm.</claim-text> <claim-text>22. A method according to any preceding claim, wherein the first layer of polycrystalline diamond layer is grown to a thickness in the range: 25 jim to 150 jim jim to 130 jim; 70 p.mto 130 jim; 80 jimto 120 am, or 90 jim to 110 jim.</claim-text> <claim-text>23. A method according to any preceding claim, wherein after removing the portion of substrate wafer material a second layer of polycrystalline diamond is grown over the first layer of polyerystalline diamond material.</claim-text> <claim-text>24. A method according to claim 23, wherein the second layer of polycrystalline diamond layer is grown to a thickness equal to or greater than: 25 jim; 50 am; 75 jim; jim; 200 am; 300 am; or 400 am.</claim-text> <claim-text>25. A method according to claim 23 or 24, wherein the second layer of polycrystalline diamond layer is grown to a thickness equal to or less than: 1mm; 750 jim; 500 jim; 400 jim; or 300 jim.</claim-text> <claim-text>26. A method according to any preceding claim, wherein the first layer of diamond material has a thermal conductivity equal to or greater than 600 WnI1K', 800 Wm1K1, 1000 Wm1K1, 1200 WnI1KT1, or 1400 Wm1K1.</claim-text> <claim-text>27. A method according to any preceding claim, wherein the first layer of diamond material, and if present the second layer ofpolycrystalline diamond material, is fabricated by a microwave plasma method.</claim-text>