GB2497144A - Feed-forward equalisation (FFE) for a serialiser/deserialiser (SERDES) receiver - Google Patents

Abstract

A serialiser/deserialiser (SERDES) receiver 11 comprises a feed forward equaliser (FFE) 4 and a decision feedback equaliser (DFE) 5 acting as a data slicer. The FFE makes an estimate of a future sample by slicing the future sample with respect to a predetermined slicing level and corrects a current sample for the effect of the future sample before it is sliced by the DFE. The FFE subtracts at least one quantising level from the current sample if the future bit is rendered as a 1 or adds at least one quantising level if the future bit is rendered as a 0. The receiver is arranged such that the subtraction and addition are performed only if the bit values of the current and future samples as rendered by the FFE are different. The invention prevents the FFE from applying a correction that is adverse to noise margin and bit error rate by moving the current sample value closer to the data slicing level of the data slicer.

Description

Improvements in or relating to Feed Forward Equalisation The present invention relates to Feed Forward Equalisation (FEE) and in particular provides an equaliser with enhanced signal to noise ratio for use for example in a highly quantized sampled data recovery system such as a serialiser/deserialiser (SERDES) based transmission scheme.

Highly quantized sampled systems are pr-one to noise amplification due to their low resolution. Noise amplification by a digital FEE may be a limiting factor in data recovery when the noise is amplified and applied such that the signal moves towards the slicing point: the amplified noise is subtracted directly from slicer margin, impacting bit error rate(EER).

This inventton seek to provide a solution which Implements a highly quantized feed forward equaliser (FEE) which has significantly higher noise immunity and signal carrier properties.

The purpose of a feed forward equalizer is to remove the effect of the future data sample from the current data sample. Ordinarily a quantized feed forward equaliser (FEE) will apply a correction to the data sample when the future sample is above or below either of two thresholds. The gap between these two thresholds defines the noise immunity of the circuit.

Known prior art relies upon the native resolution of thc sampled system to define the noise floor of the feed forward equaliser. This invention seeks to improve upon this limitation.

The present invention provides apparatus and method as set forth in the claims.

A key challenge facing designers of high-bandwidth systems such as data-routers and super-computers Is the requirement to transfer large amounts of data between ICs -either on the same circuit board or between boards. This data transmission application is called Serialisation-Deserialisation or "SerDes" for short. The present invention is useful in SerDes circuit and indeed was developed for that application. Nonetheless the invention may be used in other applications.

Analysis of typical backplane channel attenuation (which is around - 24dB) and package losses (-1 to -2dB) in the presence of crosstalk predict that an un-equalized transceiver provides inadequate porformance and that docision feedback oqualizaticn (DEE) is noeded to achieve error rates of less than lO1.

Traditional decision-feedback equalization (DEE) methods for SerDes receivers rely on either modifying, in analogue, the input signal based on the data history ["A 6.25Gb/s Binary Adaptive DEE with First Post-Cursor tap Cancellation for Serial backplane Communications" R Payne et al 185CC 2005; "A 6.4Gb/s CMOS Serces Core with feed-forward and Decision Feedback Equalization" M. Scrna et al 155CC 2005; "A 4.6- 6.4Gb/s serial link for Backplane Applications Using Decision Feedback Equalization" Eaten at ci IEEE JSSC Nov 2005.] or on having an adaptive analogue slicing level ["Techniques for High-Speed implementation of Non-linear cancellation" S.Kasturia IEEE Journal on selected areas in Conrsunioations. june 1991.] (i.e. the signal level at which the circuit decides whether the signal represents a 1 or a 0) A blook diagram of a SerDes receiver circuit 1, which forms part of an integrated circuit, in wllch the present invention may be used is shown in Figure 1. The invention may nonetheless be used in other applications.

In the receiver circuit 1 of Figure 1 the input data is sampled at the baud-rate, digitized and the equalization and clock & data recovery (CDR) performed using numerical digital processing techniques. This approach results in the superior power/area scaling with process of digital circuitry compared to that of analogue, simplifies production testing, allows straightforward integration of a feed-forward equalizer and provides a flexible design with a configurable number of filter taps in the decision feedback equaliser. The circuit has been implemented in 65nm CMOS, operating at a rate of 12.5Gb/s.

The receiver circuit 1 comprises two baud-rate sampling ADOs (analogue to digital converters) 2 and 3, a digital 2-tap FEE (feed forward equsliser) 4 and digital 5-tap DFE (decision feedback equaliser) 5 to correct channel impairments.

The SerDes section of the integrated circuit, which includes the receiver circuit 1 is also provided with a transmitter 40 (Figure 4) connectcd to trannm±t data ovor a parallel channol to that which thc receiver circuit 1 is connected to receive data. The transmitter 40 comprises a 4-tap FIR filler to pre-compensate for channel impairments.

In many applications the integrated circuit transmitting data to the receiver circuit 1 uses pre-ccmpensation and in particular a similar transmitter circuit 40, but in other applications the receiver orcuit 1 works ithout pre-compensation being used at the other end The reoelver 1 of Figure 1 is now described in more detail. The received data is digitized at the baud-rate, typically 1.0 to 12.5 Gb/s, using a pair of interleaved track and hold stages (T/H) 6 and 7 and a respective pair of 23 level (4.5 bit) full-flash ADCs 2 and 3 (i.e. they sample and convert alternate bits of the received analogue data waveform) . The two track & hold circuits enable interleaving of the half-rate ADOs and reduce signal related aperture timing errors. The two ADCs, each running at 6.25 Gb/s for 12.5 Gb/s incoming data rate provide baud-rate quantization of the received data. The ADO's dynamic range is normalized to the full input amplitude using a 7-bit automatic gain control (AGO) circuit 8. A loss of signal indication is provided by loss of signal unit 9 that detoots whon the gain control signal provided by the AGO is out-of-range. An optional attenuator is included in the termination block 10, which receives the signals from the transmission channel, to enable reception of large signals whilst minimizing signal overload.

The digital samples output from the ADOs 2 and 3 are interleaved and the resulting stream of samples is fed into a custom digital signal processing (DSP) data-path that performs the numerical feed-forward equalization and decision-feedback equalization. This is shown in Figure 2. This comprises a 1 UI delay register 12 connected to receive the stream of samples from the AECs 2 and 3. (1 UI is a period of the clock, i.e. the delay between bits.) A tap 13 also feeds the samples from the ADCs to a multiplier 14, each sample being received by the delay latch 12 and the multiplier 14 at the same time. The multnplier 14 multiplies each sample by a constant weight value (held in a programmable register 15), which value is typically 10%.. The outputs of the multiplier 14 and the delay register 12 are added together by an adder 16 to provide the output of the FEE 4.

An advantage of applying the equalization digitally is that it is straightforward to include feed-forward equalization as a delay-and-add function without any noise-sensitive analogue delay elements. The FF5 tap weight is selected before use to compensate for precursor 151 and can be bypassed to reduce latency. Whilst many standards require pre-cursor dc-emphasis at the transmitter, inclusion at the receiver allows improved bit error rate (BEE) performance with existing legacy transmitters.

The DFE 5 uses an unrolled non-linear cancellation method ["Techniques for High-Speed implementation of Non-linear cancellation1' S.Kasturia IEEE Journal on selected areas in Communications. June 1991]. The data outpur (i.e. the ls and Os originally transmitted) is the result of a magninude comparison between the output of the FEE 4 and a slicer-level dynamically selected from a set stored in a set 17 of pre-programmed registers. The values are determined by a control circuit (not shown in Figure 1) from the waveforms of test patterns sent during a setup phase of operation. The magnitude comparison is performed by a magnitude comparator 18 connected no rocoivo the output of tho FEE 4 and tho selected slicer-level; it outputs a 1 if the former is higher than the latter and a 0 if it is lower or equal, thereby forming the output of the DFE 5.

The slicer-level is selected from one of 2n possible options depending on the previous n bits of data history. The history of the bits produced by the magnitude comparator 18 is recorded by a shift register 19 which is connected to shift them in. The parallel output of the shift register is connected to the select input of a multiplexer 20 whose data inputs are connected to the outputs of respective ones of the set 17 of registers holding the possible slicer-levels.

Unrolled tap adaption is performed using a least mean square (INS) method where the optimum slicing level is defined to be the average of the two possible symbol amplitudes (11-1) when proceeded by identical history bits. (For symmetry the symbols on the channel for the bit values 1 and 0 are given the values +1 and -1) Although 5-taps of DFE were chosen for this implementation, this parameter is easily scaleable and performance can be traded-off against power consumption and die area. In addition, the digital equalizer is testable using standard ATEG (automatic test pattern generation) and circular built-in-self-test approaches.

The exemplary prior art FEE is shown in Fig.2. The FEE serves to make an estimate of the future data bit value based up a selected slicing level, such as by assessing the srgn of the raw ado sample; a positive sample is assumed to be a 1 and a negative sample a 0.

Figure 3 shows an example of the operation of the prior art FEE solution in the presence of no noise. The incoming signal is quantized by a 13 level ADO with levels at -6 to +6 to produce ADO sample values ranging from -6.5 to +6.5 as shown in the diagram. At the current sampling instant (denoted by tc) the current data sample is at -0.5 with the future data sample (at the future sampling instant denoted by tf) at +0.5. In this case the FEE has a single slicing level threshold presently set at zero. The FEE threshold is configurable to span all the available sample values. The lower the FFE threshold, the more often the FEE circuits will be in operation to correct sample values prior to application to the DEE. The FEE threshold may be set in response to channel conditions and data rate requirements. As the future data sample is above this threshold, the FEE will act to remove the effect of this future sample (which is positive) by subtracting a +1 from the current data sample. Thia results in the poat-FFE sample (at time tc) being -1.5, as shown in the diagram. The decision feedback equalizer will adapt the slicing level to be nominally 4.5 LESs away from the average post-FEE samples, at +3 in this example (as shown) The slicing level that is applied by the DEE is also shown in Figure 3.

Thus it will be seen that the samples are read correctly and with a good noise margin giving a robust system.

Figure 4 shows an example of the operation of the prior art FEE solution when there is noise present in the system. As before, at the current sampling instant (denoted by tJ the current data sample is at - 0.5. Most of the time the future data sample (for this example) would be at +0.5, resulting in the same behaviour as explained previously, with thc post-FFE sample (at time t!4 being corrected to -1.5, with the slicing level being set at +3.

However, in the presence of noise, occasionally the future sample will be seen as a -0.5 (as shown). When this happens the FEE will correct the current data sample to remove the effect of the future data sample (which is now negative as it is below the slicing threshold) . The FEE will think the future data bit is a 0 (when it is in fact a 1) . This will result in the FEE correcting the current data sample by adding a +1 to the ADO data sample. This results in a post-FEE sample of +3.5 (instead of -1.5 previously) . The post-FEE sample has now moved nearer to the slicing level (at +3) instead of away from it as before. As it is the post-FEE sample that will be sliced by the data sampler, this has a direct impact on margin and bit error rate (the margin without noise is nominally 4.5 LEEs, the margin with noise is reduced to 2.5 LEEs) Again, the slicing level that applied by the EFE is also shown in Figure 4. It will be apparent that in this exampls the noisy sample will in the end be read correctly thanks to the corrective action of the slicing level set by the DEE. However the noise margin is reduced by the action of the FEE which has the consequence that if channel noise is increased still further, data reception will fail (BEE becomes unacceptably high) sooner than would have been the case if the usually beneficial FEE had not been present.

The enhanced FEE of this solution applies its signal correction only when there is a sign change between the present and future samples; this prevents noise converting a crossing of one threshold into a crossing of the other. Effectively this doubles the noise imnunity because with the traditional implementation noise could convert a positive correction into a negative correction, whereas the worst case impacu due to noise with the enhanced solution is to prevent a correction occurring.

This invention also ensures that any correction made to the present sample is always in the direction away from the data slicer, increasing margin and decreasing bit error rate (BEE) Figure 5 shows a block diagram of the FEE implementation of an embodiment of the preaent invention.

Figure 6 shows an example of the operation of the enhanced FEE solution when there is noise present in the system.As before, at the current sampling instant (denoted by ti the current data sample is at -0.5. As in Figure 3, most of the time the future data sample (for this example) would be at ±0.5, as the current and future data ssmples are of opposite sign, the post-FEE sample (at time t) will be corrected to (- 1.5), with the slicing level adapting to a value of +3.

However, now in the presence of noise, when the future sample becomes (-0.5) (as shown), as the current and future samples are of the same sign no correction will be made on the current data sample, so the post-FEE sample for the current data sample will be -0.5. This results in a nominal margin of 3.5 lEEs, whereas the prior art FEE solution (as deocribcd in Figure 3) would hevc rcculted in a margin of 2.5 LSBo.

The prior art FEE would have resulted in a correction that would have reduced noise immunity, the present invention suppresses this correction unless there is a sign change between the present and future samples. Hence the deleterious effect of the correction on noise margin and bit error rate are avoided.

This invention improves signal to noise ratio without requiring an increase in resolution in the sampled system. Such an increase in resolution would be expensive in terms of silicon area, power dissipation and complexity.

This invention moreover has a very low implementation overhead. From circuit perspective, less than 30 standard cell gates are needed to realise this solution in a pipelined architecture.

Claims (1)

1. <claim-text>CLAIMS1. A receiver for serialised data comprising a feed forward equaliser and a decision feed back equaliser acting as a data slicer at a first predetermined Level wherein the EFE makes an estimate of a future sample to be rendered as a bit value by slicing the future sample with respect tc a second predecermined slicing Level; corrects a current sample for the effect of the future sample before the sample is sliced by the DEE by subtraction of at Least one quantising Level from the current sample if the future bit is rendered by the FFE as a 1; or addition of at Least cne quantising Level tc the current sample if the future bit is rendered by the FEE as a 0; the receiver being characterised in that: said subtraction and addition are performed if the bit value of the current and future sampLes as rendered by the FEE are different; and said subtraction and addition are not performed if the bit value of the current and future samples as rendered by the FFE are the same.</claim-text>