KR101770554B1 - Automatic gain controllable decision feedback equalizer - Google Patents

Abstract

Discloses an automatic gain adjustable decision feedback equalizer. The present invention includes an input amplifier for amplifying a received signal successively transmitted through a channel in response to a gain control signal and outputting an amplified received signal, a subtractor for subtracting at least one feedback ISI signal obtained from a previously received signal in the amplified received signal, An ISI subtracting section for compensating a channel loss of a received signal to output an equalized signal, a data determining section for determining a signal level of the equalized signal and outputting a determination signal indicating a digital value of the received signal, A delay feedback unit for generating at least one feedback ISI signal by amplifying in response to at least one subtraction control value, an error determination unit for obtaining a sign value obtained as a difference between the equalization signal and the determination signal, And using the sign value of the error signal, the gain control signal, and the sign value of at least one difference control value Includes after applying the adaptive gain control for adjusting the gain control signal, and subtracting the control value of at least one received signal for that portion.

Description

[0001] AUTOMATIC GAIN CONTROLLABLE DECISION FEEDBACK EQUALIZER [

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decision feedback equalizer, and more particularly to a decision feedback equalizer provided in an electronic device for inputting and outputting a digital signal at high speed and capable of automatic gain control in an orthogonal mixing manner.

Wired channels, which are implemented on a printed circuit board (PCB) and transmit signals between electronic devices (for example, IC chips) that perform communication, are basically channel loss (low-pass filter: LPF). Therefore, when a digital signal is transmitted at high speed through a wired channel, even if an ideal digital signal of a pulse type is applied, signal distortion occurs while being transmitted through a wired channel.

1 is a diagram for explaining distortion of a digital signal according to the length of a wired channel.

1 (a) and 1 (b) show a case where a digital signal of an ideal pulse shape is transmitted through a wired channel connected between two IC chips Chip1 and Chip2, respectively, and a digital signal is distorted according to the length of a wired channel Fig. 1 (a) shows a case where the length of the wire channel is short, and (b) shows a case where the length of the wire channel is long. 1 (a) and 1 (b), when the length of the wire channel becomes long, the digital signal distorted while passing through the wire channel is transmitted to a chip (here assumed to be Chip 2, for example) The intensity of the cursor signal h ₀ , which is the signal at the sampling timing for reading the value of the present digital signal, is reduced. The cursor signal h0 directly affects the bit error rate (BER) and is an important factor for determining the communication performance for a digital signal transmitted at a high speed.

The intensity of the (or less ISI Inter Symbol Interfernece) signal (h _1, h ₂₎ On the other hand, the distorted digital signal, and then the sampling period (T _b) remain, after applying digital read inter-symbol interference affecting the signal to . Thus, ISI signal (h _1, h ₂₎ has to be removed because there is a problem that prevents the chip (Chip2) for receiving a digital signal is read the value of the digital signal properly.

A Decision Feedback Equalizer (DFE) has been proposed to increase the strength of the cursor signal h ₀ and to eliminate the ISI signals h ₁ , h ₂ . A DFE is provided in an electronic device that inputs and outputs a digital signal at high speed and is used to reconstruct a distorted digital signal during transmission through a channel. DFE is subtracted before the basis of the result of the received digital signal ISI signal (h _1, h ₂₎ to determine, the ISI signal is determined in the digital signal it is now applied, and (h _1, h _2), which are applied It removes the ISI signal (h _1, h ₂₎ generated by a previous digital signal at a digital signal.

At this time, it is very important that the DFE subtracts the intensity of the ISI signals (h ₁ , h ₂ ) to be subtracted by appropriately adjusting the intensity. However, since most of the electronic devices including the IC chip are manufactured without knowing the length of the wire channel in advance, the magnitude of the channel loss can not be predicted in advance. In addition, channel loss occurs not only by the channel length but also by the signal transmission rate, the kind of material constituting the channel, and the surrounding environment, and it is very difficult to predict the accurate channel loss in advance. Therefore, the strength of the ISI signals (h ₁ , h ₂ ) to be adjusted can not be accurately determined.

Accordingly, a request for a DFE that can adaptively increase the strength of the cursor signal h ₀ and remove the ISI signals h ₁ and h ₂ irrespective of changes in the factors causing channel loss such as the length of the wire channel, Is continuing.

Korean Patent Laid-Open No. 10-2015-0137020 (Published Dec. 20, 2015)

It is an object of the present invention to provide an automatic gain control method and apparatus capable of increasing the intensity of a cursor signal adaptively according to a change in a factor causing a channel loss such as a change in channel length, And to provide a decision feedback equalizer.

According to an aspect of the present invention, there is provided a decision feedback equalizer comprising: an input amplifier for amplifying a received signal continuously transmitted through a channel in response to a gain control signal to output an amplified received signal; An ISI subtracter for subtracting at least one feedback ISI signal obtained from a previously received signal in the amplified received signal to output an equalized signal by compensating for a channel loss of the received signal; A data determining unit for determining a signal level of the equalized signal and outputting a determination signal indicating a digital value of the received signal; A delay feedback unit for receiving and delaying the determination signal and amplifying the delayed control signal in response to at least one subtraction control value to generate the at least one feedback ISI signal; An error discriminator for obtaining a sign value obtained by a difference between the equalization signal and the decision signal as a sign value of an error signal; And an adaptive control unit for adjusting the gain control signal and the at least one subtraction control value for a subsequently received received signal using a sign value of the error signal and a sign value of the gain control signal and the at least one difference control value, A gain control section; .

Wherein the error discrimination unit compares the equalization signal with a predetermined discrimination reference value and outputs a positive discrimination value and a negative discrimination value for the equalization signal; And an error determination unit which receives the negative discrimination value, the negative discrimination value, and the inverted determination signal inverted by the determination signal, and discriminates the sign value of the error signal; And a control unit.

The signal converter receives the equalization signal, which is a CML (Current Mode Logic) signal, and compares the level of the equalization signal with a first discrimination reference value corresponding to a sum of a predetermined reference voltage and a reference voltage, A first signal discriminator for outputting a discrimination value of the first signal discriminator; And a second signal discrimination unit which receives the equalization signal and compares the level of the equalization signal with a second discrimination reference value corresponding to a difference between the reference voltage and the reference voltage to output the discrimination value as the CMOS logic signal, group; And a control unit.

Wherein the error determination unit receives the positive discrimination value and the negative discrimination value, and performs a logical multiplication of the positive discrimination value and the negative discrimination value, and outputs the logical sum; A second AND gate element for receiving the inverted decision signal and the negative discrimination value, logically multiplying and outputting the inverted decision signal; And an OR gate element for outputting the sign of the error signal by performing an OR operation on outputs of the first and second AND gates; And a control unit.

Wherein the data determination unit is implemented as a slicer that receives the equalization signal, compares the level of the equalization signal with the reference voltage, and outputs the determination signal and the inversion determination signal, which are the CMOS logic signals, do.

Wherein the adaptive gain control unit is implemented as a digital circuit and outputs a code value of the error signal as the CMOS logic signal and a sign value of the gain control signal and the at least one difference control value as a least mean square mean square (LMS) technique to obtain the gain control signal and the at least one difference control value for compensating for channel loss caused by the channel.

And the input amplifier varies the amplification degree in response to the gain control signal to amplify the received signal to a magnitude corresponding to the reference voltage.

Wherein the delay feedback unit sequentially receives the determination signal and sequentially delays the received signal in units of one tap corresponding to a sampling period, amplifies at least one of the sequentially determined determination signals to a size corresponding to the at least one subtraction control value, And transmits one feedback ISI signal to the ISI subtracter.

The delay feedback unit includes a first tap feedback unit for delaying the determination signal by one tap, amplifying the delayed determination signal by a first difference control value, and outputting the resultant signal; A second tap feedback unit for again delaying the delayed decision signal by one tap, amplifying the two-tap delayed decision signal by the second difference control value, and outputting the amplified decision signal; And a control unit.

Wherein the adaptive gain controller adjusts the gain control signal and the first and second subtracted control values so as to facilitate the implementation of the minimum mean square (LMS)

(Where sign is a sign function and mu is an update rate adjustment value).

Therefore, the automatic gain controllable feedback feedback equalizer of the present invention is provided in various electronic devices including an IC chip for inputting and outputting data at a high speed, and adaptively gains a change in a factor affecting a channel loss such as a channel length It can automatically adjust the intensity of the cursor signal and remove the ISI signal. In particular, by modifying the minimum mean square method using the sign of the adaptive variable and the sign of the error signal, the hardware configuration for obtaining the update value of the adaptive variable can be easily implemented in a digital circuit, It is possible to obtain an adaptive variable capable of minimizing the error signal efficiently at a very high speed.

Therefore, the reception sensitivity and the bit error rate of the electronic device can be greatly improved, and the yield in manufacturing electronic devices can be greatly increased. In addition, even when a change in channel loss such as a design change of a system including an electronic device occurs, the gain can be adjusted adaptively so that it can be used without complicated operations such as channel loss measurement and circuit correction.

1 is a diagram for explaining distortion of a digital signal according to the length of a wired channel.
2 illustrates a configuration of an automatic gain controllable decision feedback equalizer according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining the equalization operation of the decision feedback equalizer of FIG. 2; FIG.
FIG. 4 is a diagram simulating a result of repeatedly updating an adaptive variable based on an error signal according to a least mean square (LMS) technique.
5 shows an example of an error determining unit for obtaining an error signal for obtaining an adaptive variable in the decision feedback equalizer of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

2 illustrates a configuration of an automatic gain controllable decision feedback equalizer according to an embodiment of the present invention.

2, a decision feedback equalizer (DFE) according to the present invention includes an input amplifier 110, an ISI subtractor 120, a data decision slicer 130, a delay feedback unit 140 An error determination unit 150, and an adaptive gain control unit 160. [

The input amplifier 110 receives the reception signal r [k] continuously transmitted through the wire channel and receives the reception signal r [k] according to the gain control value A [k] set by the adaptive gain controller 160 r [k]) and outputs the amplified reception signal A [k] r [k]. Here, the received signal r [k] is a signal distorted by the channel loss while the digital signal is transmitted through the wired channel, and the transmitted signal x [k] and the pulse response of the channel (h ₀ ) and ISI signals (h ₁ , h ₂ )).

It is assumed that the signal x [k] transmitted in the present invention is a non-return-to-zero (NRZ) signal and the received signal is a signal including the ISI of the previously received signal due to channel loss And is received in the form of an analog signal. Although the received signal r [k] is shown as being applied through a channel of a single line for convenience of explanation in FIG. 2, the received signal r [k] And may be applied with differential signals. When the received signal r [k] is applied as a differential signal through a channel of a double line, two DEFs of FIG. 2 are provided to compensate for the distortion of each differential received signal r [k] .

In the present invention, the symbol k added to each signal means a k-th time sample, which is a discrete time value indicating the sequence of each signal, and is an integer of 0 or more.

The input amplifier 110 amplifies the intensity of the received signal r [k] based on the predetermined reference voltage B in accordance with the gain control value A [k]. That is, the intensity of the cursor signal h ₀ and the ISI signals h ₁ and h ₂ .

The ISI subtracting unit 120 is implemented as a mixer and receives the amplified received signal A [k] r [k] amplified by the input amplifier 110 and the previous received signal r [k] -]) and receives the feedback ISI signals C ₁ [k] x '[k-1] and C ₂ [k] x' [k-2], which are intensity-controlled ISI signal components, (K) is calculated by subtracting the feedback ISI signals C ₁ [k] x '[k-1], C ₂ [k] And outputs a signal z [k]. As described above, since the ISI signals h ₁ and h ₂ affect the signals to be subsequently applied, the ISI signals h (k) of the previously received signals r [k-1] and r [k- _{h 1 [k-1],} h 2 [k-1]), (h 1 [k-2], h 2 [k-2])) is included in the current applied to the received signal (r [k]) which is . However, in the present invention, the ISI subtracter 120 subtracts the feedback ISI signals C ₁ [k] x '[k-1] and C ₂ [k] x' [k] from the amplified received signal A [ k-2] by subtracting a), amplifying the received signal (a [k] r [k ]) the ISI signal _{((h 1 [k-1} ], h 2 [k-1] comprising a), (h ₁ [ k-2] and h ₂ [k-2]).

Here, the feedback ISI signals C ₁ [k] x '[k-1], C ₂ [k] (H ₁ [k-1], h ₂ [k-1]), h ₁ [k-2] and h ₂ [k-2] corresponding adaptively ISI signal by _{((h 1 [k-1} ], h 2 [k-1]), (h 1 [k-2], h 2 [k-2])) the signal is to be adjusted in In addition, the signal amplification of the input amplifier 110 must be considered together.

In the present invention, assuming that affect to the reception signal (r [k]) ISI signal _{((h 1 [k],} h 2 [k]) are two sampling timing after (k + 1, k + 2 ) of the will be described, that two tabs (tab) the received signal is applied to the previous (r [k-1], r [k-2]) ISI signal _{((h 1 [k-1} ] of a, h ₂ [k-1] _{), (h 1 [k-} 2], h 2 [k-2])) it is assumed that affects a received signal (r [k]) which is currently in. Therefore, the received signal is received within the previous two tabs ( configured to subtract the r [k-1], r feedback ISI signal (C ₁ [k] to [k-2]) x ' [k-1], C 2 [k] x' [k-2]) is However, the number of feedback ISI signal to be subtracted, i.e., the received signal (r [k]) ISI signal _{((h 1 [k-1} ] that _{affect, h 2 [k-1]} ), (h 1 [k -2], and h ₂ [k-2]) can be set by adjusting the number of taps.

The data determination unit 130 receives the equalized signal z [k] equalized in the ISI subtraction unit 120 and the clock signal CLK specifying the sampling timing and outputs the equalized signal z [k] The transmission signal x [k] corresponding to the reception signal r [k] is sampled by sampling the equalization signal z [k] at the sampling timing of the sampling period T _b and confirming the level of the sampled signal. And outputs a determination signal x '[k]. Here, the determination signal x '[k] is a digital signal that is output as a -1 or 1 value corresponding to the received signal r [k].

Clock signal (CLK) is a signal which is set in synchronization with the timing of the cursor signal (h ₀₎ is the noise of the equalized signal (z [k]) including the least so as to have a rising or falling edge, the sampling period (T _b) and And have the same period.

The clock signal CLK is used to increase the accuracy of the obtained determination signal x '[k] by accurately adjusting the timing at which the data determination unit 130 samples the equalized signal z [k] The DFE subsequent stages recover the operating clock for digital signal processing.

At this time, the equalization signal z [k] applied to the data determination unit 130 is multiplied by the feedback ISI signal [k] from the amplified received signal A [k] r [k] based on the reference intensity Bx ' _{(C 1 [k] x '} [k-1], C 2 [k] x' [k-2]) is subtracted ISI signal _{((h 1 [k-1} ], h 2 [k-1]) _{, (h 1 [k-2} ], h 2 [k-2]) because it is) the removed state, a track loss signal is already compensated. Therefore, the data determination unit 130 can extract the correct determination signal x '[k].

Although not shown, the data determination unit 130 may receive the reference voltage V _CM and the reference voltage B and may use it to determine a value for the equalization signal z [k]. The reference voltage V _CM and the reference voltage B will be described later in detail.

The delay feedback unit 140 includes a plurality of delay elements DL1 and DL2 and a plurality of variable amplifiers AMP1 and AMP2 to sequentially delay the determination signal x '[k] k] according to the subtraction control values C ₁ [k] and C ₂ [k] and transmits the amplified signals to the ISI subtraction unit 120.

The first delay element DL1 and the first variable amplifier AMP1 in the delay feedback section 140 are first tap feedback sections and the second delay element DL2 and the second variable amplifier AMP2 are connected to each other through a second tap feedback Wealth. That is, the delay feedback unit 140 includes two tap feedback units.

Hayeoteumeuro in the ISI signal _{((h 1 [k-1} ], h 2 [k-1]), (h 1 [k-2], h 2 [k-2])) 2 open-circuit setting the number of taps of, In FIG. 2, the delay feedback unit 140 includes two tap feedback units. However, when the number of taps is increased, the number of delay elements DL1 and DL2 and the number of variable amplifiers AMP1 and AMP2 provided in the delay feedback section 140 is also increased corresponding to the number of taps. That is, the number of the two tap feedback portions is increased.

Each tap feedback section is connected in a dependent manner. The first delay element DL1 of the first tap feedback section receives the decision signal x '[k] and outputs a delay decision signal x' [k-1] by delaying it by a sampling period T _b , The second delay element DL2 of the second tap feedback section receives the delay determination signal x '[k-1] delayed and output from the first delay element DL1 and is delayed by the sampling period T _b again And outputs the delay determination signal x '[k-2]. That is, when the current received signal r [k] is applied to the DFE, the delay feedback section 140 selects the delayed signal corresponding to the received signal r [k-1], r [k-2] And outputs delay determination signals x '[k-1] and x' [k-2]. Here, each of the plurality of delay elements DL1 and DL2 may be implemented as a flip-flop operating in response to the clock signal CLK.

The first variable amplifier AMP1 of the first tap feedback unit receives the delay determination signal x '[k-1] applied in accordance with the subtraction control value C ₁ [k] applied from the adaptive gain control unit 160, And transmits the first feedback ISI signal C ₁ [k] x '[k-1] to the ISI subtracting unit 120. The second variable amplifier AMP2 of the second tap feedback unit amplifies the difference control value the ISI subtracter (C ₂ [k]) is the delayed decision signal (x '([k-2 ] [k-2]) a second feedback ISI signal C ₂ [k] x) amplifies, according to ( 120).

Wherein the first and second variable amplifiers (AMP1, AMP2) is subtracted the response delay determination that the signal (x '[k-1] , x' [k-2]) control value _{(C 1 [k], C} 2 [ k] to output the feedback ISI signals C ₁ [k] x '[k-1] and C ₂ [k] 1], x '[k-2]) amplified by the gain control value A [k] by the input amplifier 110 and the distortion due to the channel loss, It included in the ISI signal _{((a [k] h 1} [k-1], a [k] h 2 [k-1]), (a [k] h 1 [k-2], a [k] h ₂ [k-2])).

The error discrimination unit 150 receives the equalization signal z [k] and the determination signal x '[k] and outputs the difference between the equalization signal z [k] and the determination signal x' [k] (E [k]) from the error signal e [k].

The error determination unit 150 includes a reference amplifier BAMP and a comparator CMP. The reference amplifier BAMP receives the decision signal x '[k] output from the data determination unit 130, amplifies the reference signal B' by the reference voltage B, and outputs the amplification decision signal Bx '[k]. Since the equalization signal z [k] is a signal generated by the amplified reception signal A [k] r [k] already amplified by the input amplifier 110, the decision signal x '[k] ) Can be accurately compared between the equalization signal z [k] and the decision signal x '[k]. As described above, the amplified reception signal A [k] r [k] is a signal amplified to have a magnitude corresponding to the reference voltage B. [

The comparator CMP compares the value of the equalization signal z [k] with the value of the amplification decision signal Bx '[k] and outputs the difference to the error signal e [k]. That is, the error signal e [k] can be calculated as shown in Equation (1).

The error signal e [k] is output as a binary digital value indicating whether the result of subtracting the amplification determination signal Bx '[k] from the equalization signal z [k] is a positive value or a negative value. do.

The adaptive gain controller 160 analyzes the gain control value A [k] and the difference control values C ₁ [k] and C ₂ [k] by analyzing the error signal e [k] k].

The adaptive gain adjuster 160 adjusts the gain control value A [k] and the difference control values C ₁ [k] and C ₂ [k] respectively based on a least mean square (LMS) . The adaptive variables A [k], C ₁ [k], and C ₂ [k] in each sampling period T _{b are} calculated as an adaptive variable for the error signal e [k] (A [k], C ₁ [k], C ₂ [k]).

Based on the minimum mean square (LMS) technique, the adaptive gain adjuster 160 adjusts the gain control value A [k + 1] to be applied to the received signal r [k + 1] It is possible to obtain each of the control values C ₁ [k + 1] and C ₂ [k + 1] according to equations (2) to (4).

Here, μ is an update rate adjustment value, and if the update rate adjustment value (μ) is large, the error signal e [k] can be rapidly reduced while the stability of the DFE can be degraded. Therefore, the update rate adjustment value mu should be set in consideration of both the update rate and the stability of the DFE, and may be set to 0.05, for example.

The adaptive gain control unit 160 repeatedly updates the gain control value A [k] and the difference control values C ₁ [k] and C ₂ [k] based on the error signal e [k] The gain control value A [k] and the difference control values C ₁ [k] and C ₂ [k] are generated according to the minimum mean square method, As the updating of the values C ₁ [k] and C ₂ [k] is repeated, the error e [k] gradually reaches the minimum value.

In order to update the adaptive variables A [k], C ₁ [k], and C ₂ [k], the functions shown in equations 2 through 4 are based on the error signal e [k] ], C ₁ [k], C ₂ [k]), which is very difficult to implement in hardware and consumes high cost.

In fact, the most important feature of the least mean squares (LMS) technique is that the slope sign of the adaptive variables A [k], C ₁ [k], C ₂ [k] k].

Therefore, in the present invention, based on the sign of the decision signal x [k], x [k-1], x [k-2]) and the error signal e [k] 7] to obtain the updated values of the adaptive variables A [k + 1], C ₁ [k + 1], and C ₂ [k + 1].

That is, if the sign of the slope sign of the adaptive variables A [k], C ₁ [k], C ₂ [k] and the sign of the error signal e [k] are set correctly, The resulting variables (A [k], C ₁ [k], C ₂ [k]) result in optimal values.

Equations 5 to 7 are simply based on the sign of the decision signal x [k], x [k-1], x [k-2] and error signal e [k] k + 1], C ₁ [k + 1], C ₂ [k + 1]).

Since Equation 5 is an equation obtained by modifying Equation 2, the gain control value A [k] must be obtained using the received signal r [k], but the received signal r [k] ), The time difference must be adjusted until the error signal e [k] is obtained from the gain control signal x [k] Value (A [k]).

As a result, the adaptive gain controller 160 of the present invention repeatedly updates the adaptive variables A [k], C ₁ [k], C ₂ [k] based on the error signal e [k] , It is possible to obtain optimal adaptive variables A [k], C ₁ [k], and C ₂ [k] that minimize the error signal e [k] even under various channel loss situations.

FIG. 3 is a diagram for explaining the equalization operation of the decision feedback equalizer of FIG. 2; FIG.

3 (a) shows an example of a received signal A [k] r [k] distorted by a channel loss, and FIG. 3 (b) shows an example of a received signal r [k] Signal z [k].

2, the ISI subtractor 120 subtracts the amplified received signal A [k] r [k] from the received signal r [k] amplified by the gain control value A [k] And outputs the equalized signal z [k] equalized by subtracting the feedback ISI signals C ₁ [k] x '[k-1] and C ₂ [k] x' [k-2].

Input amplifier 110 as a received signal (r [k]), the gain control value (A [k]), so amplified by the amplified reception signal (A [k] r [k ]) , the cursor signals (h ₀₎ , But all the gain control values A [k] are amplified up to the intensity of the ISI signals h ₁ and h ₂ .

However, the ISI subtracting unit 120 does not output the amplified received signal A [k] r [k] amplified by the gain control value A [k] as shown in (a) K] by the difference control values C ₁ [k] and C ₂ [k], which are adjusted together with the gain control value A [k] based on the error signal e [k] ) Is calculated by subtracting the amplified feedback ISI signals C ₁ [k] x '[k-1] and C ₂ [k] x' _{((h 1 [k-1} ], h 2 [k-1]), (h 1 [k-2], h 2 [k-2])), (z equalized signal such as (b) by removing the [k]).

As a result, the currently received reception signal (r [k]) received before receiving the sampling timing signal of the signal generated by the ISI (r [k-1], r [k-2]) ((h 1 [k- _{1], h 2 [k-} 1]), (h 1 [k-2], h 2 , so obtaining a [k-2])) equalized signal (z by removing the influence of the [k]), the gain control value (a [k]) may generate a decision signal (x '[k]) to determine the data value for the pure cursor signal (h ₀₎ components of the received signal (r [k]) by amplification.

FIG. 4 is a diagram simulating a result of repeatedly updating an adaptive variable based on an error signal according to a least mean square (LMS) technique.

As described above, in the present invention, the adaptive gain controller adjusts the reception signal r (k) by the least mean square (LMS) technique from the error signal e [k] according to Equations 2 to 4 based on a least mean square (LMS) (the gain control value A [k + 1]) and the subtraction control values C ₁ [k + 1] and C ₂ [k + 1] . 4A is a graph showing a simulation result obtained by repeatedly updating the adaptive variables A [k], C ₁ [k], and C ₂ [k] (B) shows the slope sign and error signal e [k] of the adaptive variables A [k], C ₁ [k], C ₂ [k] of the applied adaptively variable according to the modified equation (5) to 7 are obtained by digitally _{(a [k], C 1} [k], C 2 [k]) code is repeated a graph showing the values to be updated simulation graph .

In the simulation of FIG. 4, the cursor signal h ₀ and the ISI signals h ₁ and h ₂ for two taps are set to be 500 mV, 200 mV, and 100 mV, respectively. The target amplitude of the equalization signal z [k] is assumed to be 500 mV, and the update rate adjustment value (μ) is set to 0.005.

As shown in FIGS. 4A and 4B, when acquiring the update values of the adaptive variables A [k], C ₁ [k], and C ₂ [k] (B) acquires the updated values of the adaptive variables (A [k], C ₁ [k], C ₂ [k]) sufficiently stable even after 1000 repetitions . That is, a value of a suitable adaptive variable A [k], C ₁ [k], C ₂ [k] corresponding to an arbitrary channel loss at a very high rate.

The adaptive variables A [k], C ₁ [k], and C ₂ [k] according to Equations 5 to 7 are repeatedly updated to converge to a finite specific value, Sign (e [k]) sign (e [k]) and sign (x '[k-1]) sign (e [k]), which are the last items of Equations 5 to 7, And sign (x '[k-2]) sign (e [k]) are repeatedly toggled to values of "-1" and "1". However, the adaptive variables A [k], C ₁ [k], and C ₂ [k] are not significantly changed and finally converge because the magnitude of the update rate adjustment value μ is small.

5 shows an example of an error determining unit for obtaining an error signal for obtaining an adaptive variable in the decision feedback equalizer of the present invention.

In the DFE shown in FIG. 2, the error determining unit 150 is configured to obtain the error signal e [k] in an analog manner. However, as described above, the DFE of the present invention uses the modified signatures 5 to 7 to generate a slope sign and an error signal of the adaptive variables A [k], C ₁ [k], C ₂ [k] the values of the adaptive variables A [k + 1], C ₁ [k + 1], and C ₂ [k + 1] updated from the sign of e [k] .

5 shows a circuit configuration for obtaining the sign (sign [e [k]) of the error signal e [k] to be applied to Equations 5 to 7. Referring to FIG. 5, the error determining unit 150 A signal conversion unit and an error determination unit. The signal converting unit may be composed of two signal discriminators DET1 and DET2, and the error determining unit may include two AND gates AND1 and AND2 and one OR gate element OR. Here, the two AND gates AND1 and AND2 of the error determination unit and the one OR gate element OR are CMOS logic circuit elements.

The received signal r [k] and the amplified received signal A [k] r [k] and the equalized signal z [k] It is transmitted in the form of an analog signal due to a channel loss. Particularly, in the present invention, if the equalization signal z [k] is a CML (Current Mode Logic) signal and the error signal e [k] is applied in the form of an analog signal, the adaptive gain controller 160 , The error signal e [k] can not be analyzed easily, and the hardware configuration becomes very complicated.

In the present invention, as described in Equations (5) to (7), the adaptive gain controller 160 uses the sign (e [k]) of the error signal e [k] _{a [k], C 1 [} k], C 2 [k]) hayeoteumeuro modified to renew, the error determining unit (150) is the error signal (e [k]) sign (sign (e [k] of a) May be generated as a digital signal and transmitted to the adaptive gain controller 160. The error determination unit 150 of FIG. 5 then calculates the error signal e [k] so that the sign (e [k]) of the error signal e [k] can be easily processed by the adaptive gain control unit 160 (Sign [e [k])) as a binary signal which is a CMOS logic signal.

The two signal discriminators DET1 and DET2 of the signal converting unit in the error discriminating unit 150 are differential discriminators and are composed of a slicer in the same manner as the data determining unit 130, ) In the form of a CMOS logic signal.

4 shows the data determination unit 130 together with the two signal discriminators DET1 and DET2 so that the operation of the data determination unit 130 and the operations of the two signal discriminators DET1 and DET2 can be compared.

In FIG. 4, the data determination unit 130 sets the reference voltage V _CM for discriminating the data value of the equalized signal z [k] to 0 V as an example. That is, the data determination unit 130 determines whether or not the determination signal x '[k (k)] is equal to or higher than the reference voltage V _CM at the sampling timing specified by the clock signal CLK ]) And outputs an inverted decision signal x _b '[k] having a logical inversion value of the decision signal x' [k] and the decision signal.

Each of the two signal discriminators DET1 and DET2 uses the discrimination reference values V _CM + B / 2 and V _CM -B / 2 using the reference voltage V _CM and the reference voltage B , The positive discriminant value p [k] and the negative discriminant value p [k] are obtained together with the positive discriminant value p [k] and the negative discriminant value n [k] (n [k]) and outputs the determined value of the inverted reverse amount (p _b [k]) and the reverse negative determination value of the (n _b [k]).

In this case, two signal detectors DET1 and DET2 are provided for the equalization signal z [k] using different discrimination reference values (V _CM + B / 2) and (V _CM -B / 2) Obtaining the positive discrimination value p [k] and the negative discrimination value n [k] is for converting the equalization signal z [k], which is a CML signal, into a CMOS logic signal. A CMOS logic signal is typically used as a complement signal, and since there is a transition region in which a value can not be determined between two signal levels determined to be 0 or 1, a positive (P [k]) and the negative discriminant value (n [k]) are separately read and generated. The first signal discriminator DET1 outputs the positive discrimination value p [k] for the equalization signal z [k] and the discrimination value p _b [k] for the inverting amount, The discriminator DET2 outputs the discrimination value n [k] of the equalization signal z [k] and the discrimination value n _b [k] of the reversing sound to the CMOS logic signal Conversion.

The first AND gates element AND1 of the two AND gates of the error determination unit ANDs the logical value of the positive discriminant value p [k] and the negative discriminant value n [k] And the second AND gate element AND2 ANDs the negative discrimination value n [k] with the inverted determination signal x _b [k] applied from the data determination section 130 and outputs the result. One OR gate element OR receives the outputs of the two AND gate elements AND1 and AND2 and performs an OR operation to output an error signal e [k]. Here, since the error signal e [k] is output as a CMOS logic signal, it has a value of 0 or 1.

The adaptive gain control unit 160 outputs the sign (e [k]) of the error signal e [k] if the logical value of the error signal e [k] The sign (e [k]) of the error signal e [k] is determined as -1 if the logical value of the error signal e [k] is zero. That is, the adaptive gain control unit 160 can easily determine the sign of the error signal e [k] as a digital logic signal.

The adaptive gain controller 160 receives the sign (e [k]) of the error signal e [k] and the previously determined decision signals x '[k-2], x' The change of the adaptive variables A [k], C ₁ [k], and C ₂ [k] using the current decision signal x '[k] Can be arranged.

The logical expression items in Table 1 are logic for generating an update signal of "UP ", which individually increments each of the adaptive variables A [k], C ₁ [k], and C ₂ [k] To reduce the adaptive variables A [k], C ₁ [k], and C ₂ [k] individually by a predetermined unit by reversing the expression for the expression and the logical expression for the update signal of "UP"Quot; DN "is a representation of a logical expression for generating an update signal for " DN ".

The adaptive gain control unit 160 includes an accumulator (not shown) implemented by a charge pump or the like so as to store the previously stored adaptive variables A [k], C ₁ [k], C ₂ [k Of the variable amplifiers AMP1 and AMP2 of the input amplifier 110 and the delay feedback unit 140 by increasing or decreasing the value of the amplification factor AMP2 in response to an update signal of UP or DN And variably outputs the gain control value A [k] and the difference control values C ₁ [k] and C ₂ [k].

As a result, by processing the error signal e [k] and the adaptive variables A [k], C ₁ [k], and C ₂ [k] as digital signals instead of analog signals, To obtain the adaptive variables A [k], C ₁ [k], and C ₂ [k].

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

An input amplifier for amplifying a reception signal continuously transmitted through a channel in response to a gain control signal and outputting an amplified reception signal;
An ISI subtracter for subtracting at least one feedback ISI signal obtained from a previously received signal in the amplified received signal to output an equalized signal by compensating for a channel loss of the received signal;
A data determining unit for determining a signal level of the equalized signal and outputting a determination signal indicating a digital value of the received signal;
A delay feedback unit for receiving and delaying the determination signal and amplifying the delayed control signal in response to at least one subtraction control value to generate the at least one feedback ISI signal;
An error discriminator for obtaining a sign value obtained by a difference between the equalization signal and the decision signal as a sign value of an error signal; And
Using the sign value of the error signal and the sign value of the gain control signal and the at least one difference control value to adjust the gain control signal for the subsequently received received signal and the at least one subtraction control value A gain control unit; Lt; / RTI >
The error determining unit
A signal converter for receiving the equalization signal and comparing the same with a predetermined discrimination reference value to output a positive discrimination value and a negative discrimination value for the equalization signal; And
An error determination unit which receives the positive discrimination value, the negative discrimination value, and the inverted determination signal inverted by the determination signal to discriminate the sign value of the error signal; / RTI > wherein the decision feedback equalizer comprises: delete 2. The apparatus of claim 1, wherein the signal conversion unit
(CML) signal, compares the level of the equalization signal with a first discrimination reference value corresponding to a sum of a predetermined reference voltage and a reference voltage, and outputs the positive discrimination value as a CMOS logic signal A first signal discriminator for outputting the first signal; And
A second signal discriminator for receiving the equalization signal and comparing the level of the equalization signal with a second discrimination reference value corresponding to a difference between the reference voltage and the reference voltage to output the negative discrimination value as the CMOS logic signal, ; / RTI > wherein the decision feedback equalizer comprises: 4. The apparatus of claim 3, wherein the error determination unit
A first AND gate element for receiving and outputting the positive discrimination value and the negative discrimination value, and outputting the result;
A second AND gate element for receiving the inverted decision signal and the negative discrimination value, logically multiplying and outputting the inverted decision signal; And
An OR gate element for performing an OR operation on outputs of the first and second AND gate elements and outputting a sign value of the error signal; / RTI > wherein the decision feedback equalizer comprises: 4. The apparatus of claim 3, wherein the data determination unit
And a slicer that receives the equalization signal and compares the level of the equalization signal with the reference voltage to output the determination signal and the inversion determination signal that are the CMOS logic signals. group. 6. The apparatus of claim 5, wherein the adaptive gain adjuster
A sign value of the error signal, the gain control signal, and a sign value of the at least one subtraction control value, which are the CMOS logic signals, are converted into a least mean square (LMS) To obtain the gain control signal and the at least one difference control value to compensate for channel loss caused by the channel. 7. The apparatus of claim 6, wherein the input amplifier
Wherein the gain is varied in response to the gain control signal to amplify the received signal to a magnitude corresponding to the reference voltage. 8. The apparatus of claim 7, wherein the delay feedback unit
Sequentially amplifying the at least one determination signal delayed by one tap unit corresponding to the sampling period and receiving the determination signal to a size corresponding to the at least one subtraction control value, Lt; RTI ID = 0.0 > ISI < / RTI > subtractor. 9. The apparatus of claim 8, wherein the delay feedback unit
A first tap feedback unit which delays the decision signal by one tap, amplifies the delayed decision signal by a first difference control value, and outputs the amplified decision signal; And
A second tap feedback unit for delaying the delayed decision signal again by one tap, amplifying the two-tap delayed decision signal by a second difference control value, and outputting the amplified decision signal; / RTI > wherein the decision feedback equalizer comprises: 10. The apparatus of claim 9, wherein the adaptive gain adjuster
The gain control signal and the first and second difference subtraction control values may be expressed as Equation (1) and Equation (2) so as to facilitate implementation of the minimum mean square (LMS)

(Where sign is a sign function and mu is an update rate adjustment value).
≪ / RTI >

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