GB2478195B - Content adaptive data path logic processing - Google Patents
Content adaptive data path logic processingInfo
- Publication number
- GB2478195B GB2478195B GB201103197A GB201103197A GB2478195B GB 2478195 B GB2478195 B GB 2478195B GB 201103197 A GB201103197 A GB 201103197A GB 201103197 A GB201103197 A GB 201103197A GB 2478195 B GB2478195 B GB 2478195B
- Authority
- GB
- United Kingdom
- Prior art keywords
- inputs
- primary
- preliminary
- processor
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
Disclosed is an adaptive digital data processing system. The system has primary and secondary preliminary inputs, primary and secondary main inputs, an output, primary and secondary preliminary processors and a main processor. The main processor produces the output based mainly on the primary and secondary inputs. Each of the preliminary processors take their respective preliminary inputs and produce as their output the primary inputs for the main processor. The secondary preliminary processor is controlled in part by the primary preliminary input, so as to cause the primary and secondary main inputs to arrive at the main processor in the same digital signal frame phase, ie at the same time. The preliminary processors may process the overhead bit fields of the inputs or the inputs may be advanced a number of cycles. The processor may have a multiplexer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/713,143 US8204084B2 (en) | 2010-02-25 | 2010-02-25 | Individual bit timeslot granular, input status adaptive multiplexing |
US12/869,955 US8259741B2 (en) | 2010-08-27 | 2010-08-27 | Content adaptive data path logic processing |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201103197D0 GB201103197D0 (en) | 2011-04-13 |
GB2478195A GB2478195A (en) | 2011-08-31 |
GB2478195B true GB2478195B (en) | 2012-03-21 |
Family
ID=43904142
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB201103197A Expired - Fee Related GB2478195B (en) | 2010-02-25 | 2011-02-24 | Content adaptive data path logic processing |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2478195B (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050036515A1 (en) * | 2003-08-14 | 2005-02-17 | Francis Cheung | System and method for demultiplexing video signals |
-
2011
- 2011-02-24 GB GB201103197A patent/GB2478195B/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050036515A1 (en) * | 2003-08-14 | 2005-02-17 | Francis Cheung | System and method for demultiplexing video signals |
Also Published As
Publication number | Publication date |
---|---|
GB2478195A (en) | 2011-08-31 |
GB201103197D0 (en) | 2011-04-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20200224 |