GB2473181A

GB2473181A - A CML-CMOS logic level converter with low supply noise induced jitter

Info

Publication number: GB2473181A
Application number: GB0912942A
Authority: GB
Inventors: Humberto Andrade Da Fonseca; Peter Hunt
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2009-07-24
Filing date: 2009-07-24
Publication date: 2011-03-09
Anticipated expiration: 2029-07-24
Also published as: GB2473181B; GB0912942D0

Abstract

The bias current Ibias controlling the current-switching portions 106,108 of a CML to CMOS logic level converter varies inversely with the supply voltage so that the decreased propagation delay of the output CMOS voltage-mode buffer is counteracted by an increased propagation delay in the predriver 108. Jitter in the output signal due to supply noise is reduced without requiring extra components in the converter. There is thus no loss in bandwidth due to the capacitance of these components. The drain-source resistance of the earthed gate PMOS transistor in the bias stage 102 reduces as the supply voltage increases, leading to a fall in bias current.

Description

IMPROVED CML TO CMOS CONVERTER

BACKGROUND OF THE INVENTION

The present invention relates to integrated circuits using CMOS voltage signal levels, and more particularly, to a CML to CMOS converter and a biasing stage therefor.

Current-mode-logic (CML) circuits have been widely used in high-speed data communication systems largely due to improved switching speeds when compared with voltage-mode-logic circuits.

CML circuits can operate with low signal voltage and higher operating frequency at lower supply voltage than static CMOS circuits. CML is also widely used in high-speed applications due to its relatively low power consumption and low supply voltage.

CML is also considerably faster than CMOS due to its lower voltage swings. CML has an additional advantage over other high-speed forms of logic in that CML can be fabricated using the same fabrication lines as the widely used CMOS circuits and may cohabitate with CMOS logic on the same integrated circuit. Such hybrid circuits combine the high-speed aspects of CML logic and the low power requirements of CMOS logic.

The use of CML and CMOS techno]ogies in a sing]e integrated circuit requires a conversion of CML differential voltage levels to CMOS compatible voltage levels. CML voltage levels represent the two values of a data bit depending on which of the two levels is more positive than the other. A typical CML circuit operates with a differential swing of two to three hundred milliVolts, but smaller and larger swings are possible. In contrast, a typical CMOS circuit operates according to a single ended voltage, with two specified voltage ranges with respect to that defining the two values of a data bit.

A problem with conventional techniques of CML to CMOS conversion is the presence of jitter at the CMOS output, caused in part, by variations in supply voltage VDD. Traditional CML circuits exhibit a very small speed dependency with the supply voltage, which makes this logic suitable for reference clock distributions across an entire chip. On the other hand, the speed of the CMOS output stage has a positive dependence on the power supply voltage. Traditionally, compensation for the effects of power supply variations has been carried out in the CML stage and inevitably involved the use of additional components which leads to additional capacitance in the circuit and hence decreased circuit bandwidth. Hence there is a need for an improved CML-CMOS converter in which the effect of power supply variations on speed is minimized without any loss in bandwidth.

SUMMARY OF THE INVENTION

The present invention provides a CML to CMOS converter including a biasing stage therefor. The configuration of the present invention advantageously compensates for speed variations in the converter due to supply voltage variations by adjusting the bias current supplied to the converter.

The invention and preferred features thereof are further defined in the appended claims.

A specific embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIGURE. 1 is a schematic circuit diagram of a circuit in accordance with an embodiment of the present invention; FIGURE. 2A is a graphical representation of the waveform of the noise in the supply voltage VDD over a period of time; FIGURE 2B is a graphical representation of the bias voltage supplied to the CML to CMOS converter with the supply voltage noise waveform of Figure 2A over the same period of time.

FIGURE 2C are graphical representations of the rising edges of a clock waveform at the CMOS output stage resulting from a peak in the VDD noise waveform of Figure 2A and from a stable 0.85V VDD supply voltage with no noise.

FIGURE 2D is a graphical representation of the rising edges of a clock waveform at the CMOS output stage resulting from a minimum in the VDD noise waveform of Figure 2A.

DETAILLED DESCRIPTION

Referring now to Figure 1, the circuit 100 comprises a biasing stage 102 and a CML to CMOS converter 104. The CML to CMOS converter 104 comprises three stages, a CML input stage 106, an I/C stage 108 and a CMOS output stage 110.

Specifically, the CML input stage 106 includes a differential circuit comprising first and second NMOS transistor 202 and 204. The first NMOS transistor 202 has a gate arranged to receive a CML level signal CML1, a source connected to a common node 205 and a drain connected to the drain of a first PMOS load transistor 206 of which the gate and drain are coupled together. The second NMOS transistor 204 has a gate arranged to receive a CML level inversion signal CML2, a source connected to the common node 205 and a drain connected to the drain of a second PMOS load transistor 208 of which the gate and drain are coupled together. The sources of the first and second PMOS load transistors 206 and 208 are connected to power supply voltage VDD which is typically of the order of 0.85-1.1V. A third NMOS transistor 210 has a gate arranged to receive a bias voltage V1 from the biasing stage 102, a drain connected to the common node 205 and a source connected to a ground voltage terminal. The third NMOS transistor 210 controls connection between the common node 106 and the ground voltage terminal in response to the bias voltage V1 to supply a sink current to the common node 205. The biasing stage 102 will be described in more detail below The I/C stage 108 of the converter comprises third and fourth PMOS transistors 212 and 214 and fourth and fifth NMOS transistors 216 and 218. The gates of the third and fourth PMOS transistors 212 and 214 are coupled to the gates of the first and second PMOS load transistors 206 and 208 of the CML input stage 104 respectively to form first and second current mirror circuits 220 and 222. The sources of third and fourth PMOS transistors 212 and 214 are connected to power supply VDD, while the drains thereof are respectively coupled to the drains of fourth and fifth NMOS transistors 216 and 218 respectively. The sources of the fourth and fifth NMOS transistors 216 and 218 are connected to the ground voltage terminal. The drain of the fifth NMOS transistor 218 is coupled to the gate thereof, while the gates of the fourth and fifth NMOS transistors 216 and 218 are connected together to form a third current mirror circuit 224.

The drain of the fourth PMOS transistor 212 is connected to output node 226 that is coupled to the input of CMOS output stage 110.

The CMOS output stage 110 comprises an inverter including PMOS transistor 228 and NMOS transistor 230.

In operation, as the differential CML inputs CML1 and CML2 switch, current is switched between the left and right legs of the differential transistor pair 202 and 204. In dependence on which of the two CML inputs CML1 or CML2 is higher, current is sourced by either PMOS load transistors 206 or 208 of the CML input stage 104. If current is sourced by PMOS transistor 206, the current is mirrored through PMOS transistor 212 of the I/C stage 108. If current is sourced by PMOS transistor 208, this is mirrored through PMOS transistor 214 of the I/C stage 108, and then through NMOS transistors 218 and 216 of the third current mirror 224. As a result the output node 226 of the I/C stage 108 is either charged up (i.e., at a high-level) by PMOS transistor 212 (if CML1 > CML2) or discharged (i.e., at a low-level) through NMOS transistor 216 (if CML2 > CML1) The inverter of CMOS output stage 110 outputs a high-level signal at CMOS logic amplitude when the I/C output node 226 is at a low-level (i.e., CML2 > CML1), and outputs a low-level signal at CMOS logic amplitude when the I/C output node 226 is at a high level (CML1 > CML2) The biasing stage 102 will now be described with reference to Figure 1. The biasing stage 102 comprises first and second NMOS transistors 302 and 304, first and second PMOS transistors 306 and 308, a resistor 310 and an op-amp 312. NMOS transistors 302 and 304 have equal dimensions and have their gates coupled together.

PMOS transistor 306 has a source connected to the power supply VDD, a gate connected to the ground voltage terminal and a drain connected to the source of second PMOS transistor 308. The gate of second PMOS transistor 308 is coupled via node 314 to one terminal of resistor 310, the other terminal of which is connected to the power supply VDU. The gate and drain of second PMOS transistor 304 are respectively coupled to the inputs of the op-amp 312, the output of which is coupled to a node between the common gates of NMOS transistors 302 and 304.

The op-amp 312 forces the gate and drain of PMOS transistor 308 to have the same voltage, the feedback ioop causing the current in NMOS transistors 302 and 304 to stabilize at have the same value. On stabilizing of the ioop, the arrangement of PMOS transistors 306 and 308 and resistor 310 form a reference current generator, the current of which depends on the equivalent drain-source resistance of transistor 306. The gate of PMOS transistor 306 is connected to ground to ensure that it will operate in the triode region because the gate-source voltage VGC will always be sufficiently higher than the drain-source voltage VDS. In the triode region, PMOS transistor 306 is equivalent to a variable linear resistor controlled by the gate source voltage VGS and since the gate of transistor is grounded, V is equal to the supply voltage VDD. The relationship between D, V and VL)S for a PMOS transistor in the triode region is given by = i<i. (VSG -VT)VSD -(1) where VSG�=VT and VSD�=VSDSAT(=VSG-VT) and K is Boltzmanns constant, W/L is the width-to-length ratio of the NMOS, VSG is the source-gate voltage of the PMOS, and V1 is the threshold voltage of the PMOS and VSD is the source-drain voltage of the PMOS.

The equivalent resistance REQ of the PNOS can be calculated as REQ' = ____ = KI (VSG - ) -VSD -VSD (2) or REQ= w( 1 3)

KP VDS SAT -VDS

For VDSSAT))VDS, and since the gate source voltage V13 is equal to the supply voltage V, equation (3) can be written as REQW1 (4) Hence, the biasing stage 102 is configured so that the biasing current bias produced, has a negative dependence on the supply voltage VDD. That is, as the supply voltage VDD is marginally incremented (due to supply noise), the resistance REQ of the PMOS transistor 306 marginally decreases causing the bias current bias supplied to transistor 210 of the CML stage 104 also to marginally decrease.

The present invention advantageously reduces the effect of power supply variations on the speed of the CML to CMOS converter 104 by adjusting the biasing current provided by the biasing stage 102 to compensate for such variations. As described previously, since CML levels are defined by a current, the speed of CML input stage 106 has little dependency with incremental variations of the biasing current bias or supply voltages VDD. However, the speed of I/C stage 108 of the converter 104 exhibits a negative dependency on the supply voltage due to the variation in the biasing current bias from the biasing stage 102 as a result of variations in the supply voltage VDD. The biasing current produced by the biasing stage 102 is mirrored from the loads of the CML input stage 106 to the I/C stage 108, but any variation therein has little impact on the speed of the CML input stage 104 itself. The slope of the clock waveform at the output node 226 of the I/C stage 108 depends on the ratio between bias and the input capacitance of the CMOS output stage 110.

On the other hand, the speed of the CMOS output stage 110 increases with supply voltage V because the signal levels used are either VDD or ground and the overdrive voltage (i.e., V -V1) applied to each transistor increases as the supply voltage VDD increases, causing the transistors to switch faster.

However, the dimensions of PMOS transistor 302 of the biasing stage 102 are selected so that any increase in the speed of the CMOS stage (110) due to power supply variations is compensated by a corresponding decrease in speed of the I/C stage (108) due to a decrease in the biasing current bias from the biasing stage.

The overall effect of the compensation described above is that any jitter on the rising edges at the CMOS output stage 110 due to variations in the supply voltage are corrected by the resulting variation in the bias current 1h As a result,. This is illustrated with reference to Figures 2A to 2D.

In particular, Figure 2A illustrates the waveform of the noise in the supply voltage VDD over a period of time, while Figure 2B illustrates the resultant bias voltage supplied to the CML to CMOS converter with the supply voltage noise waveform of Figure 2A over the same period of time. Figure 2C illustrates the rising edges of a clock waveform at the CMOS output stage resulting from a peak in the VDD noise waveform of Figure 2A (plot A) and resulting from a stable 0.85V V supply voltage with no noise (plot B) . In both of these plots, the outputs of the converter cross VDD/2 at the same instant in time, meaning that there is no jitter added from the different supply levels.

Similarly, Figure 2D illustrates the rising edges of a clock waveform at the CMOS output stage 110 resulting from a minimum in the VDD noise waveform of Figure 2A. As can be seen, as the supply voltage become equal, the outputs of the two converters also match.

The feedback ioop inside the biasing stage 102 has a certain bandwidth and within that bandwidth the loop is able to track variations of the supply voltage. Since only power supply noise within the bandwidth of the ioop is compensated, the bandwidth of the loop is made as high as possible.

In summary, any increase in the speed of the CMOS stage of the converter due to power supply variations is compensated by a corresponding decrease in speed of the I/C stage due to a decrease in the biasing current Ibias from the biasing stage.

This results in the overall CML to CMOS converter being immune to incremental supply variations due to supply noise.