GB2473180A

GB2473180A - Voltage controlled oscillator with reduced noise

Info

Publication number: GB2473180A
Application number: GB0912939A
Authority: GB
Inventors: Humberto Andrade Da Fonseca; Peter Hunt; Andrew Pickering; Joaquim Machado
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 2009-07-24
Filing date: 2009-07-24
Publication date: 2011-03-09
Also published as: GB0912939D0

Abstract

An improved control circuit for a CMOS ring oscillator is provided. The circuit comprises an NMOS transistor in a source follower configuration arranged to supply power to the ring oscillator. The transistor may be a native NMOS (NNMOS) device; this provides an intrinsically better noise performance than the prior art in which a PMOS transistor acts as a current source. The circuit is particularly suitable for deep sub-micron IC technologies. A differential delay cell topology (fig.2) is preferred. Applications include phase locked loop based on ring oscillators operating at frequencies above 1 GHz.Keywords: flicker noise, phase noise, jitter, loop filter, ground referred

Description

IMPROVEMENTS IN OR RELATING TO VOLTAGE CONTROLLED

OSCILLATORS

FIELD OF THE INVENTION

The present invention relates to voltage controlled oscillators. More particularly, the present invention relates to an improved CMOS ring oscillator and a control circuit therefor.

BACKGROUND OF THE INVENTION

Known Vo]tage Controlled Oscillators (VCO) with de]ay cells, use as a control element, a PMOS transistor acting as current source or a PMOS transistor controlled by an operational amplifier (OPAMP) in order to refer the control voltage to ground. Such a configuration significantly impacts on high VCO gains and random noise generation.

Thus there is a need for an improved VCO in which these effects are mitigated.

SUMMARY OF THE INVENTION

The present invention provides an improved control circuit having an NMOS follower configuration for controlling a CMOS ring oscillator. According to the present invention there is provided an NMOS controlled ring oscillator circuit as claimed in the appended claims.

Examples of the invention will now be described with reference to the accompanying drawings, of which: Figure 1 shows an NMOS controlled ring oscillator according to a preferred embodiment of the present invention; Figure 2 shows a schematic diagram of an improved VCO according to a preferred embodiment of the invention, which includes a current starved ring oscillator and the controlling transistor NCTRL; Figure 3 shows a graph plotting the voltage characteristics of NCTRL, in accordance with a preferred embodiment.

SPECIFIC DESCRIPTION

Figure 1 shows a block diagram of a Voltage Controlled Oscillator (VCO) according to a preferred embodiment, comprising a Ring Oscillator and Control Element.

The Ring Oscillator is a CMOS ring oscillator configured as an N-stage multiple pass cross-coupled ring oscillator, and comprises a series of delay cells whose speed depends upon its supply voltage.

In deep sub-micron CMOS technologies, analogue PLL5 based on ring oscillators operating at frequencies above 1GHz have their noise budget dominated by noise induced by the loop filter, and more specifically the resistor in the loop filter, whose noise is amplified by the gain of the VCO. This is a constraint imposed by the reduced supply voltage and the pressure to reduce the area of the designs. In 4Onm CMOS technology designers are forced to operate with supply voltages as low as 75OmV, which forces us to increase the VCO gain (Ky) in order to cover the required frequency ranges. A typical value for Ky is in the order of 15GHz/V at a frequency of 3GHz. The pressure to reduce the area of the designs force designers to make the low frequency poles of the loop filter by increasing the resistor as opposed to increasing the capacitance. These factors all contribute in the end to making the loop filter the dominant source of noise, instead of the intrinsic VCO phase noise.

A preferred embodiment of the invention mitigates against these undesirable effects by employing an NMOS transistor in a source follower configuration to control the Ring Oscillator, thereby inherently reducing the gain of the VCO. Such a topology may be used for Ring Control in deep-sub micron technologies without problems in the headroom by using a Native type of NMOS transistor.

Other advantages of approach implemented by the present invention include: * The loop filter of the VCO may be referred to ground without the need for a controlling operational amplifier; * The gate capacitance of the NMOS transistor is reduced due to the small gain between the gate and the source. The capacitance is reduced due to the Miller effect. In this case the gain from Gate to source is close to unit and the configuration is non inverting, which actually reduces the capacitance; * Because a Source Follower intrinsically has a gain smaller than unitary gain, this leads to VCO5 with smaller gain, which is important for noise considerations as the noise is minimized. This is particularly important for the reduction of gain produced by the loop filter components.

A further preferred embodiment of the present invention is presented below as used in a Phase Locked Loop (PLL) circuit.

Conventionally integrated Phase-Locked Loops based on current starved CMOS ring oscillators need, as ring controlling element, either a PMOS, operating as current source or an operational amplifier loop to regulate the ring voltage. The present invention demonstrates that, by using a Native NMOS device, a CMOS ring oscillator may be driven in a source follower configuration with significant advantages.

NMOS transistors formed directly on the surface of a semiconductor region that has not undergone the process of enhancement, and often referred to as Natives (NNMOS) , present interesting characteristics for analogue design such as the very low, often negative, threshold voltage (Vt) and an intrinsically better noise performance. Also, the fact that no extra IC mask is needed besides those already required by standard CMOS digital process, makes them available at no extra cost.

Figures 1 and 2 present the schematics of the VCO and Delay Cell, respectively. The top of the Ring Oscillator is driven by the NNMOS transistor NCTRL in a source follower configuration with a typical VGS drop of 6OmV when operating at 2.5GHz. The graph of Figure 3 presents the voltage characteristics of the NNCTRL as the control voltage VC is swept from 0.3 to 0.94V. The Threshold voltage keeps constant at - 22OmV while VGS grows with VC reflecting an increase in IRing.

The lower than unit gain (Av), close to O.4V/V at 2.5GHz in our design, from the Gate to the Source of NNCTRL, intrinsic to a Source Follower topology, and also observable by inspecting Graph 1, results in a smaller VCO gain (Ky) if controlling it from the Gate of NCTRL as opposed to forcing the RING_RAIL indirectly by the usage of a mirroring operational amplifier.

Lowering the Ky of VCO is an important design target due to its direct impact on area and noise performance.

The parasitic capacitance, from VC to ground is dominated by the Cgs of NCTRL. However, because Av is positive and smaller than unit, the Miller effect actually scales down Cgs when refereeing it to VC. This characteristic assumes some importance when designing very high bandwidth PLL5 with restrictions in area due to the resulting parasitic pole.

The delay cell topology used in a preferred embodiment is differential for the purpose of better power supply rejection ratio both in the VCO and in the clock buffers following it. MPP together with MNP and MPN together with MNN form the pair of inverters Ii and 12 coupled by the PMOS devices MCC1 and MCC2.

The gates of MPP and MPN are, however, taken one delay cell before the gates of MN and MNN which creates an interpolation between the delay of one cell and the delay of two consecutives cells resulting in a faster ring oscillator. The speed enhancement achieved with this technique allows for the design to use gate lengths bigger than the minimum permitted by the technology node in an effort to improve the jitter performance by reducing component flicker noise.

The cross coupled pair MCC1 and MCC2 forces differential states at the output of each delay cell avoiding this way a lock up scenario in the ring. These two transistors also create hysteresis in the differential switching point. Determined by the relative strengths between the cross coupled pair and the inverters, the aperture of the hysteresis characteristic, impacts the overall oscillation frequency and phase noise performance and was thus adjusted by simulation.

Claims

CLAIMS1. A control circuit for controlling a CMOS ring oscillator, comprising: an NMOS transistor arranged in a source follower configuration with said ring oscillator.
2. An improved Voltage Controlled Oscillator VCO comprising: a CMOS ring oscillator; and an NMOS transistor arranged in a source follower configuration with said ring oscillator.
3. An improved VCO as claimed in claim 2, wherein the ring oscillator comprises: an N-stage multiple pass cross-coupled ring oscillator.
4. An improved VCO substantially as herein described with reference to the drawings.
5. The subject matter hereof or any part thereof in any novel, inventive or useful combination.