GB2466981A - Memory management unit with a dedicated cache memory for storing management data used to fetch requested data - Google Patents
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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Abstract
Disclosed is a memory management unit 12 with a cache memory 26 that stores management data 20 to be used in generating a management response to memory access requests. The unit also has prediction circuitry 22 that predicts the management data that will be required by the memory management unit and fetches this into the cache memory prior to a memory access request that requires that management data being issued or received by the memory management unit. The cache stores a subset of the management data that is stored in a management data memory. The management data may be mapping data for mapping virtual to physical memory addresses, access permission data and/or storage parameter data for controlling storage of data. The memory access requests may be a linked list of data with data pointing to memory address of next portions of said list, which is used by the prediction circuitry to determine the next required data. The management data may be two level page table data, with the higher level entry identifying a low level page table that specifying mapping data.
Description
MEMORY MANAGEMENT UNIT
This invention relates to the field of data processing systems. More particularly, this invention relates to memory management units for managing memory accesses within data processing systems.
It is known to provide data processing systems with memory management units for managing memory accesses. Memory management units may have a variety of different functions. Some memory management units may serve to translate a virtual address to a physical address. Other memory management units (memory protection units) may be used to control access permissions to certain regions of memory (e.g. provide access only to privilege level code or to secure domain code). It is also known to use memory management units which specify storage control parameters associated with regions of memory, such as whether data from that memory is cacheable or bufferable.
Memory management units typically include a cache memory (sometimes termed a translation lookaside buffer (TLB) when virtual-to-physical mapping is performed) for storing management data associated with previously accessed memory addresses. Thus, while the main management data, such as page table data, may be located in main memory, the management unit itself holds a local copy of some of this management data in order to speed up the operation of the memory management unit. The memory management unit is typically on the critical path for determining the speed of a memory access and if the management data needed by the memory management unit is not held within the cache memory of the memory management unit, then it must be fetched from elsewhere before the management response for a corresponding memory access request can be generated. This can introduce a large and undesirable delay (latency) associated with a memory access request that misses in the cache memory of the memory management unit.
It will be appreciated from the above that the provision of a cache memory within the memory management unit for the purpose of holding a local copy of some of the memory management data is desirable in speeding up overall system performance. However, there is an overhead associated with this cache memory in terms of gate count and power consumption. Thus, while providing a large cache memory within the memory management unit may speed up operation, it has the disadvantage of increasing the system cost, gate count and power consumption. Furthermore, when large volumes of memory access requests are being performed, such as may typically be associated with image processing, it is difficult to provide sufficient cache storage within the memory management unit to hold the memory management data for all of the memory access requests associated with the image processing. I0
Image processing often involves memory access requests to a frame buffer storing image data. This frame buffer may contain a large quantity of data, e.g. a full frame of high resolution image data of HD IO8Op format may occupy approximately 8 MegaBytes of data storage. Assuming this frame buffer is divided into 4 KiloByte pages, this may correspond to an approximate requirement of 8 KiloBytes of cache storage within a memory management unit if it is to store all of the management data for memory accesses to the frame buffer. This is a disadvantageously large amount of cache storage to provide within a memory management unit. Furthermore, as system design advances, it is likely that image resolutions will increase and even such a large amount of cache storage would become insufficient and the situation could arise that due to cache replacement algorithms the management data required for use would never be found within the cache storage of the memory management unit, e.g. if a least recently used replacement algorithm was used for the cache storage of the memory management unit.
There is a need to provide memory management units able to efficiently store within their cache memory management data for generating management responses in respect of received memory access requests.
Viewed from one aspect the present invention provides a memory management unit for managing memory accesses within a data processing apparatus, said memory management unit comprising: a cache memory for storing management data for managing data access requests, said management data being fetched from a management data memory and said cache memory storing a subset of said management data stored within said management data memory; access management circuitry responsive to a memory access request and said management data stored within said cache memory to generate a management response; and prediction circuitry for predicting required management data and for triggering fetching of said required management data from said management data memory to said cache memory in advance of receiving by said access management circuitry of a memory access request corresponding to said required management data.
The present technique recognises that in many real life data processing situations the pattern of memory access requests that are to be made is highly predictable. In this case it is possible to predict what management data will be required by the memory management unit in advance of a memory access request needing that memory management data actually being issued to the memory management unit. Thus, instead of a cache miss occurring within the cache memory of the memory management unit in respect of the management data for a memory access request, the management data can be predicted as being required in respect of a future memory access request and may be fetched and stored within the cache memory of the memory management unit in advance of being required. In this way, the latency penalty associated with the management data not being present within the cache storage of the memory management unit at the time that it is needed may be avoided. The prediction of which management data may be required can be surprisingly straight forward since many real life systems perform predictable and regular patterns of memory accesses, e.g. memory accesses associated with image processing of raster scan data.
It will be appreciated that the management data stored within the cache memory of the memory management unit may take a variety of different forms. As an example, the management data may include mapping data for mapping a virtual memory address specified by a memory access request to a physical address for addressing a main memory with the management response including generating the required physical address.
Another example form of management data includes access permission data for controlling access to data corresponding to a memory access request with the management response including generating an access control signal. Thus, the memory management unit could perform the role of a memory protection unit in controlling access, such as, to only grant access to certain memory regions to privilege level code or secure domain code.
Another example form of management data includes storage parameter data for controlling storage of data corresponding to a memory access request with the management response including generating a storage control signal. Thus, storage control data, such as data indicating whether the data corresponding to the memory access request is cacheable or bufferable, may be provided within the management data and appropriate storage control signals generated by the memory management unit, e.g. to suppress caching of the data concerned if it is indicated as non-cacheable data.
While it will be appreciated that the memory management unit of the present technique can be used in a variety of different applications where regular/predictable patterns of memory accesses are performed, the present technique has particular usefulness when the memory management unit is coupled to graphics adaptor circuitry and the memory access requests received from the graphics adaptor circuitry correspond to a raster scan access sequence of image data. In this case, the prediction circuitry can predict the required management data based upon a continuation of the raster scan access sequence as this will nearly always be the case.
In one form of raster scan, the prediction circuitry predicts the memory access requests as having a linearly increasing memory address within a frame buffer such that the entirety of the frame buffer is traversed.
In other embodiments, such as when displaying a selected portion of a larger image, the prediction circuitry may predict the memory access request as having memory addresses starting from a specified line start address, increasing along the portion of a raster line to be accessed as specified by a line length, jumping to a start address of a next line spaced by a specified line pitch from the start address and then repeating this sequence. Thus, a raster-scanned portion of a frame buffer containing a full image may be read out by a sequence of memory accesses that can be accurately predicted by the prediction circuitry so as to ensure that the relevant management data is present within the cache memory of the memory management unit in advance of being required.
Another example use of the present technique where memory access requests can be predicted is where the memory access requests correspond to a linked list of data including pointer data pointing to memory addresses of next portions of the linked list. In this circumstance, the prediction circuitry can predict requirement management data based upon pointer data read from received portions of the linked list and effectively prefetch the management data for the next portion of the linked list before the memory access request for that next portion of the linked list is actually issued.
The management data can take a variety of different forms as previously discussed.
Furthermore, the management data may be internally structured in different ways so as to increase the efficiency with which it may be accessed. One particularly efficient way of structuring the management data is to provide two-level management data in which the management data for a memory access request is formed of a high-level page directory entry identifying a low-level page table, with the page table entry specifying mapping data for mapping virtual memory addresses to physical memory addresses. This two-level data may also include data indicating its own validity as well as permission data indicating permission constraints associated with the regions of memory being accessed (e.g. privilege level only).
When prediction of the management data required is performed by the prediction circuitry, the cache memory can serve to store a current page table entry and a predicted next page table entry. It may be in some embodiments that the cache memory does not store any page table entries other than the current page table entry and the next page table entry since the probability of the predicted next page table entry being correct is sufficiently high that further cache storage capacity would be a waste of resource.
In embodiments storing a current and next page table entry, a change from which page table entry is currently in use may serve to trigger fetching of a new predicted next page table entry. Thus, each time a change of the page table entry in use occurs, the prediction circuitry can prefetch what is predicted to be the next required page table entry such that this next required page table entry will be available within the cache memory of the memory management unit when it is actually required.
The highly predictable nature of the memory accesses may be further exploited to reduce power consumption in some embodiments by arranging that the access management circuitry checks access permissions when there is a change in the page table entry currently in use, but does not perform a further check of access permissions until a further change in page table entry occurs. This behaviour recognises that a sequence of memory access requests within one page will typically occur together and will share the same permissions as these are defined at the granularity of the page table entry and accordingly there is no need to repeatedly check them for memory access request within the page of that page table entry.
In a similar manner, the access management circuitry may use the current page table entry to provide the mapping data in use without a lookup of further data in the cache memory occurring for each memory access request since the mapping is again provided at the granularity of the page table entry and will be the same within the page.
Within the context of the two-level management data structure previously mentioned, the cache memory may store a current page directory entry and predicted next page directory entry such that upon a change of page directory occurring the relevant next page directory entry is already stored within the cache memory of the memory management Unit even though it was not previously used.
In some embodiments, the cache memory need not store any page directory entries other than the current page directory entry and the next page directory entry since the regular pattern of predictable memory accesses will not result in rapid switching between page directory and entries and accordingly will provide sufficient time for a new next page directory entry to be fetched whenever a change in the current page directory entry is made.
It will be appreciated that the prediction circuitry could be formed in a variety of different ways so as to match the predictable pattern of memory access requests made to the memory management unit concerned. In some embodiments the prediction circuitry can be entirely hardware based and have a configuration fixed (subject to possible initialisation parameters) so as to perform a prediction of required memory management data in a pattern that is matched to the component from which memory access requests are being received.
In other embodiments, the prediction circuitry may respond a software generated prediction of memory addresses of future memory access requests. It may be that the algorithm being executed on the supported source of memory access requests predicts its future requests and supplies this information to the memory management unit in order to avoid stalls at the memory management unit level due to management data not being present within the cache memory of the memory management unit. Furthermore, it will be appreciated that hybrid hardware and software generated predictions may also be provided.
It will be appreciated that the memory management unit is dependent upon the prediction accuracy it is able to achieve in order to avoid stalls due to the management data not being present within the cache storage of the memory management unit. Prediction accuracy may be improved when the memory management unit is dedicated to access requests from an associated source of memory access requests as then the prediction mechanisms of the prediction circuitry may be tailored to the specific requirements of the source of memory access request being serviced. Within such systems, the dedicated memory management unit may access a shared memory which is also accessed by other sources of memory access requests that do not have a predictable pattern and accordingly do not utilise the dedicated memory management unit as this would be unable to effectively predict their memory access pattern.
Viewed from another aspect the present invention provides a memory management unit for managing memory accesses within a data processing apparatus, said memory management unit comprising: cache means for storing management data for managing data access requests, said management data being fetched from a management data memory means and said cache means storing a subset of said management data stored within said management data memory means; access management means for generating a management response in response to a memory access request and said management data stored within said cache memory; and prediction means for predicting required management data and for triggering fetching of said required management data from said management data memory means to said cache means in advance of receiving by said access management circuitry of a memory access request corresponding to said required management data.
Viewed from a further aspect the present invention provides a method of managing memory accesses within a data processing apparatus using a memory management unit, said method comprising the steps of: st6ring management data for managing data access requests within a cache memory, said management data being fetched from a management data memory and said cache memory storing a subset of said management data stored within said management data memory; generating a management response in response to a memory access request and said management data stored within said cache memory; predicting required management data; and triggering fetching of said required management data from said management data memory to said cache memory in advance of receiving of a memory access request corresponding to said required management data.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates an integrated circuit including a memory management unit dedicated to servicing memory requests from a graphics adaptor; Figure 2 illustrates the mapping between virtual address space and physical address space for a frame buffer of image data that requires management by a memory management unit; Figure 3 schematically illustrates a two-level management data structure for use by a memory management unit; Figure 4 schematically illustrates a memory access pattern corresponding to a frame buffer subject to a full raster scan; Figure 5 schematically illustrates a memory access pattern corresponding to displaying a selected portion of a larger raster scan frame buffer; and Figure 6 schematically illustrates a memory access pattern corresponding to a linked list of data; Figure 7 schematically illustrates a memory management unit including prediction circuitry for predicting required memory management data to be fetched to a cache memory within the memory management unit; and Figure 8 is a flow diagram schematically illustrating the operation of the memory management unit of Figure 7.
Figure 1 schematically illustrates a data processing system 2 in the form of a system-on-chip integrated circuit 4 driving a liquid crystal display 6. The system-on-chip integrated circuit 4 includes a plurality of functional units including a microprocessor core 8, a graphics adaptor 10, a memory management unit 12 associated with the graphics adaptor 10, a universal asynchronous receive and transmit (UART) unit 14 and a main memory 16. The main memory 16 is a shared memory shared by the functional units 8, 10, 14 within the system -on-chip integrated circuit 4.
The graphics adaptor 10 generates memory access requests using virtual addresses VA that are translated into physical addresses PA by the memory management unit 12 dedicated to the graphics adaptor 10. The memory access requests generated by the graphics adaptor 10 are to a frame buffer 18 stored within the main memory 16. Also located within the main memory 16 is page table data 20 which provides management data used by the memory management unit 12 in mapping the virtual addresses VA to the physical addresses PA. The page table data 20 may also include permission data and validity data.
In operation the microprocessor core 8 generates physical addresses to the main memory 16, as does the UART unit 14. Accordingly, the processor core 8 and the UART unit 14 do not require virtual-to-physical address mapping and may be arranged so as to not require other functions of a memory management unit. Thus, the memory management unit 12 can be dedicated to the graphics adaptor 10. The graphics adaptor 10 has a highly predictable sequence of memory request accesses such that the memory management unit 12 can predict which management data from within the page table data 20 will be required before a corresponding memory access request requiring that management data is issued from the graphics adaptor 10. Thus, the memory management unit 12 can prefetch this management data from the page table data 20 and accordingly have the relevant management data stored within the cache memory of the memory management unit 12 prior to it being needed. This avoids a stall caused by a cache miss within the memory management unit 12.
Figure 2 schematically illustrates a relationship between virtual address space and physical address space used to store a frame buffer of image data. Within the virtual address space the frame buffer comprises contiguous memory addresses. However, due to memory fragmentation and other real world considerations, the frame buffer often cannot be allocated to a contiguous memory region within the physical address space. In this example the frame buffer is allocated to three distinct regions of physical address space. The management data provided by the page table data 20 stores the virtual-to-physical mapping data needed to relate addresses within the virtual address space to addresses within the physical address space such that when a memory access request is received from the graphics adaptor 10 specifying a virtual address this may be translated into a physical address and issued to the main memory 16 (assuming relevant permission functions are in place).
Figure 3 schematically illustrates a two-level structure of management data used to provide virtual-to-physical address mapping. This two-level structure may be considered to be formed of high-level page table directory entries each specifying a relevant page table and a plurality of page tables each comprising a plurality of page table entries with an individual page table entry specifying a virtual-to-physical mapping to be used in respect of its page of memory addresses (typically a four KiloByte page).
In this example, it will be seen that the highest order ten bits VA[3 1:22] of the virtual address are used to index into the page directory entries and read a pointer to a relevant page table. The page directory entries span the entirety of the virtual address space. Thus, there is a page directory entry for every possible virtual address generated. It may be that some of the page director entries are marked as invalid as they are not intended to be in use. If a virtual address seeks to access such an invalid page directory entry then this can be detected and a memory abort can be triggered.
When the relevant page table has been identified by the page directory entry indexed into by the highest order ten bits of the virtual address, the next ten bits within the virtual address (i.e. VA[21:12]) are used to index into that page table and read the appropriate page table entry which specifies the mapping data to be used to provide the virtual-to-physical mapping programmed in place for that page. The least significant twelve bits of the virtual address VA[1 1:0] are used unchanged to form the least significant twelve bits of the physical address PA[1 1:0]. This corresponds to the page granularity being 4 KiloBytes.
Figure 4 schematically illustrates one example form of a sequence of memory access requests having a highly predictable pattern which can be utilised by prediction circuitry within the memory management unit 12 to prefetch management data in advance of memory access requests actually needing that management data being received by the memory management unit 12. In the example of Figure 4, a full raster scan of a frame buffer of image data is performed. Since the full frame buffer is being read, the memory access requests have a simple sequence of linearly increasing virtual addresses. Thus, the prediction circuitry within the memory management unit 12 when it reaches the end of a page of memory corresponding to a currently in-use page table entry can change to use the predicted next page table entry and then fetch a new next predicted page table entry based upon an assumption that the memory addresses will linearly increase to follow the full raster scan pattern. There will be a wrap at the end of the frame back to the start of the frame which can be detected by an appropriate counter.
Figure 5 illustrates a raster scan of a portion of a frame of image data. The memory access pattern is again highly predictable although more complex than that illustrated in Figure 4. In this example, the sequence of memory access request addresses starts from a line start position and increases along a raster line with a linear increase up to the line length specified. At this point, the line start position is updated by adding a value corresponding to the pitch of lines thereby selecting the line start position of the next raster line within the raster scan of the portion of the full image. The process then proceeds by linearly increasing the memory address along the raster line for the line length associated with the selected portion of the image being displayed.
The prediction circuitry within the memory management unit in an embodiment supporting such raster scan of a selected portion of an image, prediction may be programmed with values indicating the initial line start at one corner of the selected portion of the image, the line length and the pitch with the hardware within the prediction circuitry then being responsible for generating the predictions as to which management data will be required based upon arithmetic circuits using these programmed values.
Figure 6 illustrates another example of a predictable memory access request pattern.
In this case, the data being accessed is in the form of a linked list with each data item fetched being in the form of a packet of data including a pointer to the next data item together with its data payload. Thus, as each package is received, the pointer for the next packet may be read from the received packet and this pointer used to fetch the appropriate management data into the memory management unit that will be required when the next packet of data is requested.
Figure 7 illustrates an example embodiment of the memory management unit 12 of Figure 1 supporting prediction associated with the full raster scan of Figure 4. In this case, the memory management unit 12 includes prediction circuitry 22, access management circuitry 24 and a cache memory 26. It will be appreciated that the memory management unit 12 may contain further functional elements. It will also be appreciated that the divisions between the various circuitry illustrated in Figure 7 are flexible, e.g. it may be that some of the circuitry used by the prediction circuitry 22 is shared with circuitry used by the access management circuitry 24. Such variations are included within the scope of the present technique.
The cache memory 26 in this example embodiment is storing management data specifying at least a virtual-to-physical address mapping. The cache memory 26 may sometimes be referred to as a translation lookaside buffer (TLB). Within the cache memory 26 there is provided storage for a current page directory entry and a next page directory entry as well as storage for a current page table entry and a next page table entry. In this example, the storage requirements of the cache memory 26 are only for these four items of data making the cache memory 26 small and efficient.
In operation a virtual address VA [31:0] comprising a 32-bit value is received from the graphics adaptor 10. This virtual address VA is supplied to the access management circuitry 24 where a virtual-to-physical address mapping is performed using the current page table entry within the cache memory 26 so as to generate an output physical address PA [31:0] in the form of a 32-bit address. The virtual address VA is also supplied to prediction circuitry 22 where a determination is made as to whether or not the virtual address corresponds to a next page table entry rather than the current page table entry. If the virtual address VA received indicates that the next page of memory has been entered, then the prediction circuitry 22 triggers the next page table entry stored within the cache memory 26 to be transferred into the storage location of the current page table entry and then used for the virtual-to-physical address mapping to be performed by the access management circuitry 24.
The prediction circuitry 22 on detection that the next page table has been entered also serves to issue a request to fetch the next page table entry to be stored within the storage location for the next page table entry within the cache memory 26. This next page table entry may take many memory cycles to retrieve from the main memory 16, but this latency in returning the next page table entry is effectively hidden since the next page table entry will not be required for use until all the data corresponding to the current newly accessed page has been processed. Thus, the next page table entry is prefetched based upon a prediction of memory access requests which will require that next page table entry, but that have not yet been made or received by the memory management unit 12.
The prediction circuitry 22 also serves to detect when the virtual address VA received corresponding to a new page table triggers the fetching of the last page table within a current page directory entry. This indicates that the next page table entry to be fetched will correspond to a different page directory entry. Thus, the prediction circuitry 22 responds by waiting until the last page table entry of the current page directory entry has been fetched and then performs a move of the next page directory entry within the cache memory 26 to the storage position of the current page directory entry so that this is available for use as soon as another page boundary is crossed and the first page table entry for the new page directory entry is required. As part of the same process, the prediction circuitry 22 triggers the fetching of a new next page directory entry from the page table data 20 within the main memory 16 and this is returned to thenext page directory entry storage location within the cache memory 26.
As illustrated in Figure 7, when the next page table entry or the next page directory entry is returned, the permission data associated with these entries is passed to the access management circuitry 24 and stored therein. When these entries are actually first used, this permission data is checked to ensure that the relevant page table entry or page directory entry being accessed is a valid entry. If either of these is invalid and there is an attempt to use the entry, then a memory abort is triggered.
Figure 8 is a flow diagram schematically illustrating the operation of the prediction circuitry 22, the access management circuitry 24 and the cache memory 26 of Figure 7. It will be appreciated that the flow diagram of Figure 8 is necessarily linear in operation whereas those in this technical field will understand that many of the operations illustrated maybe performed in parallel or in a different order. Nevertheless, the overall control in Figure 8 may be used to form a state machine for controlling the operation of the various elements of Figure 7.
At step 28 the current and next page directory entries and the current and next page table entries are initialised within the cache memory 26 at the start of image processing.
These current and next page directory entries and current and next page table entries may be written into the cache memory 26 under software control or alternatively the memory accesses for the initial processing may be triggered resulting in cache misses within the cache memory 26 that in turn trigger the management data concerned to be fetched from the main memory 16 (using conventional cache miss mechanism that are not illustrated in Figure 7).
At step 30 the memory management unit 12 waits for a virtual address to be received. When a virtual address is received, step 32 determines whether a page boundary has been crossed. If no page boundary has been crossed, then step 34 utilises the access management circuitry 24 to generate a physical address using the current page table entry.
If a page boundary has been crossed, then processing proceeds to step 36 at which the next page table entry is moved to the current page table entry within the cache memory 26. Step 38 then determines whether or not the new current page table entry violates any permissions (e.g is the new current page table entry valid, is the privilege level correct etc). If there are any such violations, then processing proceeds to step 40 where a memory abort is triggered.
If the check at step 38 did not indicate any permission violations, then processing proceeds to step 42 at which there is determination of whether the new current page table entry is the last for the current page directory entry. If the new current page table entry is not the last for the current page directory entry, then the processing proceeds at step 44.
Step 44 predicts the virtual address of the new next page table entry and fetches this new next page table entry from the page table data 20 within the main memory 16. The prediction formed is based upon the linear increase of memory access address corresponding to the full raster scan of the frame buffer illustrated in Figure 4 (with an appropriate wrap at the end of a frame). The new next page table entry is thus identified and fetched into the cache memory 26 of the memory management unit 12 even though a memory request requiring that new next page table entry has yet to be generated by the graphics adapter 10.
After step 44 processing returns to step 34 where the current page table entry is used to generate the physical address PA. This current page table entry will have been updated at step 36 in the flow that passes through step 44.
If the determination at step 42 was that the new current page table entry is the last for the current page directory entry, then processing proceeds to step 46 where the next page directory entry is moved to the current page directory entry. Step 48 checks whether the new current page directory violates any permissions in a manner similar to step 38. If permissions are violated, then a memory abort is triggered at step 40. If permissions are not violated, then processing proceeds to step 50 at which a virtual address of a new next page directory entry is predicted and the new next page directory entry fetched from the page table data 20 within the main memory 16. The predictioned can again be based upon the predetermined memory access pattern corresponding to the full raster scan of Figure 4 with wrap.
The flow diagram of Figure 8 omits provision for the stopping of the fetching of data, for example, as would occur if switching to a blank output when driving a display. In this case, the next page directory entry or the next page table entry would not be fetched, the move of "next" to "current" performed as steps 36 or 46 would be prevented as a special case and aborts would not be triggered from steps 38 or 48. It will be appreciated by those in this technical field that this end of operation control can be handled in a variety of different way and the above is only an example outline of such control.
Claims (23)
- CLAIMSI. A memory management unit for managing memory accesses within a data processing apparatus, said memory management unit comprising: a cache memory for storing management data for managing data access requests, said management data being fetched from a management data memory and said cache memory storing a subset of said management data stored within said management data memory; access management circuitry responsive to a memory access request and said management data stored within said cache memory to generate a management response; and prediction circuitry for predicting required management data and for triggering fetching of said required management data from said management data memory to said cache memory in advance of receiving by said access management circuitry of a memory access request corresponding to said required management data.
- 2. A memory management unit as claimed in claim I, wherein said management data includes mapping data for mapping a virtual memory address specified by said memory access request to a physical memory address for addressing a main memory and said management response including generating said physical address.
- 3. A memory management unit as claimed in any one of claims I and 2, wherein said management data includes access permission data for controlling access to data corresponding to said memory access request and said management response includes generating an access control signal.
- 4. A memory management unit as claimed in any one of claims 1, 2 and 3, wherein said management data includes storage parameter data for controlling storage of data corresponding to said memory access request and said management response includes generating a storage control signal.
- 5. A memory management unit as claimed in any one of the preceding claims, wherein said memory management unit is coupled to graphics adaptor circuitry, memory access requests received from said graphics adaptor circuitry correspond to a raster scan access sequence of image data and said prediction circuitry predicts said required management data based upon continuation of said raster scan access sequence.
- 6. A memory management unit as claimed in claim 5, wherein said prediction circuitry predicts said memory access requests as having linearly increasing memory addresses within a frame buffer.
- 7. A memory management unit as claimed in claim 5, wherein said prediction circuitry predicts said memory access requests as having memory addresses starting from a specified line start address, increasing along a portion of a raster line to be accessed as specified by a line length, jumping to a start address of a next line spaced by a specified line pitch from said start address and repeating.
- 8. A memory management unit as claimed in any one of claims I to 4, wherein said memory access requests correspond to a linked list of data including pointer data pointing to memory addresses of next portions of said linked list and said prediction circuitry predicts said required management data based upon said pointer data read from received portions of said linked list.
- 9. A memory management unit as claimed in any one of the preceding claims, wherein said management data comprises two-level page table data in which management data for said memory access request is formed of a high-level page directory entry identifying a low-level page table, said page table entry specifying said mapping data for mapping said virtual memory address to said physical memory address.
- 10. A memory management unit as claimed in claim 9, wherein said cache memory stores a current page table entry and a predicted next page table entry.
- 11. A memory management unit as claimed in claim 10, wherein said cache memory does not any page table entries other than said current page table entry and said next pagetable entry.
- 12. A memory management unit as claimed in any one of claims 10 and II, wherein said prediction circuitry is responsive to a change in which page table entry is currently in use to trigger fetching of a new predicted next page table entry.
- 13. A memory management unit as claimed in any one of claims 10, 11 and 12, wherein said access management circuitry is responsive to a change in which page table entry is currently in use to trigger a check of access permissions for said changed current page table entry, said access management circuitry not performing any further check of access permission until a further change in current page table entry occurs.
- 14. A memory management unit as claimed in any one of claims 10 to 13, wherein said access management circuitry uses said current page table entry to provide said mapping data without a lookup of further data within said cache memory.
- 15. A memory management unit as claimed in any one of claims 10 to 14, wherein said cache memory stores a current page directory entry and a predicted next page directory entry.
- 16. A memory management unit as claimed in claim 15, wherein said cache memory does not any page directory entries other than said current page directory entry and said next page directory entry.
- 17. A memory as claimed in any one of the preceding claims, wherein said prediction circuitry predicts said required management data based upon a hardware generated prediction of memory addresses of future memory access requests.
- 18. A memory as claimed in any one of the claims I to 16, wherein said prediction circuitry predicts said required management data based upon a software generated prediction of memory addresses of future memory access requests.
- 19. A memory management unit as claimed in any one of the preceding claims, wherein said memory management unit is a dedicated memory management unit managing memory access requests from an associated source of memory access requests to a shared memory within data processing apparatus containing one or more further sources of memory access requests to said shared memory that are not managed by said dedicated memory management unit.
- 20. A memory management unit for managing memory accesses within a data processing apparatus, said memory management unit comprising: cache means for storing management data for managing data access requests, said management data being fetched from a management data memory means and said cache means storing a subset of said management data stored within said management data memory means; access management means for generating a management response in response to a memory access request and said management data stored within said cache memory; and prediction means for predicting required management data and for triggering fetching of said required management data from said management data memory means to said cache means in advance of receiving by said access management circuitry of a memory access request corresponding to said required management data.
- 21. A method of managing memory accesses within a data processing apparatus using a memory management unit, said method comprising the steps of: storing management data for managing data access requests within a cache memory, said management data being fetched from a management data memory and said cache memory storing a subset of said management data stored within said management data memory; generating a management response in response to a memory access request and said management data stored within said cache memory; predicting required management data; and triggering fetching of said required management data from said management data memory to said cache memory in advance of receiving of a memory access request corresponding to said required management data.
- 22. A memory management unit substantially as hereinbefore described with reference to the accompanying drawings.
- 23. A method of managing memory accesses substantially as hereinbefore described with reference to the accompanying drawings.
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| Application Number | Priority Date | Filing Date | Title |
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| GB0900748A GB2466981A (en) | 2009-01-16 | 2009-01-16 | Memory management unit with a dedicated cache memory for storing management data used to fetch requested data |
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| Application Number | Priority Date | Filing Date | Title |
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| GB0900748A GB2466981A (en) | 2009-01-16 | 2009-01-16 | Memory management unit with a dedicated cache memory for storing management data used to fetch requested data |
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| GB2466981A true GB2466981A (en) | 2010-07-21 |
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| GB0900748A Withdrawn GB2466981A (en) | 2009-01-16 | 2009-01-16 | Memory management unit with a dedicated cache memory for storing management data used to fetch requested data |
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| CN103927130B (en) * | 2014-03-14 | 2016-10-05 | 山东大学 | Based on external memory framework in the unification of memory management unit MMU |
| GB2545398A (en) * | 2015-12-08 | 2017-06-21 | Advanced Risc Mach Ltd | Data processing system |
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| KR101766833B1 (en) * | 2010-08-16 | 2017-08-09 | 에스프린팅솔루션 주식회사 | Image forming apparatus and method for transformation virtual memory address to physical memory address thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| GB0900748D0 (en) | 2009-03-04 |
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