GB2466283A

GB2466283A - Phase locked loop with controlled loop filter capacitance multiplier

Info

Publication number: GB2466283A
Application number: GB0823146A
Authority: GB
Inventors: John Paul Lesso
Original assignee: Wolfson Microelectronics PLC
Current assignee: Cirrus Logic International UK Ltd
Priority date: 2008-12-18
Filing date: 2008-12-18
Publication date: 2010-06-23
Also published as: GB0823146D0

Abstract

A phase locked loop (PLL) has an input 12, a phase detector 14, a charge pump 16, a loop filter 18 and a voltage controlled oscillator (VCO) 20 connected to the output 22 of the loop. The voltage controlled oscillator 20 is connected to variable divider 24 in the feedback path of the loop. The PLL is characterized in that a property of the loop filter 18, such as an effective capacitance value 30, is controlled based on a value of the controllable frequency division ratio. The capacitance value 30 may be scaled by a current mirror circuit (fig.3). The current mirror circuit may be controlled by a control signal derived from the frequency division ratio via a look up table 38. The invention achieves a reduction in the area required for the capacitor of the loop filter.

Description

PHASE LOCKED LOOP

This invention relates to a phase locked loop, and in particular to a phase locked loop with a controllable division ratio.

Phase locked loops are extremely common circuits, in which an input signal at one frequency is converted to an output signal at a different, higher, frequency.

The phase locked loop is based around a feedback loop, with the output signal being applied to a frequency divider in the feedback path, and the phase of the resulting signal being compared with the input signal, the feedback loop then tending to act such that the phase of the fed back signal becomes equal to the phase of the input signal.

The result is that the frequency of the output signal becomes equal to the frequency of the input signal, multiplied by the division ratio of the frequency divider in the feedback path.

In order to stabilize the feedback loop, it is necessary to include a filter in the feedforward path of the loop. In practice, it is often found that a capacitor in the loop filter occupies a not insignificant part of the physical area of the phase locked loop, when implemented in a semiconductor device, especially in the case of low noise phase locked loops. It would therefore be advantageous to be able to reduce the size of the loop filter capacitor, where this can be achieved without prejudicing the other operational properties of the phase locked loop.

According to a first aspect of the present invention, there is provided a phase locked loop, comprising: an input; a phase detector, having first and second inputs, wherein the first input of the phase detector is connected to the input of the phase locked loop; a feedforward path, including a charge pump, a loop filter and a voltage controlled oscillator, the feedforward path being connected to receive a signal from the phase detector, and the voltage controlled oscillator being connected to an output of the phase locked loop; and a feedback path, for receiving an output from the voltage controlled oscillator, and including a controllable frequency divider having a controllable frequency division ratio, an output of which is applied to the second input of the phase detector, wherein a property of the loop filter is controlled based on a value of the controllable frequency division ratio.

This has the advantage that a characteristic of the loop filter can be changed as required, in order to maintain a desirable operational property of the phase locked loop.

Preferably, the capacitance value of the capacitor can be controlled on the basis of the division ratio.

For a better understanding of the present invention, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:-Figure 1 is a schematic diagram of a phase locked loop in accordance with an aspect of the present invention; Figure 2 is a schematic diagram, showing in more detail a part of the circuit shown in Figure 1; and Figure 3 is a schematic diagram, showing in further detail a part of the circuit shown in Figure 2.

The invention will be described below with reference to its application in an otherwise conventional straightforward phase locked loop. However, it is equally applicable in other phase locked loop circuits that are provided with additional control circuitry. For example, the invention is applicable to a phase locked loop circuit of the type shown in US 2005/0281 367, which is herein incorporated by reference, in which the output signal is fed back through a second loop and compared with a reference clock signal, in order to generate an adjustable frequency division value. Further, the invention is applicable to a phase locked loop circuit in a clock synchroniser as shown in US 2005/0220240, which is herein incorporated by reference, in which data is clocked into a buffer using a received clock signal, while the phase locked loop is used to generate a local clock signal that is used to clock data out of the buffer, with a fill-level signal from the buffer being used to control the frequency of the local clock signal by varying the division ratio in the phase locked loop.

Figure 1 shows a phase locked loop (PLL) 10, having an input line 12 on which is received a signal at an input first frequency F1, connected to a first input terminal of a phase detector 14. The output signal from the phase detector 14 is applied to a feedforward path that contains a charge pump 16, a loop filter 18 and a voltage controlled oscillator (VCO) 20. The charge pump 16 receives the output from the phase detector 14, and the output from the charge pump 16 is passed through the loop filter 18 to the voltage controlled oscillator (VCO) 20. The output of the voltage controlled oscillator 20 is a signal at an output second frequency F2, which is passed to an output 22 of the phase locked loop 10.

The output from the voltage controlled oscillator 20 is also applied to a feedback path that comprises a frequency divider 24. The frequency divider 24 has a frequency division ratio N, such that the output of the frequency divider 24 is a signal at a frequency F2/N.

The output of the frequency divider at the frequency F2/N is fed to a second input terminal of the phase detector 14.

As is well known, the loop then operates to bring the frequencies of the two inputs of the phase detector 14 together. That is, when the frequency F2IN is less than the input first frequency F1, a positive output is generated in the phase detector 14, which controls the charge pump 16, such that it increases the amount of charge that is applied to the loop filter 18, which causes an increased voltage to be applied to the voltage controlled oscillator 20, causing the frequency F2 to increase. Conversely, when the frequency F2/N is higher than the input first frequency F1, a negative output is generated in the phase detector 14, and this eventually causes a reduced voltage to be applied to the voltage controlled oscillator 20, causing the frequency F2 to decrease.

When the loop has reached a stable operating condition, the frequencies of the two signals at the inputs of the phase detector 14 are equal, i.e. F2/N = F1, and therefore F2 = N.F1, that is, the frequency of the output signal becomes equal to the frequency of the input signal, multiplied by the division ratio of the frequency divider in the feedback path.

As shown in Figure 1, the loop filter 18 comprises a combination of a first capacitor 26, having a capacitance value C, in parallel with a series circuit including a resistor 28 having a resistance value R1 and a second capacitance 30 having a variable capacitance value. As further shown in Figure 1, the second capacitance 30 is formed from a third capacitor 32, having a capacitance value C3, in parallel with a current mirror circuit 34.

Figure 2 is a more detailed circuit diagram of the current mirror circuit 34, which is of a type that is generally understood, and which will therefore not be described further, except as required for an understanding of the present invention. Specifically, a pair of MOS transistors 34, 342 have their gates connected together, to form a current mirror, with the current l through the first of these transistors 34 being applied to a further MOS transistor Ml, and with the current through the second of these transistors 342 being applied to a second further MOS transistor M3. The magnitude of this current through the second of the paired transistors 342 is determined by a scaling ratio, that is itself determined by the properties of the second further MOS transistor M3.

In addition, the scaling ratio is controllable in this embodiment of the invention, with Figure 3 showing in more detail the form of the controllable MOS transistor M3. In fact, as shown in Figure 3, in this embodiment, the controllable MOS transistor M3 is formed from multiple MOS transistors M31, ..., M3N, which are connected to ground through respective switches S, ..., SN. These switches are controlled by an input signal 34.

That is, the switches S, ..., SN can be opened or closed, and only those MOS transistors M31, ..., M3N, which are connected to ground through closed switches S1, SN are active in the circuit. For example, the MOS transistors M31, ..., M3N could all have the same width/length ratio, so that the overall size of the transistor M3 is determined simply by the number of switches that are closed, or the MOS transistors M31, ..., M3N could be binary weighted, allowing a wider range of overall sizes to be achieved from the same number of transistors. Thus, depending on which of the switches S1, ..., SN are closed, the scaling ratio can be controlled, in order to achieve a desired gain value for the current mirror circuit 34.

Based on the input signal 34, the current mirror circuit 34 has a gain value G, and so the effect of the current mirror circuit 34 is to multiply the capacitance value C3 of the third capacitor 32 by (1 + C), so that the effective capacitance value C2 of the second capacitance 30 is equal to (1+G)C3.

The frequency divider 24 is controllable. That is, the division ratio N is supplied to the frequency divider 24 on an input 36, and the supplied value is used by the frequency divider 24 to divide the frequency F2 of the output signal.

In addition, the scaling ratio of the current mirror circuit 34, and hence the effective capacitance value in the loop filter 18, are also controllable on the basis of the division ratio N. In this illustrated embodiment, the division ratio N. is supplied to a look up table 38, which also receives a selection input on an input terminal 40, and used to select a value for the signal 34 that is input to the current mirror circuit 34, in order to achieve a gain value G, as described above.

The value of N is thus used to select a value of G, which is in turn used to control the effective capacitance in the loop filter 18.

In addition, while it is possible that the value of N could be used automatically to derive the value of C, in this embodiment of the invention the selection input to the input terminal 40 of the look up table 38 can be used to select between two or more available values for G, for any given value of N. It will be apparent that, although Figure 1 shows the use of the look-up table 38, there are many other ways in which a control signal for the current mirror circuit 34 can be derived directly or indirectly from the division ratio N, or conversely in which a control signal to vary the value of N could be derived from a desired control signal for the current mirror circuit 38, so that the division ratio and the properties of the loop filter are controlled together.

It will also be apparent that, although in the illustrated embodiment a current mirror circuit is used to achieve control of the effective capacitance value, this can be arranged in other ways.

It will also be noted that, although in the illustrated embodiment it is the effective value of capacitance in the loop filter that is controlled to vary the properties of the loop filter, this variation can be achieved in other ways. For example, the effective value of resistance in the loop filter could be varied to control the properties of the loop filter.

In the illustrated embodiment, the look up table 38 can be used so that, for any given value of N, a value of G is supplied, that gives the phase locked loop any desired property.

For example, it is known that the operating bandwidth of a phase locked loop is given, to a first order approximation, by: /KPDKVCO \! N.C2 where w is the bandwidth, KPD is the gain of the phase detector 14, Ko is the gain of the voltage controlled oscillator 20, N is the division ratio, and C2 is the effective capacitance of the loop filter, as described above.

It can therefore be seen that the bandwidth varies as a function of the division ratio, N. In order to maintain a constant bandwidth as N varies, the circuit shown in Figure 1 makes it possible to vary the effective capacitance C2 with N. For example, in order to maintain the bandwidth constant at a value w, the effective capacitance C2 can be set equal to: c KPDKVCO 2= Since C2 = (1-'-G)C3, as discussed above, this means a constant operating bandwidth can be achieved if G is controlled on the basis of N, such that:

-

Thus, by storing this function in the look up table 38, the desired property can be maintained.

In addition, it is known that the stability is approximated by: RC2o where w is the bandwidth, R28 is the resistance value of the resistor 28, and C2 is the effective capacitance of the loop filter, as described above.

Since the bandwidth varies as a function of the division ratio, N, it can therefore be seen that the stability also varies as a function of the division ratio, N. In order to maintain a constant stability as N varies, the circuit shown in Figure 1 makes it possible to vary the effective capacitance C2 with N. For example, in order to maintain the stability constant at a value,, using the approximation for w given above, the effective capacitance C2 can be set equal to: 4..N c2= R28 XPDKVCO Since C2 = (1+G)C3, as discussed above, this means a constant stability can be achieved if G is controlled on the basis of N, such that: G= 2 -1 R28.K PDK VCO Thus, by storing this function in the look up table 38, the desired property can be maintained.

Thus, two different functions have been described above, whereby an input value of N can be used by the lookup table 38 to generate an output value of G that, when applied to the current mirror 34, causes the phase locked loop to have some desirable operating property. Other functions are also possible. For example, it will be noted that maintaining the bandwidth constant causes the stability to vary, and vice versa, so it would be possible to store a compromise function whereby the stability and bandwidth both vary by reduced amounts.

Where more than one function is stored in the lookup table 38, the selection input 40 can be used to determine which function is accessed.

Clearly, other functions are possible, depending on the exact form of the phase locked loop, and the loop filter, and in particular on the exact way in which the capacitance of the loop filter is controlled.

There is therefore described a phase locked loop circuit with a variable frequency division ratio, in which at least one operating property of the phase locked loop circuit can be controlled in a desirable way, by controlling an effective capacitance within the loop filter on the basis of the variable frequency division ratio.

Although embodiments of the present invention have been described in the preceding paragraphs with reference to various examples, it should be appreciated that modifications can be made without departing from the scope of the invention as claimed.

While the words "a", "an" and the like are used herein, it should be noted that the use of a singular word does not exclude a plural meaning, and vice versa.

It will be noted that a phase locked loop as described herein can be implemented in many different forms, and can be used in many different types of device, for example in frequency generator circuits in portable and non-portable electronic apparatus and systems.

For example, the phase locked loop as described herein can be used in audio processing circuitry, where it is required to generate a clock signal at one frequency in order to be able to encode or decode digital signals at a particular sampling rate, and where the device already includes a clock that generates signals at a different frequency.

Whilst endeavouring in the foregoing specification to draw attention to draw attention to those features of the invention believed to be of particular importance, it should be understood that the applicant claims protection in respect of any patentable feature or combination of features hereinbefore referred to and/or shown in the drawings whether or not particular emphasis has been placed thereon.

Claims

CLAIMS1. A phase locked loop, comprising: an input; a phase detector, having first and second inputs, wherein the first input of the phase detector is connected to the input of the phase locked loop; a feedforward path, including a charge pump, a loop filter and a voltage controlled oscillator, the feedforward path being connected to receive a signal from the phase detector, and the voltage controlled oscillator being connected to an output of the phase locked loop; and a feedback path, for receiving an output from the voltage controlled oscillator, and including a controllable frequency divider having a controllable frequency division ratio, an output of which is applied to the second input of the phase detector, wherein a property of the loop filter is controlled based on a value of the controllable frequency division ratio.
2. A phase locked loop as claimed in claim 1, wherein the property of the loop filter, controlled based on a value of the controllable frequency division ratio, is a value of a capacitance in the loop filter.
3. A phase locked loop as claimed in claim 2, wherein the loop filter is a low pass filter, a bandwidth of which is determined by the value of the capacitance.
4. A phase locked loop as claimed in claim 2, wherein the loop filter comprises a series connection of a first capacitance and a resistor, and wherein the value of the first capacitance is controlled based on the value of the controllable frequency division ratio.
5. A phase locked loop as claimed in claim 1, further comprising a lookup table, for receiving the value of the controllable frequency division ratio as an input value, and supplying a corresponding loop filter control value as an output.
6. A phase locked loop as claimed in claim 4, wherein the lookup table has a selection input, for selecting between a plurality of loop filter control values corresponding to the received value of the controllable frequency division ratio.
7. A phase locked loop as claimed in claim 1, wherein the loop filter comprises a capacitor and a controllable current mirror circuit, connected together such that an effective capacitance of the capacitor and the current mirror circuit is equal to a capacitance value of the capacitor multiplied by a gain value, and wherein the gain value is controlled based on the value of the controllable frequency division ratio.
8. A phase locked loop, comprising a controllable loop filter, and having a controllable frequency division ratio in a feedback path, wherein the controllable loop filter is controlled based on the controllable frequency division ratio.
9. A phase locked loop as claimed in claim 8, wherein the controllable loop filter comprises a capacitance having a controllable capacitance value.
10. A frequency generator, comprising: an input for receiving a signal having a first frequency; and a phase locked loop for receiving the signal having the first frequency, and for generating an output signal having a second frequency, wherein the phase locked loop comprises: a phase detector, having first and second inputs, wherein the first input of the phase detector is connected to receive the signal having the first frequency; a feedforward path, including a charge pump, a loop filter and a voltage controlled oscillator, the feedforward path being connected to receive a signal from the phase detector, and the voltage controlled oscillator being connected to an output of the phase locked loop; and a feedback path, for receiving an output from the voltage controlled oscillator, and including a controllable frequency divider having a controllable frequency division ratio, an output of which is applied to the second input of the phase detector, wherein a property of the loop filter is controlled based on a value of the controllable frequency division ratio.
11. An electronic device, comprising a frequency generator as claimed in claim 10.
12. A portable electronic device, as claimed in claim 11.
13. An audio processing device, as claimed in claim 11.