GB2460747B - Optimizing concurrent acccesses in a directory-based coherency protocol - Google Patents

Optimizing concurrent acccesses in a directory-based coherency protocol

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Publication number
GB2460747B
GB2460747B GB0909592A GB0909592A GB2460747B GB 2460747 B GB2460747 B GB 2460747B GB 0909592 A GB0909592 A GB 0909592A GB 0909592 A GB0909592 A GB 0909592A GB 2460747 B GB2460747 B GB 2460747B
Authority
GB
United Kingdom
Prior art keywords
directory
coherency protocol
acccesses
concurrent
based coherency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0909592A
Other versions
GB2460747A (en
GB0909592D0 (en
Inventor
Hariharan Thantry
Akhilesh Kumar
Seungjoon Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0909592D0 publication Critical patent/GB0909592D0/en
Publication of GB2460747A publication Critical patent/GB2460747A/en
Application granted granted Critical
Publication of GB2460747B publication Critical patent/GB2460747B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.
GB0909592A 2008-06-13 2009-06-04 Optimizing concurrent acccesses in a directory-based coherency protocol Active GB2460747B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/157,792 US8190820B2 (en) 2008-06-13 2008-06-13 Optimizing concurrent accesses in a directory-based coherency protocol

Publications (3)

Publication Number Publication Date
GB0909592D0 GB0909592D0 (en) 2009-07-15
GB2460747A GB2460747A (en) 2009-12-16
GB2460747B true GB2460747B (en) 2010-08-04

Family

ID=40902559

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0909592A Active GB2460747B (en) 2008-06-13 2009-06-04 Optimizing concurrent acccesses in a directory-based coherency protocol

Country Status (6)

Country Link
US (1) US8190820B2 (en)
JP (1) JP5037566B2 (en)
CN (1) CN101604295B (en)
DE (1) DE102009023898B4 (en)
GB (1) GB2460747B (en)
TW (1) TWI416322B (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8180963B2 (en) * 2009-05-21 2012-05-15 Empire Technology Development Llc Hierarchical read-combining local memories
US8468309B2 (en) 2010-09-25 2013-06-18 Intel Corporation Optimized ring protocols and techniques
JP5772458B2 (en) * 2011-09-29 2015-09-02 富士通株式会社 Data management program, node, and distributed database system
US9280468B2 (en) * 2011-10-26 2016-03-08 Qualcomm Technologies, Inc. Three channel cache-coherency socket protocol
EP2786257A4 (en) * 2011-11-29 2015-06-10 Intel Corp Ring protocol for low latency interconnect switch
US9910807B2 (en) 2011-11-29 2018-03-06 Intel Corporation Ring protocol for low latency interconnect switch
JP5643903B2 (en) * 2011-12-23 2014-12-17 インテル・コーポレーション Method and apparatus for efficient communication between caches in a hierarchical cache design
US9235524B1 (en) 2011-12-30 2016-01-12 Emc Corporation System and method for improving cache performance
US9009416B1 (en) * 2011-12-30 2015-04-14 Emc Corporation System and method for managing cache system content directories
US9104529B1 (en) * 2011-12-30 2015-08-11 Emc Corporation System and method for copying a cache system
US8627012B1 (en) 2011-12-30 2014-01-07 Emc Corporation System and method for improving cache performance
US8930947B1 (en) 2011-12-30 2015-01-06 Emc Corporation System and method for live migration of a virtual machine with dedicated cache
US9053033B1 (en) * 2011-12-30 2015-06-09 Emc Corporation System and method for cache content sharing
US9158578B1 (en) 2011-12-30 2015-10-13 Emc Corporation System and method for migrating virtual machines
US9135177B2 (en) 2013-02-26 2015-09-15 Apple Inc. Scheme to escalate requests with address conflicts
US9304926B2 (en) 2013-07-23 2016-04-05 Arm Limited Coherency control message flow
US9785556B2 (en) * 2014-12-23 2017-10-10 Intel Corporation Cross-die interface snoop or global observation message ordering
CN106326183B (en) * 2015-06-30 2019-03-15 龙芯中科技术有限公司 The implementation method and device of buffer consistency based on catalogue
US10387314B2 (en) * 2015-08-25 2019-08-20 Oracle International Corporation Reducing cache coherence directory bandwidth by aggregating victimization requests
US10095595B2 (en) 2015-11-17 2018-10-09 International Business Machines Corporation Instant recovery in a multi-grained caching framework
US9965390B2 (en) 2015-11-17 2018-05-08 International Business Machines Corporation Reducing defragmentation in a multi-grained writeback cache
US9971692B2 (en) 2015-11-17 2018-05-15 International Business Machines Corporation Supporting concurrent operations at fine granularity in a caching framework
US9817757B2 (en) 2015-11-17 2017-11-14 International Business Machines Corporation Scalable metadata management in a multi-grained caching framework
US9916249B2 (en) 2015-11-17 2018-03-13 International Business Machines Corporation Space allocation in a multi-grained writeback cache
US10152417B2 (en) * 2016-04-11 2018-12-11 International Business Machines Corporation Early freeing of a snoop machine of a data processing system prior to completion of snoop processing for an interconnect operation
US10733103B2 (en) 2017-12-13 2020-08-04 International Business Machines Corporation Non-blocking directory-based cache coherence
US11544193B2 (en) 2020-09-11 2023-01-03 Apple Inc. Scalable cache coherency protocol
CN112579479B (en) * 2020-12-07 2022-07-08 成都海光微电子技术有限公司 Processor and method for maintaining transaction order while maintaining cache coherency
US11934313B2 (en) 2021-08-23 2024-03-19 Apple Inc. Scalable system on a chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426681A (en) * 1980-01-22 1984-01-17 Cii Honeywell Bull Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory
US5737759A (en) * 1995-12-06 1998-04-07 Intel Corporation Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5832276A (en) * 1996-10-07 1998-11-03 International Business Machines Corporation Resolving processor and system bus address collision in a high-level cache
US6065101A (en) * 1997-06-12 2000-05-16 International Business Machines Corporation Pipelined snooping of multiple L1 cache lines
US20090113139A1 (en) * 2007-10-31 2009-04-30 Bharadwaj Pudipeddi Avoiding snoop response dependency

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5878213A (en) * 1996-02-15 1999-03-02 International Business Machines Corporation Methods, systems and computer program products for the synchronization of time coherent caching system
US5897657A (en) * 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessing system employing a coherency protocol including a reply count
US6122719A (en) * 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
FI108502B (en) * 1998-12-11 2002-01-31 Nokia Corp Procedure and apparatus for transmitting a short message
US20040103248A1 (en) * 2002-10-08 2004-05-27 Hass David T. Advanced telecommunications processor
US7461213B2 (en) * 2002-10-08 2008-12-02 Rmi Corporation Advanced processor system using request, data, snoop, and response rings
US6922756B2 (en) * 2002-12-19 2005-07-26 Intel Corporation Forward state for use in cache coherency in a multiprocessor system
US7917646B2 (en) * 2002-12-19 2011-03-29 Intel Corporation Speculative distributed conflict resolution for a cache coherency protocol
JP4658064B2 (en) 2003-10-22 2011-03-23 インテル コーポレイション Method and apparatus for efficient sequence preservation in interconnected networks
JP4085389B2 (en) * 2003-12-24 2008-05-14 日本電気株式会社 Multiprocessor system, consistency control device and consistency control method in multiprocessor system
US7856534B2 (en) * 2004-01-15 2010-12-21 Hewlett-Packard Development Company, L.P. Transaction references for requests in a multi-processor network
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
EP1782244A4 (en) * 2004-07-07 2010-01-20 Emc Corp Systems and methods for providing distributed cache coherence
US7454576B2 (en) * 2004-12-27 2008-11-18 Intel Corporation System and method for cache coherency in a cache with different cache location lengths
US7406566B2 (en) * 2005-06-03 2008-07-29 Intel Corporation Ring interconnect with multiple coherence networks
US7437518B2 (en) * 2005-09-07 2008-10-14 Intel Corporation Hiding conflict, coherence completion and transaction ID elements of a coherence protocol
US8010753B2 (en) * 2005-09-28 2011-08-30 International Business Machines Corporation Systems and methods for temporarily transferring use of portions of partitioned memory between host computers
US7747897B2 (en) * 2005-11-18 2010-06-29 Intel Corporation Method and apparatus for lockstep processing on a fixed-latency interconnect
US7962694B2 (en) * 2006-03-31 2011-06-14 Intel Corporation Partial way hint line replacement algorithm for a snoop filter
US20080005486A1 (en) * 2006-06-29 2008-01-03 Mannava Phanindra K Coordination of snoop responses in a multi-processor system
US8301790B2 (en) * 2007-05-30 2012-10-30 Randy Morrison Synchronization of audio and video signals from remote sources over the internet
JP2009245323A (en) * 2008-03-31 2009-10-22 Nec Computertechno Ltd System and method for reducing latency

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426681A (en) * 1980-01-22 1984-01-17 Cii Honeywell Bull Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory
US5737759A (en) * 1995-12-06 1998-04-07 Intel Corporation Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5832276A (en) * 1996-10-07 1998-11-03 International Business Machines Corporation Resolving processor and system bus address collision in a high-level cache
US6065101A (en) * 1997-06-12 2000-05-16 International Business Machines Corporation Pipelined snooping of multiple L1 cache lines
US20090113139A1 (en) * 2007-10-31 2009-04-30 Bharadwaj Pudipeddi Avoiding snoop response dependency

Also Published As

Publication number Publication date
DE102009023898B4 (en) 2020-06-18
US8190820B2 (en) 2012-05-29
DE102009023898A1 (en) 2009-12-31
CN101604295A (en) 2009-12-16
CN101604295B (en) 2013-03-27
JP5037566B2 (en) 2012-09-26
TWI416322B (en) 2013-11-21
TW201011536A (en) 2010-03-16
GB2460747A (en) 2009-12-16
GB0909592D0 (en) 2009-07-15
JP2009301552A (en) 2009-12-24
US20090313435A1 (en) 2009-12-17

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