GB2457037A - Improved clocked sampling comparator for ADCs - Google Patents

Abstract

A regenerative clocked sampling circuit is described which combines the action of sampling with regeneration. The comparator uses a single clocking signal to switch the circuit between a tracking phase in which the state tracks the input signal, and a bistable phase during which the state rapidly approaches one of two states dependant on the input signal. The same clock signal also isolates the bistable circuit from the input signal source. In a preferred embodiment, these two actions are performed by the same transmission gate or gates connecting the input to the potentially bistable circuit.

Description

"Improved Clocked Sampling Comparator for Analogue to Digital Converters"

Background

This invention relates to improved sampling comparators for use in analogue to digital converters which permit higher sampling frequencies.

All digital to analogue converters require the comparison of a signal with at least one reference signal at specified sampling instants, usually at regular timing intervals, to produce a digital signal. For example, in Flash" converters a multiplicity of such sampling converters simultaneously compare the signal at the sampling time with a multiplicity of reference signals which are normally uniformly spaced over the permitted range of signal values. The digital outputs of this multiplicity of comparators are then stored in a register at a time determined by a sampling clock pulse. Combinational logic then converts this set of digital signals to a digital binary word for subsequent digital signal processing, storage or communications. in successive approximation converters, the input signal is sampled and held as an analogue signal in a stored by an analogue means, known as a sample hold or track/store, is compared repeatedly with a reference signal obtained from a digital to analogue converter whose input derives from register as the bits in the register are adjusted one bit at a time to produce the digital output word. Delta sigma converters usually comprise a sampling comparator producing a stream of binary pulses, at well over the Nyquist rate, whose input conies froni the output of a linear loop filter whose input is the difference between the input signal and the said sampling comparator output pulse stream. This forms a non-linear feedback ioop which adjusts the pulse stream so that it matches the input signal over the pass-band of the loop filter. The digital output of the converter is obtained by decimation of the sampling comparator output bit stream by a digital filter. The comparator output bit stream has conceptually been passed through a I bit digital to analogue converter, the accuracy of which, i.e. the consistency of the pulse amplitudes, limits the overall converter accuracy. Clearly also, accuracy is enhanced by increasing the ioop gain over the signal bandwidth, and by maximizing the over-sampling rate. In all analogue to digital converters, the sampling rate and accuracy of a sampling converter are a key factors in determining the performance of the converter.

Prior Art

The usual means of implementing sampling comparators is to use some kind of high gain amplifier whose output saturates at signal levels within the voltage range accepted by logic circuits as either "1" or "0". The minimum gain of such samplers is determined by the Page 1 requirement that some minimum signal lcvcl will cause the output to reach its saturated level to a specified accuracy within a specified time. Such a circuit must be preceded or possibly, as in Flash converters, followed by some sampling and storage means to define the sampling instant and ensure that the output is held at a constant value long enough for it to have finished being used by the subsequent circuitry. Figure I shows a typical circuit of such a Sample Hold. The analogue accuracy of the digital output signal depends on the type of converter. In cases of flash converters the accuracy had only to be adequate to prevent ambiguity about whether the output is a "I" or a "0". In the case of a successive approximation converter, variation in the comparator output voltage could cause sonic variation in the signal presented to the successive stage.

resulting to erroi-s. However these problems are small compared to that encountered in a sigma delta converter in which the output of the comparator which comprises the (digital) output bit So stream is in fact also the (analogue) feedback signal compared with the input within the feedback loop. This can easily be the limiting factor in the performance of the converter, particularly at high sampling speeds. However the usc of high gain multi-stage amplification required for this, causes its own problems: apart from the tendency to high frequency instability of high gain multi-stage amplifiers, the delay, silicon area and probably more importantly, power consumption increase in proportion to the number of stages.

Instead of achieving the high gain required by means of a multi-stage amplifier, positive feedback may he used as in the conventional Schmitt trigger circuit as in Figure 2. Such a prior art circuit to achieve this is shown in figure 2 from the classic textbook "CMOS Analogue Circuit Design" by P.E. Allen and DR. Holberg (ISBN 0-03-006587-9). These have a transfer characteristic which displays hysteresis which, unless ii. is very small, this can causes errors and compromise performance. Such small amounts of hysteresis require a loop gain which very accurately equal to -I The fact that the input signal is still connected to the histable circuit could still have some effect on the output signal. A better solution is to combine the action of sampling with regeneration in a clocked regenerative sampler. Clocked samplers, in fact, unlike Schmitt triggers, have no requirement to minimize the hysteresis in the interests of accuracy. In fact the larger the better as the last thing one wishes is for the state to change in the middle of being used by other circuits! Since the regenerative circuit rapidly approaches an attractor which would normally be a constant signal value (voltage or current), it would be unlikely to be affected by smaller, parasitic, feedback paths in the way that a high gain cascaded amplifier would, and would act as a discrete time system. The circuit in Figure 2 could be made to perform in such a manner if the clock pulse were applied to point I 1 to turn the circuit on and off in stead of the constant bias assumed in the text. However the ioop gain achievable by this circuit is fairly low, as is indeed desirable in a Schmitt trigger to enable the circuit to be reset to the other state without and unnecessarily large dead band. Another disadvantage of this circuit is that the response of the circuit is rather slow, both due to the low loop gain, and also by the slow action of the P channel devices in the current mirrors which provide the cross coupling to effect the Page2 negative resistance load on the comparator transistors connected to the input, and the higher the gain of the mirrors, the slower are their open loop response.

For these reasons most sampled regenerative comparators use the simpler, faster, and higher loop gain histahie using two n channel devices with the bases of each connected to the collectors of the other, as with the cross connected CMOS inverters 108 and 109 in the otherwise somewhat complex prior art circuit in figure 3 from US Patent no 6037890A1. With this clocking is provided primarily by turning on the bistable by means of transistor 102 while making simultaneous changes to the conduction states of 101, 103, 106 and 107.

A similar, and somewhat simplified and improved sampled regenerative comparator is shown in Figure 4 from US patent application 2005242844 by John B. Hughes filed by Koninklije Philips NV. In this, as in the previous case, the input signal is a current rather than a voltage. The sampling instant is primarily determined by the opening of gate 36 which has up till then been short circuiting the drains 32 and 34. In a real circuit, gate 36, when conducting, has a finite resistance which determines the effective transconductance gain of the circuit while in the stable state. When the gate opens, the circuit becomes bistable and whichever gate is more positive to take to the positive rail and the other to the negative rail. However, the input would still he connected to the bistable throughout the regenerative phase were it not for the actions of gales 50, 54 and 60, which would not only cause "kick hack" of the transient to the input being sampled. hut also, not mentioned in the patent, small variations in the output voltage in the presence of large input signals. Much of the patent concerns the complexities and compromises involved in the liming of these various gates.

Drawings

Figure 1 shows a prior art sample hold circuit.

Figure 2 shows a prior art Schmitt trigger regenerative comparator.

Figure 3 shows another prior art clocked regenerative comparator Figure 4 shows a further improved prior art clocked regenerative comparator Figure 5 shows a conceptual block diagram to illustrate the invention and differentiate from

prior art.

Figure 6 shows a schematic diagram of an idealized preferred embodiment of the invention Figure 7 shows a block diagram of a preferred embodiment of the invention

Description

Figure 5 shows a conceptual block diagrani which illustrates a wide class of regenerative clocked samplers to which the invention belongs as well as the prior art mentioned above. An Page3 amplifying means 15 can receive its input from an external input 13 which is usually differential but for clarity shown here as a single signal, via some gating means 18. It may also receive a regenerative from its own output signal 16, again frequently differential, via another gating means 17. Amplifying means 15 will possess memory whereby its output will not change the instant it receives no input, in practice usually due to the effect of gate capacitance. Prior art clocked regenerative samplers function in two different ways: In the first signal 13 is enabled until the sampling instant followed after some interval of time by the enabling of the regenerative signal 16. In this case the action of gate 18 is that of a sample/hold as illustrated in figure 1, which is followed by regenerative amplification. The other way they operate is described in detail in the prior art from which Figure 4 is taken. In this the sampling instant is defined as that at which regeneration is enabled by removing the short circuit effected by 30.

which has the effect of 17 in figure 5. The input is then removed by 13 to prevent subsequent variations of input signal affecting the output 16. It is observed that the criterion for loop stability depends the finite on the ratio of the on conductance of 30 to the transconductance of the amplifying transistors. What is not observed is that in fact there may be benefits in terms of increasing Sensitivity and speed in 30 not acting as a perfect short circuit. This is because the voltage on the gates of the active transistors, effectively the input to 15, is enhanced by the effect of some positive feedback prior to histability. Upon the transition to histahility, these gate voltages act as initial condition to the initially exponential growth. This means that an amount proportional to the logarithm of this initial condition is in tict added to the settlement time of the comparator output.

What is taught herein is a two phase clocked regenerative sampling comparator comprising amplifying means and regeneration means controllable by a clocking signal, wherein the sampling is effected by the transition from loop gain of a designed amount below unity to one above unity. In the one phase, the tracking phase, the output state varies approximately linearly with the input signal, and in the other, the histahle phase, the output state approaches one of two limiting output values dependant on the state at the start of the phase.

A schematic diagram of a preferred embodiment of the invention is shown in figure 6 wherein is an input signal source, 23 is a non-inverting transconductance amplifier, 24 a resistive load, 22 an ideal transmission gate means, 21 a series resistance comprising the on resistance of transmission gate 22 and internal resistance of signal source 20. 1 the value of 21 is R1 and that ISO of 24, R and the transconductance of 23, g1. the condition for stability when the transmission gate 22 conducts is that g< hR1 +l/R2 when 22 becomes open circuit then obviously the criterion for stability is that Page4

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g < hR2 or conversely if Xm> hR2 then the output will grow exponentially from its initial condition till the output voltage nears one of two limiting values. It is thus apparent that when stopping conduction transmission gate 20 performs three functions simultaneously and in a fast and predictable manner, i.e. 1. It defines the sampling instant by increasing the loop gain 2. It prevents the input from having any further effect on the state of the bistable 3. It prevents the kick-back" effects of the state transition of the histable by isolating it from the input. It does this without the need for a further gate to short circuit the signal input, as is done by 60 in Figure 4, relying instead on the low impedance of the signal source.

he loop gain is varied by a clock signal so that before the clock transition the loop gain is below unity, hut after the transition it is above unity making the circuit become bistable, i.e., having two stable attractors. This means that if the signal exceeds the reference signal, the circuit state rapidly moves to one attractor, and if vice versa, to the other.

When this phase ends, and the circuit returns to the stable amplifying state, the circuit will take some time for the transient to subside and this obviously provides a minimum duration for this phase without which accuracy would he compromised for the next sample.

Although to simplify the explanation Figure 6 shows the embodiment drawn as if it use a single ended signal path, in fact in real life there are many benefits for using symmetrical differential I 80 circuits, and one such embodiment is illustrated in figure 7.

A preferred embodiment of the invention in a real application is shown in figure 7, wherein: 9 is the positive supply rail, 204 and 205 are transistors forming the basic bistable element, 203 and 204 are transmission gates connecting the differential input voltages 200 and 201 to the bistable, 1 85 such that when connected via the transmission gates 204 and 205, act as a stable somewhat regenerative differential amplifier. This requires that the impedance of the signal source has a sufficiently low impedance. Transistors 205 and 206 act as cascode amplifiers which, together with the source followers they drive, provide isolation from the following stage. 213 to 218 are loads which may be resistive or active circuits such as complementary MOS transistors. The action of this following circuit is as follows: A pulse is supplied at 212 which turns transistor 216 on for a short lime which finishes at or before the time the sampler changes from the histable phase to the tracking phase. 209 and 210 act as a differential gate which routes this current pulse to either 217 or 218 depending on which of signals 204 and 203 is the larger. PageS

Claims (5)

1. A two phase clocked regenerative sampling comparator comprising amplifying nieans and regeneration means controllable by a clocking signal, wherein the sampling is effected by the transition from loop gain of a designed amount below unity iii the first phase to one above unity in the second phase while simultaneously isolating the input signal.

2. A comparator according to claim I wherein the control of the regeneration is effected by the loading of the amplifying means by the connection of the input during the first phase.

3. A comparator according to either of the previous claims wherein the connection of the input signal is effected by one or more transmission gates.

205

4. A comparator according to any of the above claims wherein the transmission gate is a MOS transistor or pair of complementary MOS transistors with appropriate signals applied to the gates.

5. A clocked regenerative comparator substantially as herein described and illustrated in Figures 5, 6 or 7 of the accompanying drawings. Page6