GB2456624A - Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value. - Google Patents
Checking Arithmetic operations using residue modulo generation by applying the modulo operations of the prime factors of the checking value. Download PDFInfo
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- GB2456624A GB2456624A GB0822772A GB0822772A GB2456624A GB 2456624 A GB2456624 A GB 2456624A GB 0822772 A GB0822772 A GB 0822772A GB 0822772 A GB0822772 A GB 0822772A GB 2456624 A GB2456624 A GB 2456624A
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- 238000012937 correction Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000010606 normalization Methods 0.000 description 2
- 239000013598 vector Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/721—Modular inversion, reciprocal or quotient calculation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
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Abstract
Disclosed is a method and an apparatus using residue modulo checking for arithmetic operations. To get a high Modulo m and thus a high residue modulo checking coverage within a checking flow 31, at least two modulo operations 32, 33 are separately applied in parallel, a first Modulo q0 operation and at least one second Modulo qn operation, where q0, q1, q2,... qn-1, qn, are different primes with m=q0*q1*q2*. . .*qn-1*qn. The checking is done by comparing the residue modulo of the result of an arithmetic operation 36 with the results of the modulo operations on the inputs of the arithmetic operation 35. The modulo operations may be provided by a modulo decode for the modulos applied in the parallel flows or by providing a modulo shift table. The values of m may be 15 or 255 and the values of q may be 3 and 5 or 3, 5 and 17, respectfully.
Description
2456624
DESCRIPTION
Method and apparatus for residue modulo checking for arithmetic operations
Technical field
The present invention relates to residue modulo generation and error detection within a floating-point unit of a microprocessor. More particularly the invention relates to a residue modulo generating and error detecting apparatus on floating-point operations, which may be addition, subtraction, multiplication, divide, square root, convert.
Background of the invention
A floating-point unit of a microprocessor comprises a residue modulo generating and error-detecting apparatus, which performs residue modulo checking for arithmetic floating-point operations, like e.g. addition, subtraction, multiplication, divide, square root or convert operations, for error detection. Thereby a Modulo m, e.g. residue Modulo3 or residue Modulo5 or residue Modulol5, is used for error checking within a checking flow that is performed in parallel to a data flow within the floating point unit.
A schematically depiction of the data flow 01 and the checking flow 02 of a state of the art residue checking for a floating point operation is shown in Fig. 1. Within the data flow 01 operands A, B and C are provided by an input register 03. The operands A, B and C are processed by different functional elements 04 according to the operation to be performed. Finally a result is provided within a result register 05. For the checking flow 02 residues are generated at significant positions
within the data flow 01 by residue generators 06. Modulo decoders 07 are connected with the residue generators 06 providing residue modulos to different functional elements 08 within the checking flow 02. For checking a final compare element 09 is foreseen which compares the result provided by the final functional element 08, 20 with the residue modulo of the result provided by the result register 05 of the data flow 01.
The functionalities of the functional elements 08 of the checking flow 02 as well as the functionalities of some of the functional elements 04 of the data flow 01 can be explained best regarding the different stages 10, 11, 12, 13, 14, 15 of the checking flow 02. In a first stage 10 of the checking flow 02 the residue modulos of the operands A and C are multiplied by the functional element 16. In the second stage 11 the residue modulo of the addend, which is the operand B in Fig. 1, is added to the product-residue modulo of the first stage 10 by the functional element 17. In the third stage 12 the residue modulo of the bits lost at the alignment 21 of the addend is subtracted by the functional element 18. In the fourth stage 13 a residue-multiplication with a constant to compensate for normalize-shift is performed by the functional element 19. In the fifth stage 14 a residue-subtract, of bits lost at the normalizer 22 is performed by the functional element 20. In the sixth stage the results of the residue of the result of the data flow 01 and the checking flow 02 are compared by the compare element 09.
Thereby the coverage of residue modulo checking depends on the Modulo m, which is chosen. Assuming a 'random' type of logic, i.e. assuming that a multiplier would represent this, the probability of an undetected single error with a Modulo m is 1/m. Or the in other words, (m-l)/m single errors will be detected, which is the checking coverage. For Modulo3 this is 1-
]
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1/3=2/3, for Modulo5 this is 1-1/5=4/5 and for Modulol5 this is 1-1/15=14/15.
As it can be seen that the coverage of residue checking depends on the Modulo m which is chosen, a high Modulo m is preferred, which disadvantageously is more difficult to implement than a lower modulo.
From US 4,926,374 a residue checking apparatus is known which uses common circuitry to conduct residue checking of the outcome of an arithmetic operation, which may be an addition, a subtraction, a multiplication, a divide or a square root operation.
Object of the invention
It is thus an object of the invention to develop an improved method and apparatus for residue modulo checking for arithmetic operations, which provides a high coverage of residue modulo checking but which is less complex to implement.
Summary of the invention
The shortcomings of the prior art are overcome and additional advantages are provided by a method for residue modulo checking for arithmetic operations. Thereby, according to the invention, the checking coverage of Modulo m is reached by separately applying at least two modulo operations in parallel, a first Modulo q0 operation and at least one second Modulo operation, wherein n=l, 2, 3, ... ;
Qo, qi, Q2, Qn-i, qn are primes with Qo^qi^^-^qn-i^qn; and m=qo*q1*q2*...*qn-i*qn.
]
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Doing so, the modulo calculation can be factorized and therefore used more effectively.
Thereby within the different stages of a checking flow the different operations required are performed for the first and the second modulo in parallel modulo flows, until finally a result of an arithmetic operation provided at the end of a data flow is e.g. successively compared with the results of the first and the second modulo flow, in order to get a check coverage corresponding to Modulo m.
According to a preferred embodiment of said method, the checking flow is subdivided into at least two parallel modulo flows, a first one where Modulo qo is applied and at least a second one where Modulo qn is applied, wherein a checking coverage of Modulo m is reached by separately comparing a residue modulo of a result of an arithmetic operation provided at the end of a data flow with the results of the parallel modulo flows, in order to get a check coverage corresponding to Modulo m.
A second subject of the invention concerns an apparatus for modulo checking for arithmetic operations. Said apparatus comprises means to separately apply at least two modulo operations in parallel on a checking flow, a first Modulo q0 operation and at least one second Modulo qn operation, wherein n=l, 2, 3, ... ;
Qo/ qi/ q2, .../ qn-i, qn are primes with q0^qi#q2^...#qn-i#qn; and m=q0 * qi * q2 * ...* qn-i * q„.
Preferably said apparatus comprises means to subdivide the checking flow into at least two parallel modulo flows, a first one where Modulo qo is applied and at least one second one where
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Modulo qn is applied, and means to separately compare a residue modulo of a result of an arithmetic operation provided at the end of a data flow with the results of the parallel modulo flows, in order to get a check coverage corresponding to Modulo m.
Preferably the means to separately apply at least two modulo operations in parallel on a checking flow comprise an arrangement and/or an apparatus providing a complete modulo decode for the modulos applied in the at least two parallel modulo flows.
According to a preferred embodiment of said apparatus, said means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus providing a modulo shift table.
According to another preferred embodiment of said apparatus,
said means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus for Modulo3 decode and an apparatus for Modulo5 decode.
According to an additional preferred embodiment of said apparatus, said means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus for Modulo3 add and an apparatus for Modulo5 add.
According to a particularly preferred embodiment of said apparatus, said means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus for Modulo3 subtract and an apparatus for Modulo5 subtract.
According to another particularly preferred embodiment of said apparatus, said means to separately apply at least two modulo
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operations in parallel on a checking flow comprise an apparatus for Modulo3 multiply and an apparatus for Modulo5 multiply.
It is also thinkable that the means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus for Modulo3 compare and an apparatus for Modulo5 compare.
The foregoing, together with other objects, features, and advantages of this invention can be better appreciated with reference to the following specification, claims and drawings.
Brief description of the drawings, with
Fig. 1 schematically showing a checking-flow in parallel to a data-flow according to the state of the art.
Fig. 2 schematically showing a check-coverage scheme with modulo values Modulo3, Modulo5 and Modulol5 according to the invention.
Fig. 3 schematically showing a checking-flow subdivided into two parallel modulo flows in parallel to a data-flow according to the invention.
Fig. 4 schematically showing an apparatus for a complete modulo checking according to the invention.
Fig. 5 showing a depiction of the modulo decode of the apparatus of Fig. 4.
Fig. 6 schematically showing an apparatus providing a modulo shift table according to the invention.
Fig. 7 schematically showing an apparatus for Modulo3 decode.
Fig. 8 schematically showing an apparatus for Modulo5 decode.
Fig. 9 schematically showing an apparatus for Modulo3 add.
Fig. 10 schematically showing an apparatus for Modulo3 subtract.
Fig. 11 schematically showing an apparatus for Modulo5 add.
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Fig. 12 schematically showing an apparatus for Modulo5 subtract.
Fig. 13 schematically showing an apparatus for Modulo3 multiply.
Fig. 14 schematically showing an apparatus for Modulo5 multiply.
Fig. 15 schematically showing an apparatus for Modulo3 compare.
Fig. 16 schematically showing an apparatus for Modulo5 compare.
Tab. 1 representing a shift table for Modulo3 of the apparatus shown in Fig. 6.
Tab. 2 representing a shift table for Modulo5 of the apparatus shown in Fig. 6.
Tab. 3 representing a Modulo3 decode table of the apparatus of Fig. 7.
Tab. 4 representing a Modulo5 decode table of the apparatus of Fig. 8.
Tab. 5 representing a Modulo3 add table of the apparatus of Fig. 9.
Tab. 6 representing a Modulo3 subtract table of the apparatus of Fig. 10.
Tab. 7 representing a Modulo5 subtract table of the apparatus of Fig. 12.
Tab. 8 representing a Modulo5 multiply table of the apparatus of Fig. 14.
Tab. 9 representing a Modulo3 multiply table of the apparatus of Fig. 13.
Tab. 10 representing a Modulo5 add table of the apparatus of Fig. 11.
Detailed description of the drawings
A basic idea of the invention is, that in general the coverage of residue checking depends on the Modulo m, which is chosen.
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Assuming a 'random' type of logic, i.e. assuming that a multiplier would represent this, the probability of an undetected single error with a modulo m is 1/m. In other words, (m-l)/m single errors will be detected, which is the checking coverage. As already explained, for Modulo3 this is 1-1/3=2/3, for ModuloB this is 1-1/5=4/5 and for Modulol5 this is 1-1/15=14/15.
The invention profits of the fact that the checking coverage (CC) of e.g. Modulol5 can be reached by separately applying Modulo3 (M3) and Modulo5 (M5), since the CC of M3+M5 is CC(M3+M5) = 1- (1/3*1/5) =14/15. The tables 23, 24, 25 in Fig. 2 show this in an example.
In general for Modulo p, q the CC of Mp+Mq is CC<Mp+Mq)=l-(l/p*l/q) as long as the modulo numbers are different primes.
When the logic is not of random type, like an adder, the checking coverage is higher, but the relationship between the factorized modulo values is still applicable.
Regarding an example shown in Fig. 3, where a check-coverage of e.g. Modulol5 is achieved by separately applying Modulo3 and Modulo5 in parallel, advantages of the invention over the state of the art are that
- Modulol5 would need fifteen decoded signals to handle, while Modulo3 needs only three and Modulo5 only five. Thus savings are in range of relation 15: (3 + 5) for combinatorial logic, wires and latches.
Separated Modulo3 plus Modulo5 are more effective to implement than Modulol5. This is valid for every modulo operation like e.g. Add, Sub, Mult, Divide, Increment, Decrement, etc. and for wiring to connect all these blocks.
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Thereby in Fig. 3 Modulo3 is indicated by Modulo p and Modulo5 is indicated by Modulo q to show the extendability of this scheme for other modulo-values. Both modulo flows 32, 33 are performed in parallel within a checking flow 31 parallel to a data flow 30.
It is important to mention that the following generalizations are thinkable
The invention is applicable for every modulo calculation, which is a product of primes 3, 5, 7,.. , without the primes 1, 2.
For practical use it is most effective, when the product of the primes is equal to 2b-l. Wherein here b is the number of bits in sections the operands are subdivided into.
Especially examples with primes p, q, r: p=3, q=5, b=4 (i.e. modulo 15) and p=3, q=5, r=17, b=8 (i.e. modulo 255) are of great advantage.
To implement the basic idea of the invention described above, an apparatus for modulo checking for arithmetic operations is foreseen. Said apparatus comprises means to separately apply at least two modulo operations in parallel on a checking flow 31, a first Modulo qo operation and at least one second Modulo qn operation, wherein n=l, 2, 3, ... ;
qo, qi, q2, •», qn-i. qn are primes with qo^qi^^-^qn-i^qn; and m=q0*q1*q2*...*qn-i*qn.
With reference to Fig. 3 said apparatus preferably comprises means to subdivide the checking flow 31 into at least two parallel modulo flows 32, 33, a first one 32 where Modulo qo is applied (Modulo p in Fig. 3) and at least one second one 33 where Modulo qn is applied (Modulo q in Fig. 3). Further said
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apparatus comprises means 34, 3 5 to separately compare a residue modulo 36 of a result of an arithmetic operation provided at the end of the data flow 30 with the results of the parallel modulo flows 32, 33, in order to get a check coverage corresponding to Modulo m.
Said means to separately apply at least two modulo operations in parallel on a checking flow 31 preferably comprise an arrangement 4 0 shown in Fig. 4. Said arrangement 40 provides a complete modulo decode for the modulos applied in the two parallel modulo flows. A depiction of an apparatus 50 providing the modulo decode of said arrangement 40 is shown in Fig. 5.
Fig. 4 shows an overview over the arrangement 40 providing the complete checking-structure as described herein. All residue-inputs from the dataflow on the left side are four bit wide and coded from binary '0000' up to binary '1111', so the first step before further calculation is to decode these input-vectors by the multiple Modulo decode blocks 50 to create modulo-values as inputs to the further processing-blocks 90, 100, 110, 120, 130, 140, 150 and 160 building up the two residue-flows for modulo3 and modulo5 shown on the right hand of figure 4.
For shift-operations of the dataflow during alignment and normalization of the operands, the dataflow delivers two shift-amount values of two bit each to allow shift-corrections from zero to three for the residue-values of the affected operands (residue of operand b for the alignment and normalizer data when subtracting normalizer-bits lost later on). These shift-values are translated into modulo-values by the two shift-table blocks 60 and these modulo-values are multiplied by blocks 130 and 140 respectively to compensate for the shift-operation that occurred in parallel within the dataflow. The shifted align-operand residue is added by blocks 90 and 110 to the product-residue.
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Beside the three input-operand residues, the dataflow delivers residue-values for bits lost during alignment (Res_aln(0..3)) and for bits lost at later normalization (Res_norm(0..3)). These losses are subtracted after shift-correction from the actually calculated, expected result-residue by the sub-blocks 100 and 120 for modulo3 and modulo5 respectively.
The result of all these calculations is the expected result to occur at the end of the checking-pipeline, and this is compared by blocks 150 and 160 against the dataflow-delivered Res_result(0..3) to deliver a check-signal in case of mismatch.
Fig.5 shows the structure of the decode blocks 50, i.e. of the apparatus 50 providing the modulo decode of the arrangement 4 0 shown im Fig. 4. Each block 50 gets a four bit binary coded input-value between '0000' and '1111' standing for decimal 0..15, which represents the modulol5-value delivered from the dataflow. This input is decoded in subblock 51 for modulo3 and in subblock 52 for modulo5,
Delivering a three bit modulo3 output and a five bit modulo5 output. Details of the subblocks 51 and 52 are described later with reference to Figs. 7 and 8.
Said means to separately apply at least two modulo operations in parallel on a checking flow 31 can also comprise an apparatus 60 providing a modulo shift table (Fig. 4). Such an apparatus is shown in Fig. 6. An associated shift table for Modulo3 is given in Tab. 1 and an associated shift table for Modulo5 is given in Tab. 2. Thereby the section 61 of the apparatus 60 performs the Modulo3 shift table (Tab. 1), wherein the section 62 of the apparatus 60 performs the Modulo5 shift table (Tab. 2).
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Fig. 6 shows the structure and internals of the modulo-shift blocks 60, i.e. of an apparatus 60 providing a modulo shift table. Input is a two bit coded shift-amount between zero and three, whereof for modulo3 the section 61 providing the Modulo 3 shift-table only needs the lower bit (1) and creates a modulo3 value of either 'one' at '00'-input (to pass modulo for unshifted data) or 'two' at '01'-input (for shifted data to multiply data by two in next block 130), according to Tab. 1. The only logic-gate needed here is the shown inverter 65. The section 62 does similar for modulo5, where both inputs and more logic are needed to form a modulo5-value for shift-amounts from zero to three according to Tab. 2. The logic to do so consists of four AND-gates 63 shown in Fig. 6 and four inverters 64 represented by the input-dots of three of these AND-gates 63.
It is also thinkable that said means to separately apply at least two modulo operations in parallel on a checking flow 31 comprise an apparatus 51 for Modulo3 decode and/or an apparatus 52 for Modulo5 decode (Fig. 5). An example of an apparatus 51 for Modulo3 decode is shown in Fig. 7. This apparatus 51 performs a Modulo3 decode as given in Tab. 3. An example of an apparatus 52 for Modulo5 decode is shown in Fig. 8. This apparatus 52 performs a Modulo5 decode as given in Tab. 4. The apparatus 51 as well as the apparatus 52 are part of the apparatus 50 shown in Fig. 5.
Fig.7 shows the details of the modulo3 decoder block 51, i.e. of the apparatus 51 for Modulo3 decode, doing the logic of Tab. 3 to decode the input-values 0 to 15 into the modulo3 bits (0 to 2). The AND-gates 70 shown, together with the inverters 71 represented by the input-dots at some of their inputs decode each input-value and the three OR-gates 72 of the second stage do an OR-together of those five to six decodes for each of the modulo3 bits (0 to 2).
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FIG.8 shows the details of the modulo5 decoder block 52, i.e. of the apparatus 52 for Modulo5 decode, doing the logic of Tab. 4 to decode the input-values 0 to 15 into the modulo5 bits (0 to 4). The AND-gates 80 shown, together with the inverters 81 represented by the input-dots at some of their inputs decode each input-value and the five OR-gates 82 of the second stage do an OR-together of those three to four decodes for each of the modulo5 bits (0 to 4).
Said means to separately apply at least two modulo operations in parallel on a checking flow 31 can also comprise an apparatus 90 for Modulo3 add and/or an apparatus 110 for Modulo5 add (Fig. 4). An example of an apparatus 90 for Modulo3 add is shown in Fig. 9. The apparatus 90 performs a Modulo3 add according to Tab. 5. An example of an apparatus 110 for Modulo5 add is shown in Fig. 11. The apparatus 110 performs a Modulo5 add according to Tab. 10.
Fig. 9 shows the details of the modulo3 adder block 90, i.e. of the apparatus 9 0 for Modulo3 add, doing the logic of Tab. 5 to add the input-values a(0 to 2) and b(0 to 2} into the modulo3 bits (0 to 2). The AND-gates 91 shown decode each relevant input-value according to Tab. 5 to form the three modulo3 sum-bits and the three OR-gates 92 of the second stage do an OR-together of the three decodes for each of the modulo3 bits (0 to 2) .
Fig.11 shows the details of the modulo5 adder block 100, i.e. of the apparatus 110 for Modulo5 add, doing the logic of Tab. 10 to add the input-values a(0 to 4) and b(0 to 4) into the modulo5 bits (0 to 4). The AND-gates 111 shown decode all relevant input-value according to Tab. 10 to form the five modulo5 sum-bits, wherein the five OR-gates 112 of the second stage do an
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OR-together of those five adds for each of the modulo5 bits (0 to 4). To condense the drawing a little, the gates for m5 (1..3) are not explicitly shown, as indicated by the dots .
It is also thinkable that said means to separately apply at least two modulo operations in parallel on a checking flow 31 comprise an apparatus 100 for Modulo3 subtract and/or an apparatus 120 for Modulo5 subtract (Fig. 4). An example of an apparatus 100 for Modulo3 subtract is shown in Fig. 10. Further, an example of an apparatus 120 for Modulo5 subtract is shown in Fig. 12. The apparatus 100 performs a Modulo3 subtract according to Tab. 6. The apparatus 120 performs a Modulo5 subtract according to Tab. 7.
Fig. 10 shows the details of the modulo3 subtract block 100, i.e. of the apparatus 100 for Modulo3 subtract, doing the logic of Tab. 6 to subtract the input-values a (0 to 2) and b (0 to 2) into the modulo3 bits (0 to 2). The AND-gates 101 shown decode each relevant input-value according to Tab. 6 to form the three modulo3 sum-bits. The three OR-gates 102 of the second stage do an OR-together of the three decodes for each of the modulo3 bits (0 to 2) .
Fig.12 shows the details of the modulo5 subtrac block 120, i.e. of the apparatus 120 for Modulo5 subtract, doing the logic of Tab. 7 to decode the input-values a (0 to 4) and b (0 to 4) into the modulo5 bits (0 to 4). The AND-gates 121 shown decode each relevant input-value according to Tab. 7 to form the five moduloS result-bits. The five OR-gates 122 of the second stage do an OR-together of those five decodes for each of the modulo5 bits (0 to 4). It is important to mention, that to condense the drawing a bit, the gates for m5 (1..3) are not explicitly shown, as indicated by the dots .
As depicted in Fig. 4, said means to separately apply at least two modulo operations in parallel on a checking flow 31 can further comprise an apparatus 130 for Modulo3 multiply shown in Fig. 13 and/or an apparatus 140 for Modulo5 multiply shown in Fig. 14. The apparatus 130 performs a Modulo3 multiply according to Tab. 9 and the apparatus 140 performs a Modulo5 multiply according to Tab. 8.
Fig. 13 shows the details of the modulo3 multiply block 130, i.e. of the apparatus 130 for Modulo3 multiply, doing the logic of Tab. 9 to multiply the input-values a (0 to 2) and b (0 to 2) into the modulo3 bits (0 to 2). The AND-gates 131 shown decode each relevant input-value according to Tab. 9 to form the three modulo3 result-bits, wherein the three OR-gates 132 of the second stage do an OR-together of the three decodes for each of the modulo3 bits (0 to 2).
Fig. 14 shows the details of the modulo5 multiply block 140, i.e. of the apparatus 140 for Modulo5 multiply, doing the logic of Tab. 8 to multiply the input-values a (0 to 4) and b (0 to 4) into the modulo5 bits (0 to 4). The AND-gates 141 shown decode each relevant input-value according to Tab. 8 to form the five modulo5 result-bits, wherein the five OR-gates 142 of the second stage do an OR-together of the one to four decodes for each of the modulo5 bits (0 to 4).
It is also thinkable that the means to separately apply at least two modulo operations in parallel on a checking flow comprise an apparatus 150 for Modulo3 compare and/or an apparatus 160 for Modulo5 compare (Fig. 4). An apparatus 150 for Modulo3 compare is schematically shown in Fig. 15. An apparatus 160 for Modulo5 compare is schematically shown in Fig. 16.
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Fig. 15 shows the details of the modulo3 result compare block 150, i.e. of the apparatus 150 for Modulo3 compare, doing a bit by bit compare by XOR-gates 151 of the modulo3 value delivered from the dataflow-result with the calculated result of the modulo3 flow 31. In case of mismatch of one of the three XOR-compares, the OR-gate 152 sends a check-signal as output.
Fig. 16 shows the details of the modulo5 result compare block 160, i.e. of the apparatus 160 for Modulo5 compare, doing a bit by bit compare by XOR-gates 161 of the modulo5 value delivered from the dataflow-result with the calculated result of the modulo5 flow 32. In case of mismatch of one of the five XOR-compares, the OR-gate 162 sends a check-signal as output.
The apparatus 150 and the apparatus 160 preferably form the means 34, 35 (Fig. 3) to separately compare a residue modulo 36 of a result of an arithmetic operation provided at the end of the data flow 30 with the results of the parallel modulo flows 32, 33, in order to get a check coverage corresponding to Modulo m.
It is important to mention that within this description the primes q0, qi, q2 are indicated by p, q, r in order to simplify.
While the present invention has been described in detail, in conjunction with specific preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
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Claims (11)
1. Method for residue modulo checking for arithmetic operations, characterized in that in order to get a high Modulo m and thus a high residue modulo checking coverage within a checking flow (31), Modulo m is reached by separately applying at least two modulo operations (32, 33) in parallel, a first Modulo q0 (32) operation and at least one second Modulo qn (33) operation, wherein n=1, 2, 3 , . . . ;
Qo, qi, q?, qn-i/ qn are primes with q0^qi^q2^-• .^qn-i^qn; and m=qo*qj*q2* . . . *qn-i*qn-
2. Method according to claim 1, characterized in that the checking flow (31) is subdivided into at least two parallel modulo flows (32, 33), a first one (32) where Modulo qo is applied and at least one second one (33) where Modulo qn is applied, wherein a checking coverage of Modulo m is reached by separately comparing a residue modulo (36) of a result of an arithmetic operation provided at the end of a data flow (30)
with the results of the parallel modulo flows (32, 33).
3. Apparatus for modulo checking for arithmetic operations, characterized by means (40, 50, 60, 90, 100, 110, 120, 130, 140, 150, 160) to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31), a first Modulo qo operation (32) and at least one second Modulo qn operation (33), wherein n=l, 2, 3,
qo, qi, <Z2 qn-i, qn are primes with q0#qi#q2#. . .^qn-i^qn; and m=q0*qi*q2* . . . *qn-i*qn-
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4. Apparatus according to claim 3, characterized by means to subdivide the checking flow into at least two parallel modulo flows (32, 33), a first one (32) where Modulo qo is applied and at least one second one (33) where Modulo qn is applied, and means (34, 35, 150, 160) to separately compare a residue modulo (36) of a result of an arithmetic operation provided at the end of a data flow (30) with the results of the parallel modulo flows (32, 33).
5. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an arrangement (40) and/or an apparatus (50) providing a modulo decode for the modulos applied in the at least two parallel modulo flows.
6. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus (60) providing a modulo shift table.
7. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus (51) for Modulo3 decode and an apparatus (52) for Modulo5 decode.
8. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus (90) for Modulo3 add and an apparatus (110) for Modulo5 add.
r
- 19 -
9. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus (100) for Modulo3 subtract and an apparatus (120) for Modulo5 subtract.
10. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus for Modulo3 multiply (130) and an apparatus (140) for Modulo5 multiply.
11. Apparatus according to claim 3 or 4, characterized in that the means to separately apply at least two modulo operations (32, 33) in parallel on a checking flow (31) comprise an apparatus (150) for Modulo3 compare and an apparatus (160) for Modulo5 compare.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP08150329 | 2008-01-16 |
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| Publication Number | Publication Date |
|---|---|
| GB0822772D0 GB0822772D0 (en) | 2009-01-21 |
| GB2456624A true GB2456624A (en) | 2009-07-22 |
| GB2456624B GB2456624B (en) | 2012-05-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130204916A1 (en) * | 2012-02-06 | 2013-08-08 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
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|---|---|---|---|---|
| US3814923A (en) * | 1973-01-02 | 1974-06-04 | Bell Telephone Labor Inc | Error detection system |
| US4926374A (en) * | 1988-11-23 | 1990-05-15 | International Business Machines Corporation | Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations |
| US6694344B1 (en) * | 1998-11-10 | 2004-02-17 | International Business Machines Corporation | Examination of residues of data-conversions |
| US20040260931A1 (en) * | 2001-10-17 | 2004-12-23 | Infineon Technologies Ag | Method and apparatus for protecting an exponentiation calculation by means of the chinese remainder theorem (CRT) |
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2008
- 2008-12-15 GB GB0822772.0A patent/GB2456624B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3814923A (en) * | 1973-01-02 | 1974-06-04 | Bell Telephone Labor Inc | Error detection system |
| US4926374A (en) * | 1988-11-23 | 1990-05-15 | International Business Machines Corporation | Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations |
| US6694344B1 (en) * | 1998-11-10 | 2004-02-17 | International Business Machines Corporation | Examination of residues of data-conversions |
| US20040260931A1 (en) * | 2001-10-17 | 2004-12-23 | Infineon Technologies Ag | Method and apparatus for protecting an exponentiation calculation by means of the chinese remainder theorem (CRT) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130204916A1 (en) * | 2012-02-06 | 2013-08-08 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
| US8984039B2 (en) * | 2012-02-06 | 2015-03-17 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2456624B (en) | 2012-05-30 |
| GB0822772D0 (en) | 2009-01-21 |
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