GB2456624B - Method and apparatus for residue modulo checking for arithmetic operations - Google Patents

Method and apparatus for residue modulo checking for arithmetic operations

Info

Publication number
GB2456624B
GB2456624B GB0822772.0A GB0822772A GB2456624B GB 2456624 B GB2456624 B GB 2456624B GB 0822772 A GB0822772 A GB 0822772A GB 2456624 B GB2456624 B GB 2456624B
Authority
GB
United Kingdom
Prior art keywords
checking
arithmetic operations
residue modulo
modulo
residue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0822772.0A
Other versions
GB0822772D0 (en
GB2456624A (en
Inventor
Guenter Gerwig
Klaus Michael Kroener
Juergen Haess
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB0822772D0 publication Critical patent/GB0822772D0/en
Publication of GB2456624A publication Critical patent/GB2456624A/en
Application granted granted Critical
Publication of GB2456624B publication Critical patent/GB2456624B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/721—Modular inversion, reciprocal or quotient calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
GB0822772.0A 2008-01-16 2008-12-15 Method and apparatus for residue modulo checking for arithmetic operations Expired - Fee Related GB2456624B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08150329 2008-01-16

Publications (3)

Publication Number Publication Date
GB0822772D0 GB0822772D0 (en) 2009-01-21
GB2456624A GB2456624A (en) 2009-07-22
GB2456624B true GB2456624B (en) 2012-05-30

Family

ID=40326076

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0822772.0A Expired - Fee Related GB2456624B (en) 2008-01-16 2008-12-15 Method and apparatus for residue modulo checking for arithmetic operations

Country Status (1)

Country Link
GB (1) GB2456624B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9170771B2 (en) 2012-02-06 2015-10-27 International Business Machines Corporation Residue-based error detection for a processor execution unit that supports vector operations

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814923A (en) * 1973-01-02 1974-06-04 Bell Telephone Labor Inc Error detection system
US4926374A (en) * 1988-11-23 1990-05-15 International Business Machines Corporation Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations
US6694344B1 (en) * 1998-11-10 2004-02-17 International Business Machines Corporation Examination of residues of data-conversions
US20040260931A1 (en) * 2001-10-17 2004-12-23 Infineon Technologies Ag Method and apparatus for protecting an exponentiation calculation by means of the chinese remainder theorem (CRT)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814923A (en) * 1973-01-02 1974-06-04 Bell Telephone Labor Inc Error detection system
US4926374A (en) * 1988-11-23 1990-05-15 International Business Machines Corporation Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations
US6694344B1 (en) * 1998-11-10 2004-02-17 International Business Machines Corporation Examination of residues of data-conversions
US20040260931A1 (en) * 2001-10-17 2004-12-23 Infineon Technologies Ag Method and apparatus for protecting an exponentiation calculation by means of the chinese remainder theorem (CRT)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9170771B2 (en) 2012-02-06 2015-10-27 International Business Machines Corporation Residue-based error detection for a processor execution unit that supports vector operations

Also Published As

Publication number Publication date
GB0822772D0 (en) 2009-01-21
GB2456624A (en) 2009-07-22

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20130107

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20191215