GB2456616A

GB2456616A - Active matrix vertical alignment LCD apparatus utilising slits in pixel electrodes

Info

Publication number: GB2456616A
Application number: GB0819412A
Authority: GB
Inventors: Sakae Tanaka; Toshiyuki Samejima
Original assignee: Mikuni Electron Co Ltd
Current assignee: Mikuni Electron Co Ltd
Priority date: 2006-06-15
Filing date: 2008-10-23
Publication date: 2009-07-22
Anticipated expiration: 2027-04-26
Also published as: GB0819412D0; GB2456616B

Abstract

An active matrix vertical alignment liquid crystal display (LCD) apparatus comprises: a slit 6 for liquid crystal alignment control formed on a transparent pixel electrode 5; an insulating film 8 formed on the transparent pixel electrode; and a liquid crystal alignment control electrode 12 formed on a TFT substrate underneath the slit 6. The liquid crystal alignment control electrode 12 has the same potential as the transparent pixel electrode 5, preferably by being connected to the same voltage source. The LCD apparatus preferably further includes a video signal line (17) and a scan line (13). The video signal line (17), the transparent pixel electrode 5 and the liquid crystal alignment electrode 12 are preferably bent 90 degrees in a position proximate the centre of the transparent pixel electrode 5 and are aligned to the scan line (13) at an angle of 45 degrees.

Description

2456616

AN ACTIVE MATRIX VERTICAL ALIGNMENT LIQUID CRYSTAL

DISPLAY APPARATUS

FIELD OF THE INVENTION

5 The present invention relates to a large-screen wide-angle liquid crystal display apparatus manufactured by using a halftone exposure method.

BACKGROUND OF THE INVENTION

In multi-domain vertical alignment (MVA) liquid crystal display apparatuses,

an alignment control electrode for controlling an alignment of a liquid crystal 10 molecule has been disclosed in Japan Laid Open Patents Nos. 07-230097, 11-109393 and 2001-042347.

SUMMARY OF THE INVENTION

In view of the shortcomings of the prior art, the inventor of the present invention based on years of experience in the related industry to conduct 15 researches and experiments, and finally developed a large-screen wide-angle liquid crystal display apparatus in accordance with the present invention to overcome the foregoing shortcomings.

Therefore, it is a primary objective of the present invention to adopt a prior art alignment control electrode of an LCD panel structure to correspond to smaller 20 pixels. Since only one type of alignment control electrode is used only, and the edge field effect of a pixel electrode is adopted, therefore it is not applicable for lager pixels.

At present, the mainstream of multi-domain vertical alignment (MVA) liquid crystal display apparatus generally uses a bump or slit electrode for the alignment 25 control of the sides of a color filter (CF) substrate, and this method can make a

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proper alignment if the pixel is large, but the cost of CF substrates is high, and becomes an obstacle for manufacturing a large-screen liquid crystal TV by a low cost.

Therefore, it is a primary objective of the present invention to reduce the 5 number of photolithographic procedures of the TFT active matrix substrate and the CF substrate during the manufacture of the TFT active matrix liquid crystal display apparatus, in order to shorten the manufacturing procedure, lowering the manufacturing cost, and improving the yield rate.

The technical measures taken by the present invention are described as 10 follows.

In Measure I, unstable and swinging discrimination lines are avoided, and two types of alignment control electrodes are installed at an upper layer of a pixel electrode through an insulating film, and between common electrodes corresponding to the pixel electrodes. With the foregoing two different types of 15 alignment control electrodes, the oblique direction of anisotropic liquid crystal molecules having a negative dielectric constant can be controlled precisely.

In Measure 2, one type of alignment control electrode is installed at an upper layer of a pixel electrode through an insulating film, and a slender slit is formed in the pixel electrode, and these two alignment control mechanisms can control the 20 oblique direction of anisotropic liquid ciystal molecules having a negative dielectric constant precisely.

In Measure 3, the alignment control electrodes as used in Measures 1 and 2 is connected to the pixel electrodes as closer to the substrate as possible.

In Measure 4, the alignment control mechanisms as used in Measures 1 and 2 25 provides four perfect area alignments for a curvature of 90 degrees at a position

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proximate to the center of the pixel.

In Measure 5, a halftone exposure method is introduced into the manufacturing process of the TFT array substrate to reducc the number of photolithographic procedures.

5 In Measure 6, a basic unit pixel is divided into two sub pixels, and the common electrodes are installed parallelly on a video signal line, and the common electrodes of odd-numbered rows and even-numbered rows switch signals with different polarities in each scan period, and produce different voltages applied to the liquid crystal molecules of the two sub pixels.

10 With Measures 1 and 2, the TFT array substrate has all alignment control functions, and thus it is not necessary to form a pad or slit on the CF substrate for the alignment control, so that the MVA LCD panel can be manufactured with a low-cost CF substrate to lower the cost and improve the yield rate.

With Measure 3, the alignment control electrode connected to the pixel 15 electrode is proximate to the substrate for enhancing the rotational torque of an electric field of anisotropic liquid crystal molecules having negative dielectric constant and acted at the vertical alignment, so as to achieve a high-speed response.

With Measure 4, unnecessary discrimination lines can be avoided to improve 20 the overall light transmission rate of the screen and reduce unevenness of the LCD panel.

With Measures 1, 2 and 5, the processing costs for both CF substrate and TFT array substrate can be lowered, and thus the manufacturing cost of MVA LCD panels can be lowered significantly; the production efficiency can be improved, 25 and the yield rate can be enhanced.

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«..

I

t,

With Measures 5 and 6, the liquid crystal alignment control mechanism can be manufactured by a very simple manufacturing process, and the correction of y curve can be achieved by a very simple circuit, and thus a little cost is incurred for enhancing the display quality of a MVA liquid crystal display apparatus.

5 BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a cross-sectional view of a conventional MVA LCD panel;

Fig. 2 is a cross-sectional view of a conventional MVA LCD panel;

Fig. 3 is a cross-sectional view of a MVA LCD panel of the present invention;

Fig. 4 is a cross-sectional view of a MVA LCD panel of the present invention; 10 Fig. 5 is a schematic view of the principle of a MVA LCD panel of the present invention;

Fig. 6 is a schematic view of the principle of a MVA LCD panel of the present invention;

Fig. 7 is a schematic view of the principle of a MVA LCD panel of the present 15 invention;

Fig. 8 is a cross-sectional view of a MVA LCD panel adopting a TFT matrix substrate in accordance with the present invention;

Fig. 9 is a cross-sectional view of a TFT array substrate used for a MVA LCD panel in accordance with the present invention;

20 Fig. 10 is a cross-sectional view of a TFT array substrate used for a MVA LCD panel in accordance with the present invention;

Fig. 11 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 12 is a cross-sectional view of a TFT array substrate used in a MVA LCD 25 panel in accordance with the present invention;

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Fig. 13 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 14 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

5 Fig. 15 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 16 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 17 is a cross-sectional view of a TFT array substrate used in a MVA LCD 10 panel in accordance with the present invention;

Fig. 18 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 19 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

15 Fig. 20 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 21 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 22 is a cross-sectional view of a TFT array substrate used in a MVA LCD 20 panel in accordance with the present invention;

Fig. 23 is a cross-sectional view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 24 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

25 Fig. 25 is a planar view of a TFT array substrate used in a MVA LCD panel in

accordance with the present invention;

Fig. 26 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 27 is a planar view of a TFT array substrate used in a MVA LCD panel in 5 accordance with the present invention;

Fig. 28 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 29 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

10 Fig. 30 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 31 is a planar view of a TFT array substrate used in a MVA LCD panel in accordance with the present invention;

Fig. 32 shows a circuit model of a TFT array substrate of field-sequential 15 driven MVA LCD panel in accordance with the present invention;

Fig. 33 shows a relation between the brightness and the signal voltage applied to a MVA LCD panel as depicted in Fig. 32;

Fig. 34 is a waveform diagram of a MVA LCD panel as depicted in Fig. 21;

Fig. 35 shows a circuit model of a TFT array substrate that is divided into 20 upper and lower field-sequential driven MVA LCD panels in accordance with the present invention;

Fig. 36 illustrates a field-sequential driving method that divides a screen into upper and lower sections and writes data from the center of the screen to the upper or lower section of the screen in accordance with the present invention; 25 Fig. 37 illustrates a field-sequential driving method that divides a screen into

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upper and lower sections and writes data from the upper or lower sections of the screen towards the center of the screen in accordance with the present invention;

Fig. 38 illustrates a field-sequential driving method that divides a screen into upper and lower sections and writes data from the center of the screen to the upper 5 or lower section of the screen in accordance with the present invention;

Fig. 39 illustrates a field-sequential driving method that divides a screen into upper and lower sections and writes data from the upper or lower sections of the screen towards the center of the screen in accordance with the present invention;

Fig. 40 is a cross-sectional view of a basic unit pixel of a TFT array substrate 10 of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 41 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 42 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention; 15 Fig. 43 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 44 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 45 is a cross-sectional view of a basic unit pixel of a TFT array substrate 20 of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 46 shows a circuit model of a circuit of a TFT array substrate of a field-sequential driven horizontal electric field LCD panel in accordance with the present invention;

Fig. 47 is a cross-sectional view of a TFT array substrate of a horizontal 25 electric field LCD panel in accordance with the present invention;

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Fig. 48 is a cross-sectional view of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 49 is a planar view of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

5 Fig. 50 is a planar view of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 51 is a planar view of a TF'f array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 52 is a planar view of a TFT array substrate of a horizontal electric field 10 LCD panel in accordance with the present invention;

Fig. 53 is a planar view of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

Fig. 54 is a planar view of a TFT array substrate of a horizontal electric field LCD panel in accordance with the present invention;

15 Fig. 55 is a waveform diagram of a horizontal electric field LCD panel as depicted in Fig. 54;

Fig. 56 shows a circuit model of a TFT array substrate of a field-sequential driven horizontal electric field LCD panel that divides a display screen into upper and lower sections in accordance with the present invention;

20 Fig. 57 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a MVA LCD panel in accordance with the present invention;

Fig. 58 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a MVA LCD panel in accordance with the present invention;

Fig. 59 is a cross-sectional view of a basic unit pixel of a TFT array substrate 25 of a MVA LCD panel in accordance with the present invention;

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Fig. 60 is a cross-sectional view of a basic unit pixel of a TFT array substrate of a MVA LCD panel in accordance with the present invention;

Fig. 61 is a cross-sectional view of a manufacturing flow that adopts a halftone exposure method to form a contact pad for a pixel electrode in accordance with 5 the present invention;

Fig. 62 is a cross-sectional view of a manufacturing flow that adopts a halftone exposure method to form a contact pad for a pixel electrode in accordance with the present invention;

Fig. 63 is a cross-sectional view of a manufacturing flow that adopts a halftone 10 exposure method to give an island effect to a semiconductor layer of a thin film transistor component and form a contact hole in accordance with the present invention;

Fig. 64 is a cross-sectional view of a manufacturing flow that forms a source 15 electrode, a drain electrode, a terminal electrode, and comb common electrode in accordance with the present invention;

Fig 65 is a cross-sectional view of a flow of manufacturing a thin film transistor substrate by a halftone exposure method in accordance with the present invention;

20 Fig. 66 illustrates the structure of a horizontal electric field active matrix substrate at a center pixel common electrode of the center of a basic unit pixel;

Fig. 67 illustrates a masking principle of a halftone exposure applied in the present invention;

Fig. 68 illustrates the principle of a halftone multiple exposure method applied 25 in the present invention;

Fig. 69 illustrates a first photolithographic procedure that needs to align at a mark when using a halftone multiple exposure method in accordance with the present invention;

Fig. 70 illustrates the principle of aligning with a mark by a halftone multiple 5 exposure method that uses a pulse laser in a glass substrate in accordance with the present invention;

Fig. 71 is a cross-sectional view of a manufacturing flow of using a halftone exposure method to form a thin film transistor substrate in accordance with the present invention;

10 Fig. 72 is a cross-sectional view of a manufacturing flow of using a halftone exposure method to form a scan line portion, a pixel electrode and a terminal portion of a thin film transistor substrate in accordance with the present invention;

Fig. 73 shows a cross-sectional view of a manufacturing flow of using a halftone exposure method to give an island effect to a semiconductor layer of a 15 thin film transistor component and expose a pixel electrode and a terminal portion completely;

Fig. 74 shows a cross-sectional view of a manufacturing flow before forming a source electrode and a drain electrode in the process of manufacturing a thin film transistor component as illustrated in Figs. 73 and 74;

20 Fig. 75 is cross-sectional view of the structure forming a TFT array substrate of an alignment control electrode connected to a scan line and disposed on the previously formed pixel electrode;

Fig. 76 is a planar view of a TFT array substrate as depicted in Fig. 75;

Fig. 77 is a cross-sectional view of forming a vertical alignment cell of one 25 type of alignment control electrode connected to a common electrode and

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disposed on the previously formed pixel electrode;

Fig. 78 is a cross-sectional view of a vertical alignment cell of one type of alignment control electrode connected to a pixel electrode and disposed on the previously formed plate electrode;

5 Fig. 79 is a cross-sectional view of a structure of forming only one type of alignment control electrode on a pixel electrode of the previously formed TFT array substrate;

Fig. 80 is a cross-sectional view of a structure of forming only one type of alignment control electrode on a pixel electrode of the previously formed TFT 10 array substrate;

Fig. 81 is a cross-sectional view of a structure of forming only one type of alignment control electrode on a pixel electrode of the previously formed TFT array substrate;

Fig. 82 illustrates a manufacturing flow of performing the photolithographic 15 procedure for three times that uses a MVA TFT array substrate to apply a halftone exposure method for two times;

Fig. 83 illustrates a manufacturing flow of performing the photolithographic procedure for three times that uses a MVA TFT array substrate to apply a halftone exposure method for two times;

20 Fig. 84 illustrates a manufacturing flow of performing the photolithographic procedure for three times that uses an IPS TFT array substrate to apply a halftone exposure method for three times; and

Fig. 85 illustrates a manufacturing flow of performing the photolithographic procedure for three times that uses an IPS TFT array substrate to apply a halftone 25 exposure method for three times.

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The reference numerals in the figures:

1 opposite flat common electrode

2 bump for liquid crystal alignment control

3 vertical alignment film

5 4 slit for liquid crystal alignment control formed at an opposite flat common electrode

5 pixel electrode

6 slit for liquid crystal alignment control formed at a pixel electrode

7 liquid crystal molecules of negative dielectric anisotropy 10 8 insulating film

9 liquid crystal alignment control electrode connected to a common electrode

10 liquid crystal alignment control electrode connected to a pixel electrode

11 equal-potential lines

15 12 alignment control electrode disposed under an alignment control slit of a pixel electrode

13 scan line (gate electrode)

14 contact pad formed in a pixel electrode (for connecting a drain electrode)

15 passivation film 20 16 common electrode

17 video signal line (source electrode)

18 drain electrode

19 barrier metal

20 ohmic contact layer (n+-a-silicon layer)

25 21 non-doped film semiconductor layer (i-a-silicon layer)

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25

26

27

28

29

30

31

32

33

34

35

36

37

contact pad formed in a pixel electrode (for connecting an alignment control electrode)

contact pad formed in a pixel electrode (for connecting a holdup capacitor forming electrode)

holdup capacitor forming electrode glass substrate alignment control electrode connected to a common electrode buried in a gate insulating film gate insulating film at lower layer gate insulating film at upper layer pixel electrode buried in a gate insulating film floating electrode for increasing the height of a alignment control electrode connected to a pixel clectrode pad electrode for increasing the height of a alignment control electrode connected to a pixel electrode thin film transistor component contact hole for connecting an alignment control electrode and a common electrode contact hole for connecting a drain electrode and a contact pad formed in a pixel electrode contact hole for connecting an alignment control electrode and a contact pad formed in a pixel electrode contact hole opened on a passivation film of a drain electrode thin film transistor component for driving large area pixel electrode (sub pixel B)

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38 thin film transistor component for driving small area pixel electrode (sub pixel A)

39 common electrode arranged in parallel to a video signal line (source electrode)

40 large area pixel electrode (sub pixel B)

41 small area pixel electrode (sub pixel A)

42 contact hole opened on a passivation film of a common electrode

43 common electrode for shielding a video signal line

44 comb common electrode for driving liquid crystal

45 comb pixel electrode for driving liquid crystal

46 common electrode at the center of a pixel (Center COM electrode), which is arranged in parallel to a video signal line

47 contact hole for connecting a holdup capacitor forming electrode and a contact pad formed in a pixel electrode

48 contact hole for connecting a common electrode and a comb common electrode for driving liquid crystal

49 plat common electrode for driving liquid crystal

50 contact hole for connecting a common electrode at the center of a pixel (Center COM electrode) and a common electrode for shielding a video signal line

51 video signal line for driving a upper display screen

52 video signal line for driving a lower display screen

53 thick area of positive photoresist developed by halftone exposure

54 thin area of positive photoresist developed by halftone exposure

55 transparent electrode layer

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57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

low-resistance wiring electrode layer remained positive photoresist after an oxygen plasma ashing process complete blocking region of UV light at a halftone mask transparent region of UV light at a halftone mask semi-transparent region of UV light at a halftone mask positive photoresist for halftone exposure connection terminal of a external circuit alignment film region of a good rubbing process alignment film region of a bad rubbing process textile fiber of a rubbing process quartz glass for a halftone mask

UV light of complete exposure region

UV light of incomplete exposure region alignment mark formed inside a glass substrate for a halftone double exposure process pulsed laser light condenser remained positive photoresist after a general exposure process source electrode formed by a transparent electrode (video signal line) opposite substrate (CF substrate)

liquid crystal alignment control electrode connected to a gate electrode alignment control electrode which has the same potential as a common electrode formed on the passivation film metal electrode which is the same as a gate electrode (connected to a transparent pixel electrode)

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78 alignment control electrode formed by the same transparent electrode material as a pixel electrode

79 metal electrode which is the same as a source electrode and a drain electrode (connected to a alignment control electrode)

5 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

To make it easier for our examiner to understand the objective, innovative features and performance of the present invention, we use a preferred embodiment and the accompanying drawings for a detailed description of the present invention.

Referring to Figs. 1 and 2 for cross-sectional views of a current mainstream 10 MVA LCD panel, a mechanism for controlling the direction of movements both is installed separately on upper and lower substrates to control the vertical alignment of anisotropic liquid crystal molecules of a negative dielectric constant. Since the discrimination line of an LCD panel using this method is constant without swinging, therefore uneven display rarely occurs, and LCD panels with high 15 quality of display can be produced at a good yield rate. However, it is necessary to form a slit or a bump disposed on a lateral side of a CF substrate corresponding to a TFT substrate for the structure as shown in Figs. 1 and 2 to control the liquid crystal alignment, and the production cost of the CF substrate is higher than that of the TN CF substrate. To lower the cost of the CF substrate, all liquid crystal 20 alignment control functions are built in the TFT substrate side.

Referring to Figs. 75 to 81 for an embodiment of a CF substrate side having no alignment control function as disclosed in the previous patents, these CF substrates cannot be used as large substrates. These prior arts can be used for small pixels only. Since an edge field effect of a pixel electrode is used, 25 therefore these substrates are not appropriate for the large pixel electrodes used for

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the liquid crystal TV.

With the two basic structures as shown in Figs. 3 and 4, a TFT substrate side has all of the liquid crystal alignment control functions. In the TFT substrate side as shown in Fig. 3, two different liquid crystal alignment control electrodes 5 are installed between the common electrode of the substrate and corresponding to the pixel electrode to successfully form an equal-potential distribution as shown in Fig. 5. In Fig. 4, one type of alignment control electrode is installed on a pixel electrode at the TFT substrate side and between the slit for alignment control and the pixel electrode corresponding to the common electrode of the substrate to 10 successfully from an equal-potential distribution as shown in Fig. 6. Even for a structure as shown in Fig. 7 instead of the structure as shown in Fig. 6, the similar equal-potential distribution an be formed successfully.

From Figs. 5 to 7, a liquid crystal alignment control electrode connected to a pixel electrode is installed at an upper layer of the pixel electrode. The closer the 15 distance from the common electrode of the CF substrate, the more similar is the equal-potential distribution diagram of the pixel electrode through another type of liquid crystal alignment control electrode formed by an insulating film. Since the liquid crystal alignment control electrode not connected to the pixel electrode yet is connected to a common electrode same potential of the corresponding substrate. 20 If a cell gap is greater than 5^m, the structure of a pixel electrode of a TFT substrate connected to the liquid crystal alignment control electrode in accordance wit the present invention almost has no effect. However, if the cell gap is below 3fim, the effect is significant. If the cell gap is below 2.5(im, a sufficiently equal-potential distribution diagram is formed for controlling the alignment of 25 liquid crystal molecules.

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Referring to Figs. 24 and 26 for planar views of Embodiment I of a TFT substrate, two types of different alignment control electrodes are formed at an upper layer of a pixel electrode, and an alignment control electrode installed at the middle of a pixel is coupled to a gate electrode and installed parallel with a 5 common electrode. Another alignment control electrode with a different alignment control is passed and disposed at a contact pad in the pixel electrode and coupled to the pixel electrode. Referring to Figs. 57 and 59 for a cross-sectional view of Embodiment 1 of the present invention, the height of alignment control electrode of the pixel electrode is increased to get closer to the 10 common electrode of the substrate as much as possible.

Referring to Figs. 8, 9 and 11 for cross-sectional views a TFT portion as depicted in Figs. 20, 24 and 26 respectively, the pixel electrode must be installed at a lower layer to form a liquid crystal alignment control electrode at an upper layer of the pixel electrode in accordance with the present invention, and thus its 15 characteristic resides on that the photolithographic procedure is used for producing a pixel electrode. Fig. 8 shows a process of using the photolithographic procedure for three times as depicted in Fig. 82. To shorten the manufacturing process, the present invention adopts a halftone exposure method, characterized in that an exposure method as shown in Figs. 67 and 68 is used for 20 producing two or more types of posiresist thicknesses after the image is developed.

In the first of the three times of photolithographic procedure ass shown in Fig. 82, a gate electrode, a pixel electrode, a common electrode and a contact pad in a pixel electrode are formed. In the first procedure, two manufacturing processes 25 exist as shown in Figs. 61 and 62, and either one of the two manufacturing

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processes can be used for forming the pixel electrode, but it is preferable to select a shorter process as shown in Fig. 61. If the thickness of the alignment control electrode as shown in Fig. 9 is reduced, and the halftone exposure method is used in the third time photolithographic procedure, it is preferable to select the process 5 as shown in Fig. 62.

Since aluminum alloy is used for making a scan line (or a gate electrode) in this invention, therefore ITO cannot be used in the pixel electrode, because a partial battery reaction will result, and the abnormal corrosion or ITO blackening issues usually occur. As a result, the pixel electrode is generally a transparent 10 electrode made of a thin film oxide such as titanium nitride or zirconium nitride.

The nitride of the transparent pixel electrode and the P - SiNxo of the gate insulating film cannot have a large selectivity for creating a contact hole by a y etching method, and the manufacturing processes of the previous embodiments as shown in Figs. 72 to 74 cannot be used anymore. To solve this problem, the 15 present invention uses an aluminum alloy series contact pad to solve the aforementioned problem.

In the second time of the photolithographic procedure, the thin film semiconductor components are separated and the contact hole is formed, and this procedure is illustrated in Fig. 63. Since this procedure also adopts the halftone 20 exposure method, therefore the procedure of the first time can be used for performing two operations. The process adopted in Figs. 11 and 26 is a halftone exposure process other than that adopted in Fig. 82, and the halftone exposure method as illustrated in Fig. 65 is used for separating the thin film semiconductor components while forming a source electrode and a drain electrode. The 25 halftone exposure process as shown in Fig. 65 is veiy similar to the halftone

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exposure process as shown in Fig. 71, but the halftone exposure process as shown in Fig. 65 is more difficult to take place. When a positive photo-resist layer at a thin area is removed by an oxygen plasma method in the foregoing embodiment as shown in Fig. 71, sidewalls of a thin film semiconductor layer are oxidized, and 5 the oxidization takes place easily at the time of removing an ohmic contact layer (n+a - silicon layer) of a channel portion of the thin film transistor component, but an even removal cannot be achieved. In the situation as shown in Fig. 65, the thin film semiconductor layer is protected by a metal barrier layer completely when the positive photo-resist layer at the thin area is removed by the oxygen 10 plasma method, and thus the oxidization almost will not take place at the sidewalls.

In the third photolithographic procedure as shown in Fig. 82, an exposure method is generally used for forming a source electrode, a drain electrode and an alignment control electrode as shown in Fig. 8. In Fig. 9, the third 15 photolithographic procedure also adopts a photolithographic procedure that uses a halftone exposure method as shown in Fig. 64.

In Figs. 8, 9 and 20, the third photolithographic procedure is used for forming two different types of alignment control electrodes at an upper layer of the pixel electrode through the insulating film. In Fig. 11, a fourth photolithographic 20 procedure is used for forming two different types of alignment control electrodes, such that an oblique direction of vertical alignment negative dielectric constant anisotropic liquid crystal molecules as shown in Figs. 3 and 5.

In Figs. 8, 9 and 20, a passivation film is a P - SiNx film formed partially by using a CVD method. An ink-jet printing method or a plate offset printing 25 method is sued to coat a passivation film made of an organic compound such as

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BCB. The shortcoming of the process shown in Fig. 11 resides on that a short circuit may occur easily at the common electrode of the corresponding substrate when two different types of alignment control electrodes are formed on the passivation film.

Referring to Figs. 25 and 27 for planar views of Embodiment 2 of TFT substrate in accordance with the present invention, a slit is formed on the pixel electrode for the alignment control, and a liquid crystal alignment control electrode connected to the pixel electrode is formed at an upper layer of the pixel electrode through the insulating film. Referring to Figs. 58 and 60 for cross-sectional views of Embodiment 2 of a pixel, Embodiment 2 similar to Embodiment 1 also installs the alignment control electrode connected to the pixel electrode at a position proximate to the substrate, and thus its characteristic resides on that each type of electrodes and semiconductor layers is installed at a lower layer of the alignment control electrode.

Embodiments 1 and 2 of the present invention include all alignment control functions at the TFT substrate side. Compared with the previous methods as shown in Figs. 1 and 2, the methods adopted by the present invention as shown in Figs. 3 and 4 also have the existing short-circuit problem at the same layer of a video signal line while the alignment control electrode is being formed. Therefore, the pixel structures as shown in Figs. 24 to 27 are avoided, and a structure having a curvature of 90 degrees at the center of the pixel is used instead. The video signal line and the alignment control electrode of this structure are arranged in parallel and equidistantly with each other, so as to reduce the chance of having a short circuit.

Referring to Figs. 10, 12 and 21 for cross-sectional views of the TFT portions

as shown in Figs. 21, 25 and 27 respectively, the basic principle of the Embodiment 2 as illustrated in Figs. 5 and 6 adopts an alignment control slit for determining the oblique direction of the liquid crystal molecules correctly, but Embodiment 1 cannot increase the strength of electric field as Embodiment 1 does.

5 Therefore, the response rate of Embodiment 2 is slower than that of Embodiment 1. In the application of displaying animations, it is appropriate to adopt Embodiment 1 for the manufacture of LCD panels. From the planar views as shown in Figs. 24 and 26, many metal wires are installed densely on the same layer in Embodiment 1, and thus the existing short circuit problem may occur 10 easily. In addition to the short-circuit issue, the voltage applied to the pixel electrode of Embodiments 1 and 2 is not 100% applied to the liquid crystal layer, and thus the shortcoming of requiring a higher driving voltage as shown in Figs. 1 and 2 still exists. Since the CF substrate can use a low-cost CF substrate which has about the same cost of TN, therefore the product competitiveness can be 15 improved. Particularly, it is not necessary to use a field order driven LCD panel of the CF substrate, which must align the upper and lower substrates as shown in Figs. 1 and 2, but the present invention does not need any manufacture on the substrate as shown in Figs. 3 and 4. Such arrangement simply needs to form a substrate with a transparent electrode film, and requires no adjustment of 20 alignment theoretically.

Referring to Figs. 28 to 31 for planar views of the TFT substrate in accordance with Embodiment 3 of the present invention and Fig. 32 for a circuit model of the TFT substrate of the invention, a basic unit pixel is divided by the video signal line into two sub pixels: sub pixel A and sub pixel B. The ratio of areas of the 25 sub pixel A to the sub pixel B is approximately equal to 1:2. Fig. 34 shows a

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driving signal waveform of an LCD panel in accordance with Embodiment 3 of the present invention. Even though the data is obtained from the same video signal line, the phase is changed by different common electrode as shown in Fig. 34, since each pixel electrode is combined with a capacitor of a different common 5 electrode, and a horizontal period (H period) is applied, and the waveform of a signal with an opposite polarity maintains the effective voltage of the sub pixel A greater than the effective voltage of the sub pixel B. Fig. 33 shows the quantity of light transmission of the LCD panel when the signal waveform is driven, and the threshold voltage of the liquid crystals of the sub pixel A and the sub pixel B 10 can be changed for correcting y.

Fig. 83 shows the process of manufacturing the TFT substrates as illustrated in Figs. 28 to 31, and Fig. 82 illustrates Embodiments 1 and 2. A common electrode is manufactured in the first the photolithographic procedure. In Embodiment 3 as shown in Fig. 32, it is not necessary to arrange the video signal 15 line in parallel with the common electrode, and thus the common electrode is manufactured by the third photolithographic procedure as shown in Fig. 83.

Fig. 35 shows a circuit model of the TFT substrate when a high-precision super large LCD panel is manufactured. Figs. 36 to 39 show the method of driving a TFT substrate as illustrated in Fig. 35. Figs. 36 to 39 relate to the field order 20 driving method. Since the display screen is divided into two: an upper screen and a lower screen, therefore the video signal line is also divided into two: an upper video signal line and a lower video signal line, and the video signals of the same polarity are applied.

The common electrode has not been divided into two, but both upper and 25 lower portions integrated. Figs. 36 and 38 show that video signals are written

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from the center of the screen to the upper and lower screens in order to prevent the blocks of the upper and lower screens from being separated. Figs. 37 and 39 show the video signals are written from the upper and lower screens onto the center of the screen. To divide the display screen into two, the horizontal scan 5 period is extended to two times of 2H. Figs. 36 and 37 show that the horizontal scan period is divided into two, such that different video signals can be written for two pixels by two different multitasking methods. Figs. 38 and 39 show that the horizontal scan period is divided into three, such that different video signals can be written for three pixels by three multitasking methods.

10 Referring to Figs. 53 and 45 for a planar view and a cross-sectional view of an IPS TFT substrate in accordance with Embodiment 4 of the present invention, and Fig. 84 for the manufacturing process of an IPS TFT substrate in accordance with Embodiment 4 of the present invention, three times of photolithographic procedure adopting three times of halftone exposure method are conducted. Fig.

15 46 shows a circuit model of a TFT substrate as illustrated in Fig. 53. The center of a pixel and the video signal are arranged in parallel with the common electrode. Fig. 56 shows a circuit model of a TFT substrate when a high-precision supper large LCD panel is manufactured. Fig. 55 shows a driving waveform diagram of a TFT substrate as illustrated in Fig. 56. Signal waveforms of different polarities

20 are applied on even-numbered rows and odd-numbered rows, and signal waveforms of different polarities are applied to the even-numbered rows and odd-numbered row of video signal waveforms, and a signal with an opposite polarity is applied to the common electrode of each corresponding video signal line.

25 Even the modes of liquid crystals are different, the circuit models of the

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common electrode and the video signal line is identical to those as shown in Fig. 35. The IPS TFT substrate as shown in Fig. 56 can also adopt the same field order driving method of Embodiment 3. Similar to the process as shown in Fig. 35, the process as shown in Fig. 56 divides the display screen into two: an upper 5 screen and a lower screen, and thus the video signal line is also divided into two: an upper video signal line and a lower video signal line, and the polarity of video signals are the same.

The common electrode has not been divided into two, but it is connected from top to bottom as a whole. To prevent the blocks of upper and lower screens from 10 being separated, the video signals are written from the center of the screen upward or downward, or the video signals are written from the top or bottom of the screen towards the center of the screen. The driving method for the scan lines is identical to that of Embodiment 3.

Referring to Figs. 54 and 44 for a planar view and a cross-sectional view of a 15 FFS TFT substrate in accordance with Embodiment 5 of the present invention respectively, Fig. 47 for a cross-sectional view of a portion of a thin film transistor, and Fig. 85 for the manufacturing process of a FFS TFT substrate in accordance with Embodiment 5 of the present invention, the photolithographic procedure is conducted for three times, and a halftone exposure method is applied for all of the 20 three times. The three times of Embodiments 4 and 5 H 3 use the halftone exposure method as shown in Fig. 66. Unlike the vertical alignment LCD panel, a horizontal electric field panel requires different alignment processing procedure (such as the friction processing). To prevent having a poor alignment area, it is necessary to minimize the roughness of the TFT substrate. However, the planar 25 views of Figs. 53 and 54 show that the thickness of electrodes is increase to lower

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the resistance of a common electrode at the center of the screen.

Since a poor alignment area as shown in Fig. 66 must occur in both IPS and FFS modes, therefore the shortcoming of unable to show the black color for a black potential exists. To minimize the poor alignment area, it is necessary to 5 apply the halftone exposure method for three times.

Figs. 61 and 62 use the manufacturing process as illustrated in Fig. 85, the process of the halftone exposure method is applied for one time, and any one can be selected. Fig. 63 illustrates the process of applying the halftone exposure method for the second time, and Fig. 64 illustrates the process of applying the 10 halftone exposure method for three times, and Fig. 65 illustrates the process of performing the photolithographic procedure for four times for manufacturing the FFS TFT substrate. The halftone exposure method is applied for two times.

Even if the FFS TFT substrate as shown in Fig. 54 adopts the same driving method as the IPS TFT substrate as shown in Fig. 53, all circuit models of the TFT 15 substrate as shown in Fig. 56 can be applicable for the FFS mode of Fig. 54. If the driving method of Fig. 55 is used, the FFS mode with a high driving voltage can be driven easily. Since the FFS mode can produce a strong electric field, therefore the response rate of the liquid crystal molecules is smaller than that of the IPS mode and applicable for the field order driving method. Particularly, a 20 high voltage can be applied to the LCD panels as shown in Figs. 55 and 56, and thus such method is considered as a driving method applicable for high-speed operations, and most suitable for the field order driving method for the divided upper and lower screens as shown in Figs. 36 to 39.

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KEY TO THE DRAWINGS

Fig. 82

MVA Mode Using a Photolithographic Procedure for Three Times (A)

(1) Form a gate electrode, a pixel electrode, a common electrode and a contact pad in the pixel electrode (wherein the photolithographic procedure uses a halftone exposure method for the first time).

(2) Form a separate thin film semiconductor layer component, and a contact hole (wherein the photolithographic procedure uses a halftone exposure method for the second time).

(3) Form a source electrode, a drain electrode and an orientation control electrode (wherein the photolithographic procedure uses a general exposure method).

After an ohmic contact layer of a channel portion of the thin film transistor is dry etched, a partial film of a passivation layer is formed by a silicon nitride film by using a mask deposition method (wherein the film is formed at a terminal portion other than those of a gate electrode, a source electrode and a common electrode).

Fig. 83

MVA Mode Using a Photolithographic Procedure for Three Times (B1 (1) Form a gate electrode, a pixel electrode and a contact pad in the pixel electrode (wherein the photolithographic procedure uses a halftone exposure method for the first time).

(3) Form a source electrode, a drain electrode, an orientation control electrode and a common electrode (wherein the photolithographic procedure uses a general exposure method).

After an ohmic contact layer of a channel portion of the thin film transistor is dry

etched, a partial film of a passivation layer is formed by a silicon nitride film by using a mask deposition method (wherein the film is formed at a terminal portion other than those of a gate electrode, a source electrode and a common electrode).

Fig. 84

IPS Mode Using a Photolithographic Procedure for Three Times (C)

(1) Form a gate electrode, a comb pixel electrode, a common electrode for shielding a video signal line (or a source electrode), a contact pad in the pixel electrode, and a video signal line for shielding the contact pad in common electrode (wherein the photolithographic procedure uses a halftone exposure method for the first time).

(3) Form a source electrode (or video signal line), a drain electrode, a common electrode at the center of a pixel and a comb common electrode (wherein the third time of photolithographic procedure uses a halftone exposure method).

FFS Mode Using a Photolithographic Procedure for Three Times (D)

(1) Form a gate electrode, a pixel electrode and a contact pad in the pixel electrode (wherein a first time of applying the photolithographic procedure adopts a halftone exposure method).

(2) Form a separate thin film semiconductor layer component, and a contact hole

Fig. 85

(wherein a second time of applying the photolithographic procedure adopts a halftone exposure method).

(3) Form a source electrode (or a video signal line), a drain electrode, a common electrode at the center of a pixel and a comb common electrode (wherein a third time of applying the photolithographic procedure adopts a halftone exposure method).

3l1

Claims

CLAIMS What is claimed is:

1. An active matrix vertical alignment liquid crystal display apparatus, comprising:

a transparent pixel electrode;

a slit for liquid crystal alignment control formed thereon;

an insulating film formed thereon; and a liquid crystal alignment control electrode formed thereon on a TFT substrate, wherein the liquid crystal alignment control electrode has same potential as the transparent pixel electrode.

2. The active matrix vertical alignment liquid crystal display apparatus of claim 1, wherein the liquid crystal alignment control electrode connects to the same potential as the transparent pixel electrode.

3. The active matrix vertical alignment liquid crystal display apparatus of claim 1 or 2, further comprising a video signal line and a scan line, wherein the video signal line, the transparent pixel electrode and the liquid crystal alignment control electrode are bent 90 degrees at a proximate position of a center of the transparent pixel electrode, and they are aligned to the scan line that serves as a central line at an approximate angle of - 45 degrees or + 45 degrees.

ao

3. The active matrix vertical alignment liquid crystal display apparatus of claim 1 or 2, further comprising a video signal line and a scan line, wherein the video signal line, the transparent pixel electrode, the liquid crystal alignment control electrode are bent 90 degrees more than once at a proximate position of a center of the transparent pixel electrode, and are aligned to the scan line in ±45 degrees.

Amendments to the claims have been filed as follows

What is claimed is:

a transparent pixel electrode (5);

a slit (6) for liquid crystal alignment control formed on one side of the transparent pixel electrode (5);

an insulating film (8) of a TFT substrate formed on another side of the transparent pixel electrode (5); and a liquid crystal alignment control electrode formed on the insulating film (8),

wherein the liquid crystal alignment control electrode has the same potential as the transparent pixel electrode.