GB2456406A - Residue calculation in modulo system using 4:2 counter - Google Patents
Residue calculation in modulo system using 4:2 counter Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/727—Modulo N arithmetic, with N being either (2**n)-1,2**n or (2**n)+1, e.g. mod 3, mod 4 or mod 5
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Abstract
A residue of an operand with a width of n bits with respect to a modulo m where m=2b-1, can be calculated by partitioning the operand into segments, each of b bits starting with the Least Significant Bit (LSB). The segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24) The adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (In1, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each. the first level (22) are grouped in fours, such that the propagate outputs (43) are ring like connected with the propagate inputs (44), and that the first to fourth inputs (In1, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (In1), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process. This leads to a reduction in the area needed on the chip to make the calculation, relaxes the timing requirement, as the calculation requires fewer logical levels, and increases the error detection rate for a single random type of operation.
Description
- i - 2456406
DESCRIPTION
Apparatus comprising •?. reduction tree for calculation of a residue of an operand
Technical field
The present invention relates to residue generation and error detection within a floating-point unit of a microprocessor. More particularly the invention relates to error detection of floating point number operations within a floating-point unit of a microprocessor, wherein an appropriate residual generation like e.g. modulo3 or modulol5 is carried out.
Background of the invention
A floating-point unit of a microprocessor comprises a residue generating and error-detecting apparatus, which performs residue checking for error detection on floating-point operations, which may be addition, subtraction, multiplication, divide, square root or convert operations. Thereby, as part of e.g. residue modulo3 checking, the residue modulo3 remainder has to be built of the involved data operands. This is implemented in form of a so-called counter tree.
From US 4,538,237 a method and apparatus for calculation the residue of a binary number or operand of n bits with respect to a given check base m where m=2b-l. Thereby m=31 and b=5 is used. The binary number is partitioned into segments, each of b bits starting with the Least Significant Bit (LSB). If n is not an even multiple of b, higher order bit positions of the segment containing the Most Significant Bit (MSB) of the number are filled with logical zeros. The segments are applied to levels of carry save adders to reduce the segments of the binary number to
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a single sum segment of b bits and a single rotated carry segment of b bits where a rotated carry segment is a carry segment produced by a carry -savp artrtpr; the MSB of which is rotated so that it becomes the LSB of the rotated carry segment. Carry segments produced by carry save adders of one level or stage are converted to rotated carry segments before being applied to a carry save adder of a lower level carry save adder, i.e. from the point of view of an operand register providing the binary number before being applied to a carry save adder of a higher stage carry save adder. The single sum segment and single rotated carry segment produced by the lowest level carry save adder are applied to a l's complement full adder. The b bit output of the l's complement full adder is the residue of the binary number with respect to the check base m with m=2b-l.
From US 4,926,374 a residue checking apparatus is known which uses common circuitry to conduct residue checking of the outcome of an arithmetic operation, which may be an addition, a subtraction, a multiplication, a divide or a square root operation.
A state of the art modulo3 counter tree 01 is shown in Fig. 1. Registers of an operand register 02 carry 32 bits of an operand, in the following called 32-Bit-operand, starting with the MSB in the register indicated with '0' on the left, and ending with the LSB in the register indicated with '31' on the right. The counter tree 01 comprises five stages 04, 05, 06, 07, 08, a first stage 04 with modulo3 decoders 03 and second to fourth stages 05, 06, 07, 08 with modulo3 adders 09. The operand is divided into p=16 segments of two bits each with a number of segment bits b=2 in order to get a modulo base m=3. Thus the bit width w of the operand is w=p*b and the modulo base m is m=2b-l. Modulo3 decoders 03 are connected with the registers of the operand register 02 in a way that each modulo3 decoder 03 is connected with two adjacent register bits of the operand
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register 02 for receiving in parallel two bits of numerical data each, wherein each register bit of the operand register 02 is connected with one juodulo3 decodcr 03. Thus, £c * 32-Bit-operand having an operand width of w=32 p=16 modulo3 decoders 03 are required. Every adjacent pair of modulo3 decoders 03 of the first stage is connected with a modulo3 adder 09 in the second stage. Any adder 09 of the following stages 06, 07, 08 is connected with two adders 09 of the previous stage until in the last stage 08 only one adder 09 is arranged. Thus the counter tree 01 comprises sixteen modulo3 decoders 03 plus fifteen modulo3 adders 09.
Such a modulo3 counter tree for a 16-Bit-operand is known from US 4,190,893.
A state of the art modulol5 counter tree 10 shown in Fig. 2 has a similar complex architecture with four instead of five stages. Thereby each modulol5 decoder is connected with four adjacent registers of the operand register for receiving in parallel four bits of numerical data each. According to m=2b-l a number of segment bits b=4 is required to receive a modulo base m=15. According to w=p*b the number of segments p=8 in combination with an operand with an operand width w of w=32.
Summarized, according to the state of the art, in the beginning of the residual creation, a decoding of the operand has to be performed. This is disadvantageously, since such a decoding has to be performed p-times, depending on the width of the operand, leading to additional disadvantages of the state of the art.
Object of the invention
It is thus an object of the invention to develop an improved method and apparatus for calculation the residue of a binary
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number or operand of w bits with respect to a given check base m, i.e. modulo base.
Summary of the invention
The shortcomings of the prior art are overcome and additional advantages are provided by an apparatus for calculation the residue of an operand with a width of n bits with respect to a given check base i.e. modulo m where m=2b-l, wherein the operand is partitioned into segments, each of b bits starting with the Least Significant Bit (LSB), wherein the segments are applied to a counter reduction tree comprising levels of adders. The adders of a first level of the counter tree below an operand register with successive registers keeping the successive bit positions of the operand are 4:2 counters. The 4:2 counters have four inputs plus a propagate input each. The 4:2 counters have also a carry and a sum output plus a propagate output each. Every four 4:2 counters of the first level are grouped in a way that propagate outputs of the 4:2 counters are ringlike connected with propagate inputs of the 4:2 counters. The first to fourth inputs of the of the 4:2 counters are connected with successive registers of said operand register such that the first inputs of the of the 4:2 counters are connected with four successive registers in ascending order followed by the second, third and fourth inputs. According to the invention a decoding is performed only one time at the end of the residue generation process, i.e. at the end of the counter reduction tree.
The ringlike arrangement of at least one group of four 4:2 counters provides a feedback among the counters which allows to group four of them physically and thus to reduce area requirements.
An advantage of the invention over the state of the art is that the time consuming decoding has to be performed less times. Thus
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compared to the state of the art the apparatus according to the invention is faster.
According to a preferred embodiment of the invention, the segments have a width of b=4 bits so that the content of four successive segments is applied on four counters, wherein starting with a less significant bit position of the operand, the first bit positions of said four successive segments are applied on successive inputs of a first counter, the second bit positions of said four successive segments are applied on successive inputs of a second counter, the third bit positions of said four successive segments are applied on successive inputs of a third counter and the fourth bit positions of said four successive segments are applied on successive inputs of a fourth counter.
If n is not an even multiple of b, preferably higher order bit positions of the segment containing the Most Significant Bit (MSB) of the operand are filled with logical zeros.
Preferably the adders of a second level are 4:2 counters too, wherein every four counters of the second level are grouped in a way that the propagate outputs are ringlike connected with the propagate inputs.
Preferably it applies for the inputs of the 4:2 counters as well of the first as of the second level that all four inputs of each counter have the same value, i.e. that they match the same modulo residue.
According to a preferred embodiment of the invention, a residue information generated by the levels of adders is reduced to eight bits, which can be used in different ways for a further processing in a control logic according to the state of the art, and which are to be used to check a related operation. The
residue number representation preferably is reduced to eight signals, i.e. bits, which can be differently handled in a control logic in order Lu check a related operation. By redoing the residue information to eight bits the checking which is not part of the present invention can be done in different ways.
According to another preferred embodiment of the invention, a 4:2 counter is implemented with two 3:2 counters comprising three inputs plus two outputs each, connected in a way that the three inputs of a first 3:2 counter form three successive inputs of the four successive inputs of said 4:2 counter, starting with the most significant input, wherein the carry output of the first 3:2 counter forms the propagate output of said 4:2 counter and the sum output of the first 3:2 counter is connected with the most significant input of the second 3:2 counter, wherein the least significant input of the second 3:2 counter forms the propagate input of said 4:2 counter and the fourth and least significant input of said 4:2 counter is formed by the middle input of said second 3:2 counter, and wherein the outputs of the second 3:2 counter are the carry and the sum outputs of said 4:2 counter.
According to a particular preferred embodiment of the invention, a modulol5 residue generation is performed. The invention has the advantage over the state of the art that it performs a modulol5 residue generation with a partial data reduction tree, which compared to the state of the art is faster and smaller and needs less design effort.
According to an additional preferred embodiment of the invention, 32-Bit-operands are processed. Surprisingly the invention performs best with 32-Bit-operands. Thereby in combination with 32-Bit-operands it seems to exist an optimum.
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The foregoing, together with other objects, features, and advantages of this invention can be better appreciated with rcfcrcncc to the following specificatiop. claims and drawings.
Brief description of the drawings, with:
Fig. 1 schematically showing a modulo3 counter tree according to the state of the art.
Fig. 2 schematically showing a modulol5 counter tree according to the state of the art.
Fig. 3 schematically showing a modulol5 counter tree according to the invention.
Fig. 4 schematically showing the design of a 4:2 counter.
Detailed description of the drawings
An apparatus 20 for calculation the residue of an operand with a width of 32 bits with respect to a given check base of modulol5 is shown in Fig. 3. The apparatus 20 comprises a counter reduction tree 21 comprising levels 22, 23 of adders 24. The apparatus 20 further comprises an operand register 25 with successive registers keeping the successive bit positions of the operand. The operand is partitioned into segments, each of four bits starting with the LSB on the right, indicated by 31. The segments are applied to the counter reduction tree 21. The adders 24 of the counter tree 21 of the first level 22 below the operand register 25 are 4:2 counters 24. The 4:2 counters 24 have four inputs plus a propagate input each. The 4:2 counters 24 have also a carry and a sum output plus a propagate output each. Every four 4:2 counters 24 of the first level 22 are grouped in a way that propagate outputs of the 4:2 counters 24 are ringlike connected with propagate inputs of the 4:2 counters 24. The first to fourth inputs of the of the 4:2 counters are
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connected with successive registers of said operand register 25 such that the first inputs of the of the 4:2 counters 24 are connected with four successive registers in ascending order followed by the second, third and fourth inputs. According to the invention a decoding is performed only one time at the end of the residue generation process, i.e. at the end of the counter reduction tree 21.
Thereby decoding is the transforming of coded signals, which preferably have a binary format, into undecoded signals, which preferably are explicit modulo remainders, according to a decoding table. An example of a decoding table for modulo3 according to the state o the art is represented by table 1.
By performing the decoding at the end of the counter reduction tree 21 the time consuming decoding has to be performed only one time. Thus compared to the state of the art the apparatus 20 according to the invention is faster.
To do so, a residue information generated by the levels 22, 23 of adders 24 is reduced to eight bits, which can be used in different ways for a further processing in a control logic according to the state of the art, and which are to be used to check a related operation. The residue number representation preferably is reduced to eight signals, i.e. bits, which can be differently handled in a control logic in order to check a related operation. By reducing the residue information to eight bits the checking which is not part of the present invention can be done in different ways.
The ringlike arrangement of four 4:2 counters 24 provides a feedback among the counters 24 which allows to group four of them physically and thus to reduce area requirements.
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The segments have a width of four bits so that the content of four successive segments is applied on four counters 24 of the first level 22, wherein starting with a less significant bit position of the operand, the first bit positions of said four successive segments are applied on successive inputs of a first counter 24 indicated Ml, the second bit positions of said four successive segments are applied on successive inputs of a second counter 24 indicated M2, the third bit positions of said four successive segments are applied on successive inputs of a third counter 24 indicated M3 and the fourth bit positions of said four successive segments are applied on successive inputs of a fourth counter 24 indicated M4.
Preferably the adders 24 of a second level 23 are 4:2 counters 24 too, wherein every four counters 24 of the second level 23 are grouped in a way that the propagate outputs are ringlike connected with the propagate inputs.
A 4:2 counter 24 preferably is implemented with two 3:2 counters 4.0 as shown in Fig. 4. Each 3:2 counter 40 comprising three inputs plus two outputs each, connected in a way that the three inputs of a first 3:2 counter 41 form three successive inputs inl, In2, In3 of the four successive inputs of said 4:2 counter 24, starting with the most significant input Inl, wherein the carry output of the first 3:2 counter 41 forms the propagate output 43 of said 4:2 counter 24 and the sum output of the first 3:2 counter 41 is connected with the most significant input of the second 3:2 counter 42, wherein the least significant input of the second 3:2 counter 42 forms the propagate input 44 of said 4:2 counter 24. The fourth and least significant input In4 of said 4:2 counter 24 is formed by the middle input of said second 3:2 counter 42. The outputs of the second 3:2 counter 42 are the carry and the sum outputs 45, 46 of said 4:2 counter 24. Implementing a 4:2 counter 24 with two 3:2 counters 40 results in a simple logic table for the 3:2 counters and thus in a low
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logic depth. An example of a logic table for the 3:2 counter 41 is represented by table 2.
It is important to mention that it applies for the inputs of the 4:2 counters as well of the first as of the second level that all four inputs of each counter have the same value, i.e. that they match the same modulo residue. As an example the M8 4:2 counter 24 of the second level 23 indicated by 'M8' is considered (Fig. 3, with respect to Fig. 4). The inputs Inl, In2, In3, In4 of this counter 24 are connected with the sum outputs 46 of the M8 4:2 counters 24 of the first level 22 and with the carry outputs 45 of the M4 4:2 counters 24 of the first level 22. Thus each input signal of the M8 4:2 counter 24 of the second level 23 has the value 'modulo residue 8'. This also applies for the M4, M2, Ml 4:2 counters 24 of the second level 23.
Advantages of the invention over the state of the art are:
Small area required for residue generation, since e.g. a modulo 15 implementation using 4:2 counters according to the invention needs only area in the same range as for modulo 3 according to the state of the art and thus is much smaller than the area requirement for a state of the art modulol5 implementation.
Relaxed timing requirement, since the so-called FanOut4 delay on two 4:2 counters is around 2x4=8, compared to a delay of 2+4x2=10 for decode plus four times Add for a modulo3 implementation according to the state of the art. In other words the logic depth or complexity of an implementation according to the invention is lower than needed for a state of the art solution.
- The error detection rate is increased from range of 66.7% with modulo3 to range of 93.3 % with modulolS, assuming a single random-type of operation. Thus with only the same
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area requirement like a modulo3 implementation according to the state of the art, a modulol5 implementation according to the invention provides an almost 50% increased area specific error detection rate.
- Less custom design effort, since 4:2 counters can be used, which are typically available in a floating-point unit.
- No special tuning required, since relaxed timing requirement.
- Blocks of 4 x 4:2 counters can be reused for custom design.
It is important to mention, that the following generalizations of the invention are possible:
- The invention may not be limited to floating-point calculation, but also be used on binary or decimal operations.
- The invention is not limited to a data width of 32/64/128 and modulo 15.
It is optimal for data width of w=2n with n=4,5,6,7,.. leading to w=16,32,64,128,256, . .
- It is of advantage on modulo values m=2b-l with b=2,3,4,5,6,7,8,.. leading to m=3,7,15,31,63,127,255,..
- Most optimal are structures with b=2c and m=2b-l, wherein c=l,2,3,.. leading to m=3,15,255 ..., allowing structures as shown in Fig. 3 for modulol5.
While the present invention has been described in detail, in conjunction with specific preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
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Claims (9)
1. Apparatus (20) for calculation of •? rpsidue of an operand with a width of n bits with respect to a modulo m where m=2b-l, wherein the operand is partitioned into segments, each of b bits starting with the Least Significant Bit (LSB), wherein the segments are applied to a counter reduction tree (21) comprising levels (22, 23) of adders (24), characterized in that the adders (24) of a first level (22) below an operand register (25) with successive registers keeping the successive bit positions of the operand are 4:2 counters (24) having four inputs (Inl, In2, In3, In4) plus a propagate input (44), a carry and a sum output (45, 46) plus a propagate output (43) each, wherein every four counters (24) of the first level (22) are grouped in a way that the propagate outputs (43) are ringlike connected with the propagate inputs (44), and that the first to fourth inputs (Inl, In2, In3, In4) of the counters (24) are connected with successive registers of said operand register (25) such that first inputs (In4) of the counters (24) are connected with four successive registers in ascending order followed by second (In3), third (In2) and fourth inputs (Inl), wherein a decoding is performed only one time at the end of the counter tree (21) and thus at the end of the residue generation process.
2. Apparatus according to claim 1, characterized in that the secrments have a width of four bits so that the content of four successive segments is applied on four counters (24), wherein starting with a less significant bit position of the operand, the first bit positions of said four successive segments are applied on successive inputs (Inl, In2, In3, In4) of a first counter (24; Ml), the second bit positions of said four successive segments are applied on successive inputs (Inl, In2, In3, ln4) of a second counter (24; M2), the third bit positions of said four successive segments are applied on successive inputs (Inl, In2, In3, In4) of a third counter (24; M3) and the
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fourth bit positions of said four successive segments are applied on successive inputs (Inl, In2, In3, In4) of a fourth counter (24; M4)
3. Apparatus according to claim 1 or 2, characterized in that if n is not an even multiple of b, higher order bit positions of the segment containing the Most Significant Bit (MSB) of the operand are filled with logical zeros.
4. Apparatus according to claim 1, 2 or 3, characterized in that the adders (24) of a second level (23) are 4:2 counters (24) too, wherein every four counters (24) of the second level (23) are grouped in a way that the propagate outputs (43) are ringlike connected with the propagate inputs (44).
5. Apparatus according to one of the previous claims, characterized in that the inputs (Inl, In2, In3, In4) of the 4:2 counters (24) of the first (22) and/or the second level (23)
have the same value each, so that they match the same modulo residue.
6. Apparatus according to one of the previous claims, characterized in that a residue information generated by the levels (22, 23) of adders (24) is reduced to eight bits to be used to check a related operation.
7. Apparatus according to one of the previous claims, characterized in that a 4:2 counter (24) is implemented with two 3:2 counters (40, 41, 42) comprising three inputs plus two outputs each, connected in a way that the three inputs of a first 3:2 counter (41) form three successive inputs (Inl, In2, In3) of the four successive inputs (Inl, In2, In3, In4) of said 4:2 counter (24), starting with the most significant input (Inl), wherein the carry output of the first 3:2 counter (41) forms the propagate output (43) of said 4:2 counter (24) and the
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sum output of the first 3:2 counter (41) is connected with the most significant input of the second 3:2 counter (42), wherein the least significant input of the second 3:2 counter (d?) forms the propagate input (44) of said 4:2 counter (24) and the least significant input (In4) of said 4:2 counter (24) is formed by the middle input of said second 3:2 counter (42), and wherein the outputs of the second 3:2 counter (42) are the carry and the sum outputs (45, 46) of said 4:2 counter (24).
8. Apparatus according to one of the previous claims, characterized in that a modulol5 residue generation is performed.
9. Apparatus according to one of the previous claims, characterized in that 32-Bit-operands are processed.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP08150330 | 2008-01-16 |
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| GB0822762D0 GB0822762D0 (en) | 2009-01-21 |
| GB2456406A true GB2456406A (en) | 2009-07-22 |
| GB2456406B GB2456406B (en) | 2012-02-29 |
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| GB0822762A Expired - Fee Related GB2456406B (en) | 2008-01-16 | 2008-12-15 | Apparatus comprising a counter reduction tree for calculation of a residue of an operand |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130204916A1 (en) * | 2012-02-06 | 2013-08-08 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4190893A (en) * | 1977-11-17 | 1980-02-26 | Burroughs Corporation | Modular modulo 3 module |
-
2008
- 2008-12-15 GB GB0822762A patent/GB2456406B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4190893A (en) * | 1977-11-17 | 1980-02-26 | Burroughs Corporation | Modular modulo 3 module |
Non-Patent Citations (2)
| Title |
|---|
| Computer Arithmetic 1991 Proceedings, 10th IEEE Symposium Grenoble, France, 26-28 Jun 1991, pages: 43-50, "High-speed multiplier design using multi-input counter andcompressor circuits", Mayur Mehta, Vijay Parmar, Advanced Micro Devices, ISSN: 0-8186-9151-4 * |
| ELECTRONICS LETTERS 19th February 1998 Vol. 34 No. 4, "Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers" Shen-Fu Hsiao, Ming-Roun Jiang and Jia-Sien Yeh, Available from: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=675681 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130204916A1 (en) * | 2012-02-06 | 2013-08-08 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
| US8984039B2 (en) * | 2012-02-06 | 2015-03-17 | International Business Machines Corporation | Residue-based error detection for a processor execution unit that supports vector operations |
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| Publication number | Publication date |
|---|---|
| GB2456406B (en) | 2012-02-29 |
| GB0822762D0 (en) | 2009-01-21 |
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