GB2455133A - Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces - Google Patents

Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces Download PDF

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Publication number
GB2455133A
GB2455133A GB0723435A GB0723435A GB2455133A GB 2455133 A GB2455133 A GB 2455133A GB 0723435 A GB0723435 A GB 0723435A GB 0723435 A GB0723435 A GB 0723435A GB 2455133 A GB2455133 A GB 2455133A
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Prior art keywords
signal
interface
signals
grouped
interfaces
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GB0723435A
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GB0723435D0 (en
Inventor
Alan Henry Gray
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Picochip Designs Ltd
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Picochip Designs Ltd
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Priority to GB0723435A priority Critical patent/GB2455133A/en
Publication of GB0723435D0 publication Critical patent/GB0723435D0/en
Publication of GB2455133A publication Critical patent/GB2455133A/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)

Abstract

The invention relates to a method of assigning signals to an interface. The method is for use in a system in which at least two processor arrays are interconnected by a grouped interface connection which comprises a plurality of interfaces. The method comprises analysing a set of signals that are to be transmitted across the grouped interface connection. Each of the signals having an associated bandwidth (or other characteristic), with each signal being assigned to an interface in the grouped interface connection so as to substantially balance the total bandwidth of the signals between the plurality of interfaces.

Description

SIGNAL ASSIGNMENT
Technical Field of the Invention
The invention relates to interfaces for connecting processor arrays, and in particular to the assignment of signals passing between the arrays to an interface.
Background to the Invention
Processor arrays that contain a number of separate but interconnected processing elements are known. One such processor array is the picoArrayTM architecture produced by the applicant of the present application and described in International publication WO 02/50624. In the picoArray' architecture, the processor elements are connected together by a proprietary bus that includes switch matrices.
Hardware interfaces are also known that allow multiple processor arrays to be connected together by extending the proprietary bus from one array to another. Each processor array may have several interfaces of this type, each interface connecting the processor array to another array. In addition, a single pair of processor arrays can be interconnected using two or more interfaces. This is known as a "grouped interface connection". For a picoArray" processor, the hardware interface is known as an Inter-picoArrayTM Interface (lPl).
The software description of a digital signal processing (DSP) system comprises a number of processes that communicate with point-to-multipoint signals. Each signal has a fixed bandwidth, known as its slot rate, which has a value that is a power of two in the range 2-1024, in units of the picoArrayTM cycle. Thus, a slot rate of four means that a slot must be allocated on the bus between a sending processor and the receiving processor(s) for one clock cycle out of every four system clock cycles.
A partitioning procedure can be used to allocate groups of processes to each of the processor arrays in the system. A placement procedure can be used to allocate each process to a specific processing element within its allocated processor array. A switching or routing procedure determines the multiplexing of the signals on to the physical connections of the bus in the processor array. These procedures are described in more detail in International publication WO 20041074962 to the same applicant as the present application.
Signals that connect two processes that have been allocated to different processor arrays will pass through an interface. In this case, a further procedure called assignment must take place in which i) a specific physical interface is selected to carry the signal; and ii) resources (specifically, a hardware port and transfer start offset) within the chosen physical interface are reserved for the signal.
Hardware ports are part of the bus structure and are described in more detail in WO 2004/074962 mentioned above. Transfer start offsets are the interface-specific mechanism by which multiple signals are multiplexed over a single interface connection. The interface hardware includes a memory that stores a transfer start table, which has an entry for each interface cycle (which for an lPl corresponds to two picoArrayTM processor cycles) specifying which signal the interface will send or receive during that cycle. Depending upon the slot rate of the signal to be carried, a suitable number of equally spaced entries in the memory must be allocated to the signal in order to provide it with sufficient bandwidth across the interface. The transfer start offset is the index in the table of the earliest of these entries. The number of entries in the transfer start table reserved for a given signal is called its interface utilisation, and is readily computed from its slot rate. The sum of the interface utilisations of all signals assigned to the interface is called the total utilisatiori of the interface.
lithe assignment procedure is not carried out properly, the incorrect assignment of signals to the interface can result in unnecessary delays to the processes executing on the various processor arrays. In addition, the difficulty in achieving an optimum assignment of signals increases as the number of interfaces in a system increases (and in particular where there is a grouped interface connection).
Therefore, there is a need for a procedure for assigning signals to an interface when there are multiple interfaces, and in particular grouped interface connections, in the system.
Summary of the Invention
There is provided a method for assigning signals to an interface, the method being for use in a system in which at least two processor arrays are interconnected by a grouped interface connection, the grouped interface connection comprising a plurality of interfaces, the method comprising determining a set of signals that are to be transmitted across the grouped interface connection, each signal having an associated bandwidth; and assigning each signal to an interface in the grouped interface connection so as to substantially balance the total bandwidth of the signals between the plurality of interfaces.
According to a second aspect of the invention, there is provided a method for assigning signals to an interlace, the method being for use in a system in which at least two processor arrays are interconnected by a grouped interface connection, the grouped interface connection comprising a plurality of interfaces, the method comprising: determining first and second sets of signals that are to be transmitted across the grouped interface connection, the signals in the second set each having an associated user requirement; allocating each of the signals in the second set to a respective interface in the grouped interlace connection on the basis of the associated user requirement; dividing the signals in the first set between the interfaces in the grouped interface connection on the basis of a characteristic of each signal to provide a subset of signals for each interface; and for each subset, taking each signal in the associated subset in turn, assigning the signal to the interface.
A further aspect of the invention provides a computer program comprising code that performs either or both of the methods described above when executed in a computer.
Yet another aspect of the invention provides a computer program product comprising a computer program as described above embodied therein.
Brief Description of the Drawings
The invention will now be described, by way of example only, with reference to the following drawings, in which: Figure 1 is a block diagram of an exemplary system to which the invention applies; Figure 2 is a flow chart illustrating a method of assigning signals to a single interface; Figure 3 is a flow chart illustrating a method of assigning signals to a grouped interface connection in accordance with a first embodiment of the invention; and Figure 4 is a flow chart illustrating a method of assigning signals to a grouped interface connection in accordance with a second embodiment of the invention.
Detailed Description of the Preferred Embodiments
A system 2 to which the methods and procedures described herein are applicable is shown in Figure 1. The system 2 comprises a first processor array 4 and a second processor array 6. The first and second processor arrays 4, 6 each comprise a plurality of processing elements (not shown) interconnected by a respective bus structure (also not shown). The first and second processor arrays 4, 6 are interconnected by a grouped interface connection 8 that comprises a first interface 10 and second interface 12. The interfaces 10, 12 extend the bus structure of each processor array 4, 6 so that signals can be sent between the processor arrays 4, 6.
Although two interfaces 10, 12 are shown in the grouped interface connection 8, it will be appreciated that the grouped interface connection 8 may comprise more than two interfaces. In addition, it will be appreciated that the system 2 can also include further processor arrays that are connected to one or more of the first or second processor arrays 4, 6 by a respective interface or interfaces.
In a preferred embodiment, the first and second processor arrays 4, 6 are picoArrays as described in WO 02/50624, and the interfaces 10, 12 are lnter-picoArrayTM Interfaces (IPIs). In this embodiment, the grouped interface connection is called a grouped IPI connection.
Figure 2 shows an assignment procedure for a set of signals that are to pass across a single interface between two processor arrays. In step 101, the set of signals that are to pass across the interface (in either direction) are determined. As described above, each signal will have an associated slot rate that indicates how frequently it requires a slot on the interface.
In step 103, the set of signals are then ordered by slot rate. In other words, the signals are sorted so that the fastest signals can be considered first.
In step 105, taking each signal in turn from the sorted order, a linear scan is performed to identify the first free offset in the interface that is appropriate for the slot rate of that signal.
This method will be referred to below as a sorted scan method. If there is a complete solution to the assignment of the signals to the interface, this method will find it.
Essentially, the procedures according to the invention aim to assign signals to the interfaces so as to equalise or balance the bandwidth utilisation of each of the individual interfaces 10, 12 in a grouped interface connection 8.
Figure 3 shows a first embodiment of an assignment procedure for a system 2 as shown in Figure 1 in accordance with the invention. In this embodiment, the assignment procedure proceeds automatically, and does not allow a user to impose any requirements on the assignments (such as signal X through interface Y).
In step 201, the set of signals that are to pass across the grouped interface connection 8 (in either direction) are determined. As described above, each signal will have an associated bandwidth (otherwise known as a slot rate) that indicates how frequently it requires a slot on the grouped interface connection 8.
In step 203, the set of signals are then ordered by slot rate. In particular, the signals are sorted so that the fastest signals (i.e. those that require the most slots on the grouped interface connection 8) can be considered first.
In step 205, taking each signal in turn from the sorted order, the individual interfaces 10, 12 in the grouped interface connection 8 are considered to identify the first free offset in one of the interfaces 10, 12 that is appropriate for the slot rate of that signal.
The order in which the interfaces 10, 12 in the grouped interface connection B are considered during each iteration of step 205 can be determined in a number of possible ways.
The first option is to start with the same interface 10, 12 for each signal that is to be assigned. If the signal cannot be assigned to the first interface that is considered, the procedure will try to assign the signal to the next interface to be considered. Thus, the overall effect of this option is that the first interface considered will be filled more than the second, the second more than the third, and so on, as no signal that can be assigned to the first interface considered will be assigned to any other interface. The result of using this option will normally be an unbalanced distribution of the signals across the interfaces 101 12 in the grouped interface connection 8, unless there are sufficient signals to fill each of the separate interfaces 10, 12.
The second option is to use a round-robin order to select the first interface to consider for each signal. For example, if the first signal is tried in interface 10 first, the second signal will be tried in the second interface 12 first, the third signal will be tried in the third interface first if it is present, otherwise it will be initially tried in the first interface 10, and so on. This option tries to equalise or balance the usage of all the interfaces 10, 12 in the grouped interface connection 8.
The third option is to use the interface that has the lowest total utilisation at the point at which a signal is considered. In this way, the likelihood that each of the interfaces will be filled by a substantially equal amount is increased.
Of course, it will be appreciated by a person skilled in the art that other options are possible that each have as their object the balancing of the signal bandwidth across all of the interfaces 10, 12 in the grouped interface connection 8. For example, another option could comprise selecting, as the first interface for the next signal, the next interface after the interface to which the previous signal was assigned.
As with the single interface sorted scan method described above, if there is a complete solution to the assignment of the signals to the grouped interface connection 8, the method shown in Figure 3 will find it.
Figure 4 shows a second embodiment of an assignment procedure for a system 2 as shown in Figure 1 in accordance with the invention. In this embodiment, the assignment procedure allows a user to impose requirements on the assignments (such as signal X through interface Y). The methods described above cannot be used in this embodiment, as it may not be possible to meet the requirements of the user.
In the method presented below, the user requirements are assumed to take priority over the decisions otherwise made by the procedure.
In step 301, the set of signals that are to pass across the grouped interface connection 8 (in either direction) are determined. As described above, each signal will have an associated slot rate that indicates how frequently it requires a slot on the grouped interface connection 8. In addition, one or more signals will be subject to a user requirement that the signal or signals are assigned to a particular interface 10, 12.
In step 303, the set of signals is divided into subsets, one subset for each available interface 10, 12, by assigning the signals subject to the user requirements to the appropriate subset for that signal.
In step 305, the remaining signals (i.e. those that are not subject to user requirements) are each allocated to one of the subsets. The signals can be allocated to a particular subset based on an estimate of whether the signal will fit over the interface 10, 12 using a round-robin technique or by considering the total utilisation of the various i(IteIfdces 10, 12. Of course, at will be appreciated that other methods could be used here.
In step 307, the sorted scan method shown in Figure 1 is executed for each subset of signals to assign the signals to the appropriate start transfer offset position in the interface 10, 12.
As the procedure in Figure 4 guarantees the use of the user requirements, the procedure cannot guarantee to find a complete solution to the assignment of signals to the interfaces 10, 12 if such a solution exists (in the absence of the user requirements), since a user requirement may prevent the solution being realised. Moreover, even if a complete solution does exist after taking into account the user requirements, there is no guarantee that the procedure will find it, as the allocation of signals to subsets in step 305 is based on an estimation rather than an exact algorithm, and it is possible that the estimation will not result in the appropriate distribution of signals to subsets.
There is therefore provided a procedure for assigning signals to an interface when there are multiple interfaces, and in particular grouped interface connections, in the system.
Although the invention has been described in the form of a method, it will be appreciated that the invention can be embodied as a computer program or as suitably programmed hardware.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.
Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Claims (21)

  1. Claims 1. A method for assigning signals to an interface, the method being for use in a system in which at least two processor arrays are interconnected by a grouped interface connection, the grouped interlace connection comprising a plurality of interfaces, the method comprising: determining a set of signals that are to be transmitted across the grouped interface connection, each signal having an associated bandwidth; and assigning each signal to an interlace in the grouped interface connection so as to substantially balance the total bandwidth of the signals between the plurality of interfaces.
  2. 2. A method as claimed in claim 1, wherein the step of assigning comprises, for each signal, considering the interfaces in the grouped interface connection in sequence, and assigning the signal to the first considered interface that is suitable for the bandwidth of that signal.
  3. 3. A method as claimed in claim 2, wherein the sequence of interfaces for a particular signal starts with the interface immediately following the first interlace considered for the preceding signal.
  4. 4. A method as claimed in claim 2, wherein the sequence of interfaces for a particular signal starts with the interlace immediately following the interface to which the preceding signal was assigned.
  5. 5. A method as claimed in claim 2, wherein the sequence of interfaces for a particular signal starts with the interlace in the plurality of interfaces that has the lowest total bandwidth allocated thereto.
  6. 6. A method as claimed in any preceding claim, wherein, prior to the step of assiqning, the method further comprises the step of: arranging the signals in the set into an order based on the bandwidth required by each signal.
  7. 7. A method as claimed in claim 6, wherein the step of assigning comprises considering each signal in the arranged set in turn.
  8. 8. A method as claimed in claim 7, wherein the bandwidth of the signal is represented by a slot rate of the signal.
  9. 9. A method as claimed in claim 6, 7 or 8, wherein the step of arranging comprises arranging the signals so that the signals with the highest bandwidth are considered first during the step of assigning.
  10. 10. A method as claimed in any preceding claim, wherein the step of assigning comprises finding the first free offset on an interface in the grouped interface connection for the associated bandwidth of the signal.
  11. 11. A method as claimed in any preceding claim, wherein the interfaces are Inter-picoArray Interfaces, IPI.
  12. 12. A method as claimed in claim 11, wherein the grouped interface connection is a grouped IPI connection.
  13. 13. A method for assigning signals to an interface, the method being for use in a system in which at least two processor arrays are interconnected by a grouped interface connection, the grouped interface connection comprising a plurality of interfaces, the method comprising: determining first and second sets of signals that are to be transmitted across the grouped interface connection, the signals in the second set each having an associated user requirement; allocating each of the signals in the second set to a respective interface in the grouped interface connection on the basis of the associated user requirement; dividing the signals in the first set between the interfaces in the grouped interface connection on the basis of a characteristic of each signal to provide a subset of signals for each interface; and for each subset, taking each signal in the associated subset in turn, assigning the signal to the interface.
  14. 14. A method as claimed in claim 13, wherein the step of assigning the signal to the interface comprises: arranging the signals in the subset into an order based on a characteristic of each signal; taking each signal in the arranged subset in turn, identifying the first free offset on the interface that is appropriate for the characteristic of that signal.
  15. 15. A method as claimed in claim 14, wherein the characteristic of each signal comprises a slot rate of the signal.
  16. 16. A method as claimed in claim 15, wherein the step of arranging compnses arranging the signals so that the signals with the highest slot rate are considered first during the step of identifying.
  17. 17. A method as claimed in claim 16, wherein the step of identifying comprises performing a linear scan of the available offsets on the interface.
  18. 18. A method as claimed in any of claims 13 to 17, wherein the interfaces are Inter-picoArray Interfaces, IPI.
  19. 19. A method as claimed in claim 18, wherein the grouped interlace connection is a grouped lPl connection.
  20. 20. A computer program comprising code that performs the method of any of claims 1 to 19 when executed in a computer.
  21. 21. A computer program product comprising a computer program as claimed in claim embodied therein.
GB0723435A 2007-11-29 2007-11-29 Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces Withdrawn GB2455133A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748629A (en) * 1995-07-19 1998-05-05 Fujitsu Networks Communications, Inc. Allocated and dynamic bandwidth management
US6195699B1 (en) * 1998-11-03 2001-02-27 Acorn Networks, Inc. Real-time scheduler method and apparatus
US20020144033A1 (en) * 2001-03-28 2002-10-03 Ragland Daniel J. Method and apparatus to maximize bandwidth availability to USB devices
GB2398651A (en) * 2003-02-21 2004-08-25 Picochip Designs Ltd Automatical task allocation in a processor array

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748629A (en) * 1995-07-19 1998-05-05 Fujitsu Networks Communications, Inc. Allocated and dynamic bandwidth management
US6195699B1 (en) * 1998-11-03 2001-02-27 Acorn Networks, Inc. Real-time scheduler method and apparatus
US20020144033A1 (en) * 2001-03-28 2002-10-03 Ragland Daniel J. Method and apparatus to maximize bandwidth availability to USB devices
GB2398651A (en) * 2003-02-21 2004-08-25 Picochip Designs Ltd Automatical task allocation in a processor array

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