GB0723435D0 - Signal aassignment - Google Patents

Signal aassignment

Info

Publication number
GB0723435D0
GB0723435D0 GBGB0723435.4A GB0723435A GB0723435D0 GB 0723435 D0 GB0723435 D0 GB 0723435D0 GB 0723435 A GB0723435 A GB 0723435A GB 0723435 D0 GB0723435 D0 GB 0723435D0
Authority
GB
United Kingdom
Prior art keywords
aassignment
signal
signal aassignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB0723435.4A
Other versions
GB2455133A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Picochip Designs Ltd
Original Assignee
Picochip Designs Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Picochip Designs Ltd filed Critical Picochip Designs Ltd
Priority to GB0723435A priority Critical patent/GB2455133A/en
Publication of GB0723435D0 publication Critical patent/GB0723435D0/en
Publication of GB2455133A publication Critical patent/GB2455133A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H04L47/125—Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
GB0723435A 2007-11-29 2007-11-29 Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces Withdrawn GB2455133A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0723435A GB2455133A (en) 2007-11-29 2007-11-29 Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0723435A GB2455133A (en) 2007-11-29 2007-11-29 Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces

Publications (2)

Publication Number Publication Date
GB0723435D0 true GB0723435D0 (en) 2008-01-09
GB2455133A GB2455133A (en) 2009-06-03

Family

ID=38962370

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0723435A Withdrawn GB2455133A (en) 2007-11-29 2007-11-29 Balancing the bandwidth used by communication between processor arrays by allocating it across a plurality of communication interfaces

Country Status (1)

Country Link
GB (1) GB2455133A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5978359A (en) * 1995-07-19 1999-11-02 Fujitsu Network Communications, Inc. Allocated and dynamic switch flow control
US6195699B1 (en) * 1998-11-03 2001-02-27 Acorn Networks, Inc. Real-time scheduler method and apparatus
US6839793B2 (en) * 2001-03-28 2005-01-04 Intel Corporation Method and apparatus to maximize bandwidth availability to USB devices
GB2398651A (en) * 2003-02-21 2004-08-25 Picochip Designs Ltd Automatical task allocation in a processor array

Also Published As

Publication number Publication date
GB2455133A (en) 2009-06-03

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)