GB2453298B - Return-to-hold switching scheme for DAC output stage - Google Patents
Return-to-hold switching scheme for DAC output stageInfo
- Publication number
- GB2453298B GB2453298B GB0900998A GB0900998A GB2453298B GB 2453298 B GB2453298 B GB 2453298B GB 0900998 A GB0900998 A GB 0900998A GB 0900998 A GB0900998 A GB 0900998A GB 2453298 B GB2453298 B GB 2453298B
- Authority
- GB
- United Kingdom
- Prior art keywords
- return
- output stage
- dac output
- switching scheme
- hold switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
- H03M1/0872—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by disabling changes in the output during the transitions, e.g. by holding or latching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
- H03M1/0682—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS using a differential network structure, i.e. symmetrical with respect to ground
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/476,476 US7307568B1 (en) | 2004-11-19 | 2006-06-28 | Return-to-hold switching scheme for DAC output stage |
PCT/US2007/071990 WO2008002858A2 (en) | 2006-06-28 | 2007-06-25 | Return-to-hold switching scheme for dac output stage |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0900998D0 GB0900998D0 (en) | 2009-03-04 |
GB2453298A GB2453298A (en) | 2009-04-01 |
GB2453298B true GB2453298B (en) | 2011-04-06 |
Family
ID=38792865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0900998A Expired - Fee Related GB2453298B (en) | 2006-06-28 | 2007-06-25 | Return-to-hold switching scheme for DAC output stage |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN101507117B (en) |
GB (1) | GB2453298B (en) |
WO (1) | WO2008002858A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9065477B2 (en) * | 2013-09-03 | 2015-06-23 | Analog Devices Global | Linear and DC-accurate frontend DAC and input structure |
US9065463B2 (en) * | 2013-10-11 | 2015-06-23 | Analog Devices Global | Method and apparatus for reducing capacitor induced ISI in DACS |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417793B1 (en) * | 2000-02-04 | 2002-07-09 | Rockwell Technologies, Llc | Track/attenuate circuit and method for switched current source DAC |
US20050156765A1 (en) * | 2004-01-21 | 2005-07-21 | Todd Kaplan | Clocked D/A converter |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE523353C2 (en) * | 2002-04-26 | 2004-04-13 | Ericsson Telefon Ab L M | Digital / Analog converter with error compensation |
AU2002255056A1 (en) * | 2002-05-27 | 2003-12-12 | Nokia Corporation | Method for calibrating a digital-to-analog converter and a digital-to-analog converter |
US6768438B1 (en) * | 2003-01-24 | 2004-07-27 | Analog Devices, Inc. | Current DAC code independent switching |
-
2007
- 2007-06-25 WO PCT/US2007/071990 patent/WO2008002858A2/en active Application Filing
- 2007-06-25 GB GB0900998A patent/GB2453298B/en not_active Expired - Fee Related
- 2007-06-25 CN CN2007800307022A patent/CN101507117B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417793B1 (en) * | 2000-02-04 | 2002-07-09 | Rockwell Technologies, Llc | Track/attenuate circuit and method for switched current source DAC |
US20050156765A1 (en) * | 2004-01-21 | 2005-07-21 | Todd Kaplan | Clocked D/A converter |
Also Published As
Publication number | Publication date |
---|---|
CN101507117B (en) | 2011-10-26 |
GB2453298A (en) | 2009-04-01 |
WO2008002858A2 (en) | 2008-01-03 |
GB0900998D0 (en) | 2009-03-04 |
WO2008002858A3 (en) | 2008-03-13 |
CN101507117A (en) | 2009-08-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20230625 |