GB2452791A - LED driver with current source and shunt path - Google Patents

Abstract

A light source array comprises at least first and second light sources L1, L2, each light source L1, L2 having a respective switch S1, S2 connected in series. The second light source L2 and second switch S2 are connected in parallel with the first light source L1 and first switch S1. The light source array may be used, for example, for illuminating a scan region on a target object, wherein light reflected from said target object is captured by a detector. A shunt path 50 comprising a switching device S4 is provided in parallel with the LED array and switching array. The shunt path 50 has the advantage of enabling the switching sequence from one LED to another to be controlled such that a substantially constant current is drained from the supply (subject to any differences in the inherent current drawn by the respective light sources).

Description

LIGHT SOURCE ARRAY AND METHOD

Technical Field

The present invention relates to a light source array and a method of controlling illumination of a light source array, for example, but not exclusively, a RGB (Red, Blue, Green) light source array

Background

Figure 1 shows a basic diagram of a state of the art LED driver circuit that is used, for example, in an image reading apparatus in conjunction with a CIS or CCD image sensor device. An LED array L1-L3 is coupled to switches S1-S3 and resistors Ri-R3.

The LED array L1-L3, switching circuit Si-S3, and resistors R1-R3 are arranged separately from the analogue front end (AFE) circuitry that is used to process image data received from the sensor device, such as a Photo Diode Array (PDA) for example.

In a colour image scanner, the LED array typically comprises Red (Li), Green (L2) and Blue (L3) LEDs Light of each colour emitted from the respective LED illuminates a portion of a target object that is to be scanned, and the light reflected by the object is incident on a sensor device. Typically, the sensor device comprises an array of sensors arranged linearly as a line image sensor, each element of the sensor array comprising a photoelectric conversion element, such as a photodiode and a capacitor for each pixel, which converts incident light into a current which is accumulated as a charge on the capacitor The respective charges accumulated on the respective capacitors are converted into respective voltages that are then output from the sensor array (PDA).

The voltages output from the PDA are converted by an Analogue to Digital Converter (ADC) into digital signals for subsequent processing during generation of the image of the target object being scanned.

The scanning of an image is usually performed using a line scanning operation. For colour images, each line is scanned by the Red, Green and Blue light sources. That is, the Red LED Li is turned on to read one line in a scanning direction, thereby obtaining the Red component of that line. The Green LED L2 is then turned on to obtain the Green component of that line, followed by the Blue LED L3 being turned on to obtain the Blue component of that line. The LED array and sensor array are then typically moved on a carriage mechanism to align with the next line on the target object. Each LED L1-L3 is turned on by switching on the respective switch S1-S3, using respective switch control signals CS1-CS3 received from a switch controller logic circuit Sc.

While one line is being scanned, image data received from the sensor array (PDA) relating to a previous line scan is read out serially and processed by the ADO.

The current flowing through each LED is defined by the current-voltage characteristics of the LED, by the resistance of the series resistor and by the voltage applied from the power supply, PSU, (the on-resistance of the switch usually being negligible).

In addition to each LED passing a respective constant current during illumination of the image, it is also known to use Pulse Width Modulation (PWM) control signals for controlling the illumination of each LED, such that the illumination or intensity of the LED can be controlled by controlling the duty-cycle and/or frequency of the PWM control signals. The current though the LED may be subject to wide variation due to tolerances of the power supply voltage and the (temperature-dependent) I- V characteristic of the LEDs The LED driver circuitry is separated from the analogue processing circuitry due to the fact that, if the switching circuitry were integrated on the same Integrated Circuit (IC) as the analogue processing circuitry, i.e. AFE, the switching circuitry would interfere with the accuracy of the ADO that is used during an image scanning process.

Such interference is caused by switching transients which occur when switching from one LED to another (e.g. from Red to Green), and/or when pulse width modulating a specific one of the LEDs (e.g. switching on and off a LED using PWM control signals).

The transient signals are coupled primarily through the supply or return ground paths, and cause inaccuracies when performing an analogue to digital conversion For example, when the analogue processing circuitry is processing data obtained from a previous scan line, transient signals generated during a current scan line will adversely affect such processing. The effect of transient current spikes is exacerbated by the inductance of bond wires connecting the integrated circuit substrate to the external (PCB) ground. Similar effects occur in both monolithic integrated circuits and, to a lesser extent, in hybrid integrated circuits.

Figures 2a-2d show the switch control signals CS1-CS3 and the supply current IS drawn from the power supply PSU in a "constant current" (i.e. non-PWM) mode. The ground current is substantially equal to the supply current.

Figure 2d illustrates how the supply current IS drops and rises during a switchover from one LED to another in the circuit of Figure 1, thereby causing unwanted transient signals that can affect the analogue to digital data processing.

Figures 2e-2h show the switch control signals CS1-CS3 and the supply current IS drawn from the power supply in PWM mode.

Figure 2h illustrates how the supply current (IS) drops and rises during PWM control, and when changing from one LED to another in the circuit of Figure 1, thereby causing unwanted transient signals that can affect the analogue-to-digital data processing.

It is an aim of the present invention to provide a light source array and a method of controlling the illumination of a light source array that do not suffer from the disadvantages mentioned above.

Summary of the invention

According to a first aspect of the invention, there is provided a light source array comprising: a first light source, the first light source having a first switch connected in series therewith for selectively illuminating the first light source; a second light source, the second light source having a second switch connected in series therewith for selectively illuminating the second light source, wherein the second light source and second switch are connected in parallel with the first light source and first switch; and a shunt path, the shunt path having a third switch connected in series therewith for selectively connecting the shunt path in parallel with the first light source and first switch and/or the second light source and second switch.

According to another aspect of the present invention, there is provided a method of controlling illumination of a first light source and a second light source, the first and second light sources having respective first and second switches connected in series therewith for selectively illuminating the first and second light sources, the method comprising the steps of selectively connecting a shunt path in parallel with the first light source and second light source prior to switching illumination between the first light source and second light source, and disconnecting the shunt path from being in parallel after said switching between said first light source and second light source.

Brief description of the drawings

For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the following drawings in which: Figure 1 shows a basic block diagram of a prior art system; Figures 2a-2h show the switch control signals and the current drawn in Figure 1 when switching between LEDs in both constant current and PWM modes; Figure 3 shows a basic block conceptual diagram of a first embodiment of a LED driver apparatus, Figure 4 shows the current drawn in the circuit of Figure 2 when switching between LEDs; Figure 5 shows a basic block conceptual diagram of the invention according to a first embodiment; Figure 6 shows a flow diagram relating to the switching sequence of switches S1-S4 of Figure 5; Figures 7a to 7f are signal diagrams illustrating the switching sequence of switches Si-S4 of Figure 5; Figure 8 shows a basic block conceptual diagram of another embodiment of a LED Driver; Figures 9a to 9f are signal diagrams illustrating the switching sequence of switches Si-S4 of Figure 8, when switching between LEDs in constant current mode; Figures lOa to lOi are signal diagrams illustrating the switching sequence of switches S1-S4 of Figure 8, when switching between LEDs in PWM mode; Figure 1 la provides a more detailed illustration of Figure 8, and in particular of the first current source lSl; Figure 11 b shows a further optional improvement to Figure 11 a; Figure 12(a) illustrates a simplified example of the current source lS2 used in Figure 8; Figure 12(b) illustrates an embodiment of an implementation of a switched maximum current (lmax) detection circuit; Figure 12(c) illustrates how the maximum current detection circuit of Figure 12(b) can be switched off; and, Figure 12(d) illustrates a more detailed example of the current source 1S2 described in Figures 8 and 12(a).

Description of the preferred embodiments

In the following description of the preferred embodiments an LED array is described as comprising three LEDs, i.e. Red, Green and Blue. However, it will be appreciated that the invention is equally applicable with an LED array comprising two or more LEDs. In a similar way, although the description of the preferred embodiments refers to the switching circuitry comprising three switching devices, one for each LED, the invention is equally applicable to an arrangement having two or more switching devices, one for each LED device Aspects of the invention are also applicable to systems with only a single LED, e g in PWM mode.

Furthermore, although the invention is described in relation to the switching circuitry driving LEDs, the invention is also applicable with other light sources, not only visible light but non-visible light such as Ultra Violet (UV) and Infra Red (IR). Therefore, references to an LED or LED array in the preferred embodiments are intended to cover a light source or light source array more generally.

Figure 3 illustrates a basic block conceptual diagram of an LED driver apparatus in its simplest form, as described in co-pending patent application GB2436404 An LED array comprises Red, Green and Blue LEDs Li, L2, L3. The invention claimed in co-pending patent application GB2436404 relates to placing the LED switching circuitry Si, S2, S3 on the same monolithic structure, i.e integrated circuit, as the analogue front end circuitry (AFE), i.e. the analogue processing circuitry that processes the image data received from a sensor device. To reduce the problems associated with LED switching transients interfering with the ADC process, a current source IS1 is provided in the current path, preferably between the switches Si, S2, S3 and ground The current source IS1 controls the flow of current through the LEDs Li, L2, or L3 according to the states of switches Si, S2, S3.

The provision of the current source ISi enables the current flow through an LED (LI-L3) to be controlled, rather than being merely switched on and off as found with the prior art The current through the LED is now defined by current source IS1, independently of the LED I-V characteristics or the supply voltage tolerance, so the LED current is as accurate as the accuracy of the current source. Adjustment of the current may be by direct adjustment of ISi or by PWM modulation of IS1 and the switch signals.

The introduction of current source 151 also enables the rate of change of current (dildt) through an LED to be controlled, for example by reducing the initial rate of change of current. Figure 4 shows the supply current IS drawn by the circuit during the operation of the embodiment of Figure 3, when IS1 is decreased in an S-shape fashion before each switch Si, S2, or S3 is turned off, and increased in an S-shape fashion shortly after the next switch is turned on. As can be seen the current waveform IS has smoother S-shaped transitions than the current waveform IS of Figure 2, thereby reducing unwanted transient signals. The ground return current waveform is similar.

Such S-shape waveforms may be generated by known techniques.

Thus, it can be seen that in the first embodiment the LED switches (S1-S3) may be integrated on the same IC as the AFE processing circuitry, with the current source IS1 being provided to reduce the generation of unwanted transient signals.

Figure 5 shows a basic block diagram of an embodiment of the present invention.

In a similar manner to Figure 3, an LED array comprises Red, Green and Blue LEDs Li, L2, L3. The LED switching circuitry 51, S2, S3 is placed on the same monolithic circuit as the analogue front end circuitry (AFE) that drives the switching circuitry. A current source ISi is provided in the current path between the switches Si, S2, S3 and ground, for controlling the flow of current through the LEDs Li, L2, L3.

According to this embodiment a shunt path 50 is provided. The shunt path 50 comprises a switching device S4. The shunt path 50 having the switching device S4 is provided in parallel with the LED array and switching circuitry. The problem relating to the LED switching transients interfering with the ADC is reduced because, as will be explained below, the shunt path 50 enables harmful transitions in the ground current flow to be reduced.

The following text describes the operation of the switching device S4 in the shunt path for reducing transient signals when switching from one LED to another.

The shunt path 50 is enabled when switching device S4 is switched on. S4 is switched on in sequence with the operation of the LED switches S1-S3 as will be described in the following.

Referring to the flow chart of Figure 6, assume Si is switched on (i.e. Si is closed), step 61, such that LED Li is passing a current Ii from the positive supply VDD to ground GND via current source IS1 During operation of a scanner, for example, once Li has achieved its task (e.g used to illuminate the object while the red component of one line of its image is generated), Li has to be switched off by switching off Si (i e. opening Si), and S2 has to be switched on (closed) so that L2 passes its current 12 (thus enabling L2 to illuminate the object while the green component of one line of its image is generated) According to this embodiment, prior to switching off Si, switch S4 is switched on, i.e. closed (step 63) such the Node A, on the high side of the current source IS1, is coupled to the supply voltage VDD Switching on S4 has the effect of applying zero bias, or at least a much reduced bias, to the LED Li. In other words, S4 has the effect of steering the current away from the Li/Si current path. The current 14 through S4 is limited by the current source ISi, so the total supply or ground current is still ISi.

Even though the LED Li is effectively turned off, its associated switch SI is still however closed, i.e. switched-on.

Si can now be opened in step 65, i e. switched-off, thereby removing the LED Li from the circuit. The total supply or ground current is still IS1.

Switch S2 is then closed, step 67, thereby connecting LED L2 to the circuit. Switch S4 remains closed during this switching between Li and L2.

Once switch S2 has been closed, S4 can then be switched-off in step 69, i.e. opened, thereby allowing LED L2 to become forward biased such that a current 12 passes from the positive supply VDD to ground GND via current source Si This sequence is performed in a similar manner when changing from LED L2 to another LED, for example L3, and so on.

It will therefore be realised that, rather than the power supply current IS having large switching current components being drawn in a disrupted, non-continuous manner from the power supply (i.e. corresponding to the currents Ii, $2 & 13 being drawn by the respective LEDs during operation), the power supply current IS remains constant instead.

The circuit arrangement of Figure 5 therefore performs differential current switching, such that current either flows through an LED (e.g Li/Si) and the current source IS1, or through the shunt path 50 and the current source IS1.

Thus, it will be appreciated that the circuit of Figure 5 enables a substantially constant current IS to be drawn from the supply, and the same substantially constant current to flow in the ground return path, which reduces or substantially eliminates the ADC interference problem associated with the switching transients, such that it is now possible that the ADC is capable of being integrated on the same IC as the LED switching array (S1-S3). Integrating the switches on the same IC as the processing circuitry has the effect of minimising the cost associated with such an application.

Although Figure 5 is described as having a shunt path 50 in an arrangement where the switching circuitry Si, S2, S3 is placed on the same monolithic circuit as the analogue front end, it is noted that the aspect of having a shunt path 50 is not limited to this arrangement, and may also be used in embodiments where the switching circuitry Si, S2, S3 and analogue front end are located on separate integrated circuits. In a similar manner, although Figure 5 shows the shunt path 50 being used in conjunction with a current source IS1, it is noted that the shunt path 50 may be used in embodiments whereby there is no current source IS1. According to yet a further embodiment, the shunt path may be used in an arrangement whereby there is no current source IS1, and whereby the switching circuitry Si, S2, S3 and the analogue front end are located on separate integrated circuits.

Figures 7a-7d provide a further illustration of the switching sequence of switches Si-S4 of Figure 5. Prior to time t1 the LED Li of Figure 5 is being illuminated. In other words, switch Si is turned-on (i e due to the corresponding switch control signal CSi being high), while switches S2, S3 and S4 are turned-off (I e due to switch control signals CS2, CS3 and CS4 being low). The following operation is then performed in order to illuminate LED L2 in place of LED Li. First, at time t1 the switch S4 is turned-on (i.e. by taking the switch control signal CS4 high). This causes the shunt path 50 of Figure 5 to become operational Next, at time t2 the LED Li is removed from the circuit by turning off switch Si (i.e. by taking the switch control signal CS1 low). It will be appreciated that the current IS drawn from the supply remains constant despite LED Li being turned off, due to the effect of the shunt path 50 and current source ISi. At time t3 switch S2 is turned-on (i.e. by taking switch control signal CS2 high) such that LED L2 is connected to the circuit Finally, at time t4 the shunt path is removed by turning off switch S4 (i.e. by taking the switch control signal CS4 low).

A similar procedure is performed when switching from LED L2 to LED L3, or from LED L3toLEDL1.

Figure 7e illustrates the current IS drawn from the power supply of Figure 5 when performing the switching operation described above. As can be seen, the current IS remains substantially constant.

In contrast, Figure 7f illustrates what power supply current IS would be drawn from a power supply (or the corresponding ground return current) when performing a switching operation in a prior art arrangement as shown in Figure 1, i e. if the shunt path 50 were absent Although not shown in Figures 7a to 7f, it will be appreciated that the arrangement of Figure 5 can also be used in a PWM mode of operation, whereby the respective switches are controlled by altering the duty-cycle and/or frequency of their control signals, for example toggling CS4 during a time when one of Si to S3 are on.

It should be noted that it is preferable to switch Node A in a controlled manner so that the rate of change of voltage (dvldt) at Node A is not excessive.

Figure 8 shows a basic diagram of another embodiment.

As with Figures 3 and 5, an LED array comprises Red. Green and Blue LEDs Li, L2, L3 The LED switching circuitry Si, S2, S3 may form part of the same monolithic circuit as the analogue front end circuitry (AFE) that processes the image data received from the photo sensors. To reduce the problem associated with LED switching transients interfering with the ADC process, a current source IS1 is provided in the current path between the switches Si S2, S3 and ground, for contro!ling the flow of current through the LEDs Li, L2, L3. A differential current path 50 (or shunt path) having a switching device S4 is provided in parallel with the array of LEDs and corresponding switches is S1-S3.

In addition, according to this embodiment, a second current source lS2 is provided in the shunt path 50. The second current source lS2 enables the switching of the shunt path 50 to be performed in a more controlled manner. As will be described in greater detail below in relation to Figures 12a to i2d, there will be capacitance Op associated with Node A, either parasitic capacitances or possibly an actual additional capacitor.

The second current source 1S2 is switched on by switching device S4 in sequence with the LED switches S1-S3 as was described above in connection with Figures 5, 6 and 7.

The current drawn by the second current source 1S2 may be configured to be a predetermined amount greater than the current IS drawn through the LED Li, for example 5% greater. For example, it may be configured so that it can be switched between say 105% of IS1 and 95% of lSi, for example by comprising a 95% current source and a 10% current source in parallel, separately switchable.

Figures 9a-9d illustrate the switching sequence of switches S1-S4 of Figure 8.

Referring to Figures 9a-d, just before switch Si is switched off at time t2, current source 1S2 is switched on via switch S4 at time t1 and draws a slightly larger current IS from the supply than the current IS previously drawn by LED Li from current source IS1.

The difference in current between lS2 and IS1 serves to charge up the capacitance Cp on node A, until node A has risen to the voltage compliance limit of current source 1S2 and the output current of 1S2 reduces to equal IS1. In other words, a slightly larger current IS equal to 1S2 is drawn for a short time after time t1, as shown in Figure 9e The modulation of the ground return current is substantially the same as that of the supply current IS. It is noted that the difference between 1S2 and IS1 flows as a displacement current though Op while node A is changing voltage When switching from using one LED, for example Li, to using another LED, for example L2, as before, Si can now be opened (switched off) at time t2 so as to isolate LED Li, and S2 can be closed at time t3 to connect LED L2. During this switching operation switch S4 remains closed.

Once switch S2 is closed, current source 1S2 is reduced, to be less than IS1, and node A will decrease in voltage, at a rate determined by Op and the difference between IS1 and lS2. Node A will decrease in voltage until LED L2 starts to take the difference current. Switch S4 can then be switched off at time t4, i.e opened, thereby stopping the current flow through lS2 and fully forward biasing LED L2 such that LED L2 becomes illuminated and draws current from the supply driven by current source lSi.

This sequence is repeated when switching from LED L2 to another LED.

Thus, it can be seen that, rather than the power supply having a large switching current IS being drawn from it as shown in Figure 9f (i.e. in a disrupted or non-continuous manner corresponding to the respective LED currents Ii, 12, 13), the power supply has a much smoother or continuous current IS drawn from it (as shown in Figure 9e). The ground current will be equal to the constant current source ISi plus any brief transient currents charging Cp, so in this case the ground current will be IS1 plus or minus 5%, for example The supply current modulation will be the same. In contrast, Figure 9f illustrates what current ISPRiOR ART would be drawn in a prior art arrangement as shown in Figure 1, i e. if lS2 and S4 were absent. As shown in Figure 9f, the current ISpRIOR ART drawn from the supply would switch between ISPRIOR ART and zero when switching from one LED to another.

The smaller switching current of the invention minimises the effect of switching transients such that the ADC is capable of being integrated on the same IC as the LED switching array and the IC can be placed on the scanner head Such an integrated scheme has the effect of minimising the cost associated with such an application According to a further embodiment, the switches in the embodiment of Figure 8 can be controlled using pulse width modulation (PWM) control signals This could be achieved by toggling CS1 etc, but to reduce supply and ground current ripple, CS4 would need to be toggled in anti-phase. However, it is preferable to apply PWM to the shunt path.

In other words, while switch S2 say is closed, switch S4 is controlled using a PWM control signal, thereby indirectly controlling the current 12 passing through LED L2 and therefore the average intensity of LED L2. Figures lOa to lOi show a PWM operation where Li is run at 100% duty cycle, L2 at a small duty cycle and L3 at an intermediate duty cycle.

According to a further embodiment, to allow variation of the LED currents without PWM switching, the current source IS1 (and lS2) can be varied in magnitude, by a common amount for all LEDs or differently for each LED. In other words, the current sources IS1 and lS2 can be fixed (i.e. set to operate in a predetermined mode of operation), or programmable, such that the operation of the current source is variable. Further discussion of this aspect will be provided after discussing the features of the current source IS1 and the current source lS2 in greater detail.

Figure ha illustrates a more detailed example of a current source IS1 that may be used in the embodiments of Figures 3, 5 and 8.

Referring to Figure ha, a Current Reference Generator (CRG) basically sets the reference current ref 1 for the whole circuit.

A reference voltage Vref supplied to an input of an amplifier in the CRG is preferably a bandgap reference voltage, thus being very accurate and stable.

In this particular example of the CRG, Vref is applied to the input of amplifier Al Feedback around amplifier Al and transistor MNO forces the voltage on node Pin to equal Vref, and thus sets the current through the resistor Rext. This current passes through MNO to give the output current Iref 1, equal to VreflRext.

"Pin" may represent an output pin on an IC. This allows a user to set the reference current Irefi to a desired value by altering the value of an external resistor, Rext The ability of a user to set Irefi is preferable, since it relates to the type of LEDs (L1-L3) that are used, with different LEDs having different characteristics Alternatively Rext may be integrated with Al, possibly trimmable or digitally programmable to allow adjustment.

Current Source IS1 comprises a series of controlled current sources MP2/MP3 that define the currents lref2 and lref3 that are mirrored versions of Iref 1.

Current source IS1 comprises a variable current source, for example, a Current Dig ital-to-Analogue Converter (CDAC), which is made up of a series of 21 NMOS transistor and switch arrangements: where N is an integer greater than 1. It should be noted that lref2 & Iref3 set up the current sinking capabilities of the CDAC as will be described below.

Within the CDAC, each individual switch is controlled so as to allow its associated NMOS transistor to connect to node A, the low-side of switches S1-S4. It should be noted that the CDAC NMOS trans istors MLSB MMSB have W/L ratios that are binary-weighted such that the each successive transistor, when switched on, is capable of sinking twice as much current as its predecessor. This is denoted by the labels 1, 2, 25. . .2 close to each transistor MLSB MMSB. Such an arrangement allows the current sunk by the CDAC to be accurately controlled over a wide range of current values.

As mentioned above, in operation the Red, Green and Blue LEDs Ll-L3 may require different current values to pass through them. This is in part due to the different characteristics of the LEDs, and also in part due to the required brightness of each LED during a scanning operation. It should be noted that the brighter the LED is made the less the sampling (i.e. integration), and hence scanning, time is required which means that the scanner can operate quicker. Therefore, it is desirable to operate the LEDS at or near their maximum current ratings without damaging the LEDs.

In the circuit of Figure ha, the current lref2 through MN1 is mirrored by MN2 and MLSB, . . . ,MMSB To maintain accuracy despite variation in the voltage of node A, amplifier A2 is introduced. The voltage on the inverting input of the A2 is that of node A and varies during operation. Negative feedback from the non-inverting input of A2 via the voltage inversion and gain introduced by MN1 causes the gate voltage of MN1 to settle out to that voltage necessary to sink the current lref2 output from MP2. MN2 and MP3 are not essential, but are introduced to maintain feedback in the case where all the CDAC NMOS transistors (MLSB-MMSB) are turned off (i.e. zero output current).

Modern electronic systems, and scanners in particular, now operate at low supply voltages to reduce power consumption, power dissipation, and active and passive component cost. For low voltage applications, such as where VDD=5v, the current source lSl is therefore selected and designed such that the maximum possible voltage drop exists across the LEDs L1-L3, while the minimum possible voltage drop exists across the current source IS1.

Assuming the CDAC comprises 8bits (N=8), there are then 256 discrete levels (since 28=256) from zero to lmax3 in 255 steps, so each step (lLsB) is lmax3/255, where lmax3 is the maximum output current of the CDAC Assume that the maximum desired current through any one of the LEDs is Imaxi (allowing for tolerances in the LEDs). Then, allowing some margin, Imax3 < Imaxi.

lS2, for correct operation, is configured to be capable of sourcing a current lmax2 that is slightly greater, for reasons which will be apparent from the following description, than lmax3, such that: lmax2>lmax3 It is preferable to set the W/L ratio of MN1 to be the same as that associated with the LSB NMOS transistor of the CDAC (as indicated by the number "1" just below the gate terminal). Therefore, MN1 sinks a current lref2 that equals lmax31255 which equals LSB It should be noted that lref2 can be scaled such that it is larger or smaller than Irefi, and this can be achieved by the sizing of the transistor W/L ratios of transistors MP2 relative to transistor MP1. Also lref2 can be scaled with respect to lmax3 by sizing MN1 relative to the CDAC NMOS transistors MLSB MMSB.

Transistor MN2 is illustrated as having a parasitic Gate-Drain capacitance CGD. Such a capacitance exists in all of the NMOS transistors of the CDAC although they are not illustrated: such a parasitic capacitance is referred to as a Miller capacitance It should be noted that it is the combined Gate-Drain capacitance CGDTOI of all these capacitances (for MN2 and those NMOS transistors switched on in the CDAC and possibly input transistors of A2) that provides one mechanism for exacerbating the supply and ground current transients referred to earlier, giving rise to the requirement to render small the slew rates of node A as mentioned above in relation to Figure 5 Referring to Figure 5, the effect CGDTOT has in the arrangement of Figure 5 is that as the shunt path is enabled, i.e. as S4 switches-on, and connects the supply voltage VDD to the high sides of MN2 and the enabled CDAC NMOS transistors, there is a large dv/dt on node A. This is a.c. coupled through CGDTOT onto the gates of these transistors causing a spike in their currents, and these currents manifest as transients on the supply rails which will have an effect, to a greater or lesser effect depending on the value of CGDTOT, on the ADC.

A second effect, for example when using a current source IS1 as shown in Figure 1 la, is that the transient kick on the gates of MN2 and the other parallel NMOS transistors MLSB,. .,MMSB disturbs the bias point set by amplifierA2. A2 will have only a finite bandwidth, so may take some time to settle out and re-establish the steady-state bias point. During this time the current output from the CDAC will deviate from the nominal.

Hence, there is the need to control the slew rate of the voltage at Node A. It should be noted that S4 illustrated in Figure 5 may be, in a very basic version of the invention, implemented as a variable resistor, resistive controlled switch etc., such that it is switched on in a controlled manner so as to avoid these high rates of change of voltage dv/dt on Node A. Similarly for 1S2 in the embodiment of Figure 8.

Due to the requirement of having the maximum possible voltage drop across the LEDs, and the minimum voltage drop across the current source IS1, the circuit of Figure 11 a is susceptible to damage due to the high voltage at Node A of Figure 5 This is because the high voltage of Node A causes the voltage on the gate of MN2 to rise due to Miller Capacitance effects, thus causing MN2 to turn on.

In view of this possibility, Figure 11 b shows a preferred improvement in which a cascade transistor is connected to the drain of MN2, thereby shielding MN2 from the voltage at Node A in Figure 5. The cascade transistor is biased by a reference voltage Vbias that may, for example, be supplied by a current source arrangement as shown.

The cascade transistor illustrated in Figure 1 lb and associated with MN2 is preferably used as the basis for the respective switches associated with each of the CDAC NMOS transistors (not illustrated), Each "cascade" switch in the CDAC is controlled independently by a control signal that biases its respective cascode switch. The advantage of utilising the cascode switches in the CDAC is that it helps to isolate the CDAC and the ground supply rail from transients.

As mentioned above, in low voltage applications, it is preferable to have the maximum possible voltage drop across each of the LEDs so as to maximise the current through the LEDs, which implies the minimum possible voltage drop across each of the switches S1-S3 and the current source IS1 It is noted that the on-resistance of the switches is substantially negligible hence the voltage drop is low in comparison to that associated with the current source lSl.

In order to minimise the voltage drop across current source IS1, there needs to be a low Drain-Source voltage drop across MN1 and as well as MN2 and the CDAC transistor and switch elements However, to keep MN2 in its saturation region, thereby providing a good current source, the VssatOf these transistors must be kept low.

The transconductance (gm) of an NMOS transistor is given approximately by: gm 2 IDSNDSsaI Therefore, gm is inversely proportional to VDSsat and is therefore high for a low VDSSaI.

Any mismatch in transistors MN1 & MN2 will result in an effective offset voltage at the gate terminal of MN2 Such an offset will, because of the high gain (gm) of MN2, result in errors. From the above formula, an effective gate voltage offset AV will give a fractional error Al in output current lref3 compared to lref2 where MuDS = gm.AV/IDS = 2.AV/ VDSS3t This is especially true when the transistors within the CDAC are switched in as they too have high transconductances like MN2 plus, they are binary-weighted and driven by the effective offset voltages of similar magnitude.

To achieve say 8-bit accuracy for say a lOOmV VDSsat of MN1 requires sub-millivolt offsets. The random manufacturing offset voltage of a MOS transistor may be reduced by increasing its gate area. But since the offset is only inversely proportional to the square root of its gate area: this leads to impractically large devices for MN1 and the CDAC devices. To overcome this, there may be provided a second, more accurate, current source and calibrating the output of the first current source against this second current source. In this embodiment, lS2 comprises this second current source. 1S2 has much more headroom, almost all of VDD, so can include devices with much greater VOSsat and hence much smaller area for the required accuracy.

To provide a more detailed explanation of the current source lS2, reference will now be made to Figures 12a to 12d in which: Figure 12a illustrates a simplified example of the current source lS2 used in Figure 8.

Figure 12b illustrates an embodiment of an implementation of a switched maximum current (Imax) detection circuit.

Figure 12c illustrates how the maximum current detection circuit can be disabled.

Figure 12d illustrates a more detailed example of the current source 1S2 described in Figures 8 and 12a.

Referring to Figure 12d: transistors MP5, MN4 and MN5 constitute the current source lS3 in Figure 12b; transistors MP4, MN3 and MN6 constitute the current source lS5 in Figure 12b; and transistors MP1O, MPh and MN7 constitute the current source 1S4 in Figure 12b.

Referring to Figure 12d, transistor MP4 is driven from a suitable voltage, for example Node X of Figure 1 la, to deliver a current lref4, another replica of Iref 1 This is mirrored by transistors MN3 and MN6 and then mirrored again by transistors MP9 and MP8.

Most of MP8's output current is then output via MP6 to provide an output current 14 to deliver the current lmax2 when the LEDs are shunted by current source lS2.

MP7 mirrors the current Imax 2 flowing through transistor MP6. It should be noted that the W/L ratio of MP7 may be, for example, 1/1 000 of that of MP6. This means that the maximum current detector circuit diverts only a small fraction of MP8's output current, and only consumes minimal power when performing its current detection function.

MP5 is driven with the same gate voltage as MP4 to give another replica current lref5, which is then mirrored via MN4 and MN5. MN5 is connected to MP7. the voltage at their common drain node will go high if MP7 carries more current than MN5 and low if MP7 carries less current than MN5. Since I(MP7) is a known fraction (say ill 000) of l(MP8), this flags whether l(MP8) is less than or greater than some predetermined threshold, this predetermined threshold being determined mainly by the transistor size ratios of mirrors MP6:MP7, MN5:MN4, and the ratio of MP4, MP5 to say MP1 of figure ha The comparator Ca compares the voltage at this common drain node of transistors MP7 and MN5 with a reference voltage Vref. Thus if the maximum current flowing through MP8 exceeds the predetermined threshold then the comparator output signal LEDmax is set so as to indicate this condition.

In operation, the output of MP6 is connected to the output of IS1 as shown and conducts the current 14 If IS1 is less than 14 (i e IMP6) then node A will rise, until the source voltage of MP6, i.e the drain voltage of MP8 has risen enough to take MP8 out of saturation into triode operation, i.e. past the output voltage compliance of MP8 regarded as a current source. MP7 will still output the same fraction of 14 (i.e IMP6), so the comparator flags whether l(lSl) is less than or greater than the predetermined threshold of 14 (IMP6).

If however IS1 is greater than 14 (IMP6) then node A will fall until node A reaches the voltage compliance of IS1 when delivering 14 defined by MP8. The current through MP7 will then be high, so the comparator C4 will flag this. This "flag" signal LEDmax can then be used to inhibit the turn-on of switches Si S3 to prevent the ISi current being steered to the LEDs, at least until the digital control to IS1 CDAC has been adjusted to decrease to a desired safe level, thereby protecting the LED.

In this implementation of lS2, its output current 14 is switched on and off by controlling the gate of MP8 using a switch S4*. (Note that S4* open corresponds to S4 being closed in previous diagrams, and vice versa.) As discussed above, it is desirable to limit the voltage slew rate on node A. This is implemented with the aid of capacitor C and controlled charging currents from MN6 and MP1 1. Referring to figure 1 2b, it should be noted that the current 11S4 sourced by current source lS4 (MP1 1) is twice that of the current 11S5 sourced by current source 1S5 (MN6) such that: when S4* is open, current source 1S5 is sinking a current which pulls the gates of transistors MP8 and MP9, as well as the low-side of capacitor C towards ground. Transistors MP8 and MP9 turn on, at a rate influenced by the capacitor C, and MP8 mirrors a magnified version of the current flowing through transistor MP9. When S4* is closed current source 1S4 effectively pulls the gates of transistors MP8 and MP9, as well as the low-side of capacitor C towards the supply VDD and transistors MP8 and MP9 turn off, at a rate influenced by the capacitor C, thereby gradually stopping the current (14) flowing to current source IS1.

The capacitor C, which is a relatively large capacitor, connected between the common gate terminals of transistors MP8 and MP9 acts to delay the rise in the gate voltages of transistors MP8 and MP9 such that rather than these two transistors turning hard on in a relatively short period, the turn-on time of these transistors is relatively slower. This has the effect of reducing the rate of change of voltage dv/dt at Node A. It will be appreciated that the sizes of transistors employed and the value of the capacitor, together with the LED current values can be altered so as to produce the desired effect, i.e. a reduced dv/dt at Node A, accordingly.

Referring to Fig 12(c), it is preferable to insert a switching mechanism, as illustrated by switches S5 and S6 into the maximum LED current circuitry (Imax Det.) By inserting these switches, the current that initially flows through the LED is indicative of the current flowing through the LED for the duration that it is conducting current such that the LED current monitoring can be disabled. S5 and S6 are driven by inverse signals such that when S5 is closed, S6 is open and vice-versa.

From the above it can be seen that the arrangement of the preferred current source shown in Figures 12b, 12c and 12d allows the current set for each of the LEDs to be measured: if it exceeds a maximum then the LED is not connected, so the LED is protected. This is active whenever the shunt current path is enabled, either when switching between LEDs or in the "off' time between pulses in PWM mode. This has the advantage of enabling the current to be monitored and controlled in the shunt path, rather than in the path actually containing an LED.

It should be noted that the W/L ratio of MP8 may be scaled if desired. For instance W/L for MP8 may be scaled to be 21.2 times (i.e. for an 8 bit = 256*1.2 times) that of MP9, to give a nominal lS2 scaled by 1. 2 over IS1. Similarly W/L of say MN5 may be scaled to adjust the limit threshold.

In a further embodiment, rather than MP8 being a fixed size, it can be broken into a number, say 256 segments, and controlled digitally to act as a current DAC. Since it has more available headroom, it can be physically small. With MP8 CDAC set to the desired current, IS1 can be iterated until it is within an LSB of I(MP8) (strictly 14 (i.e IMP6)). In this way the accuracy requirements and hence the physical size of the CDAC in IS1 can be kept within reasonable limits.

It will be appreciated that the embodiments described above offer the choice of PWM or absolute control of the LED current control. To control the brightness of illumination and so the imaging period, two techniques are therefore available, i.e. adjusting the absolute current or varying the on-time of a PWM control The current detect circuit for detecting a maximum LED current, enables scan time to be minimised, by maximising LED brightness. This is achieved by running the LED near it maximum current rating. To prevent damage to the LED while flowing in S3 the LED current is checked to be within the maximum current rating of the LED.

It is noted that, in the description of the above mentioned embodiments, it is assumed in Figure 9e, for example, that LED L2 and LED L3 draw the same current as LED1, i.e. 11=12=13. It will be appreciated however that, in practice, the optimum operational current of each LED might be different Also the operational currents may be required to be adjustable, perhaps to adjust the illumination of the object to match the sensitivity of a particular sensor or reflectance of the object.

It will also be appreciated that the current source IS1 in each of the embodiments can be configured to provide a predetermined current profile, and/or configured such that the current profile is variable (for example depending upon which of the LEDs L1-L3 is being switched). In other words, the current source IS1 can be fixed (i.e. set to operate in a predetermined mode of operation), or programmable, such that the operation of the current source is variable.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims or drawings.

The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single element or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims (9)

1. A light source array comprising: a first light source, the first light source having a first switch connected in series therewith for selectively illuminating the first light source; a second light source, the second light source having a second switch connected in series therewith for selectively illuminating the second light source, wherein the second light source and second switch are connected in parallel with the first light source and first switch; and a shunt path, the shunt path having a third switch connected in series therewith for selectively connecting the shunt path in parallel with the first light source and first switch and/or the second light source and second switch.

2. A light source array as claimed in claim 1, wherein the shunt path is controlled to be connected in parallel prior to switching from illuminating a first light source to illuminating a second light source.

3 A light source array as claimed in claim 2, wherein the shunt path is controlled to be disconnected from being in parallel after switching from illuminating a first light source to illuminating a second light source.

4. A light source array as claimed in any one of claims 1 to 3, further comprising a current source for controlling the flow of current through the first light source, second light source and/or shunt path.

5. A method of controlling illumination of a first light source and a second light source, the first and second light sources having respective first and second switches connected in series therewith for selectively illuminating the first and second light sources, the method comprising the steps of: selectively connecting a shunt path in parallel with the first light source and second light source prior to switching illumination between the first light source and second light source, and disconnecting the shunt path from being in parallel after said switching between said first light source and second light source.

6. A method as claimed in claim 5, further comprising the step of providing a current source for controlling the flow of current through the first light source, second light source and/or shunt path

7. An electronic device comprising a light source array as claimed in any one of claims 1 to 4.

8. An image reading device comprising a light source array as claimed in any one of claims 1 to 4.

9. A scanning device comprising a light source array as claimed in any one of cla,mslto4