GB2448753A

GB2448753A - Encoding of display scan direction by an optional additional clock pulse

Info

Publication number: GB2448753A
Application number: GB0708175A
Authority: GB
Inventors: Patrick Zebedee
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2007-04-27
Filing date: 2007-04-27
Publication date: 2008-10-29
Also published as: GB0708175D0; WO2008136237A1

Abstract

The number of connections to the substrate 72 of an active matrix display is reduced by encoding the scan direction for a bidirectional scan pulse register 76 with an additional initial clock pulse (DIR in figure 17) which is optionally transmitted when the start pulse SP is sent to the substrate from the display controller 62. The decoder 78 (figures 18-20) may produce either a left start pulse (SPL) or a right start pulse (SPR) in response to the detected logical level of the clock signal CK when the start pulse SP goes high. Alternatively, the decoder may provide a direction signal DIR to the scan pulse shift register (figure 24).

Description

Apparatus for Transmitting a Desired State to a System The present

invention relates to an apparatus for transmitting a desired slate to a system.

The present invention also relates to an apparatus for detecting a request ft)r a desired state of a system. The invention further relates to a system including such an apparatus and to combinations of the apparatuses and system. Such an arrangement may, for example, may be used to provide a clock scheme suitable for use with a clock generator for driving the rows and/or columns of an active matrix display or other active matrix device.

Figure 1 shows a typical active matrix display. Such a display is made up of a matrix 2 of picture elements (pixels), arranged in M rows and N columns. Each row and column is connected to an electrode, with the column electrodes being connected to the N outputs ola data driver 4 and the row electrodes being connected to the M outputs ola scan driver 6.

The pixels are addressed one row at a time. The scan driver includes an M-phase clock generator, which produces a series of clock pulses as shown in Figure 2. Each clock pulse OUTI controls the activation of row i.

All the pixels of one row may be addressed simultaneously, or they niay be addressed in B blocks ofb pixels, where bB = N. In the latter case, the data driver may also include a B-phase clock generator of the type described, such that each clock pulse OUTI activates block i.

Normal operation of the display is such that data is sampled onto the pixels from top to bottoni and from left to right, corresponding to the timing shown in Figure 2. However, ii is a common requirement for the direction of sampling to be switch-able, such that data is sampled onto the pixels from bottom to top and / or from right to left. In this way, it is possible to reflect or rotate the image displayed without re-ordering the input data. Such re-ordering requires considerable additional circuitry, such as additional memory sufficient to store the whole image.

In this case, the clock generators must in addition be able to operate bi-directionally, producing either clock pulses as in Figure 2, or clock pulses of the type shown in Figure 3. Each pulse OUTI in Figure 3 still activates row i. However pulse OUT occurs before pulse OVT1, whereas in Figure 2 pulse OUT occurred after pulse OUT1.

Clock generators of the type described may be formed directly on the display substrate, reducing the number of connections required to the display. This is advantageous, since it reduces the area occupied by the connector and leads to a display which is more mechanically robust.

Such a clock generator may be formed from a shift register. A shift register is a multi-stage circuit capable of sequentially shilling a sequence of data from stage to stage along its length in response to a clock signal. In general, a shill register may shift an arbitrary sequence of data. However, when a shill register is used as a clock generator in a scan or data driver, it is only required to shift a single high state along its length. Such a shift register is referred to as a walking one" shift register, and may or may not be capable of shilling an arbitrary sequence of data.

A known type of clock generator for use in such an application is a shift register comprised of a cascade of D-type flip-flops 12 controlled by a clock signal CK, as shown in Figure 4. On each rising edge of CK, the data at the Q output of DFF 12 is sampled onto the D input of DFF I2+, and is passed to its Q output. In this way, data can be passed along the register one stage at a time, If a single 1' is sampled onto the D input of the first DFF I2, the outputs of the register, Q, will be of the general form shown in Figure 2.

An example of such a clock generator is disclosed in US 5 282 234 and is shown in Figure 5. In this case, the shill register is composed of a series of flip-flops 14 and a set of switches 16 -22 to control the direction of propagation. The switches are controlled by an additional signal, CH (and its complement CHB). When the shill register is fhrnied on the substrate of the display, this additional signal requires at least one extra connection to the display substrate (sonic input circuits require both the signal and its complement, in which case two connections are required).

An alternative type of shill register is disclosed in US 200401506lAl and is shown in Figure 6. This type of register is composed of a cascade of RSFFs (reset-set flip-flops) and does not require switches to operate bi-directionally, being controlled by the order of its clocks. CKI is connected to stages numbered 3s+I, CK2 to stages numbered 3s+2, and CK3 to stages numbered 3s. A start pulse is applied to at least one end oithe register to begin scanning. Figure 7 and Figure 8 show the clocks CK1, CK2 and CK3 and the start pulse SP required in the forward and reverse directions respectively for a register with S = 3s+2 stages.

In the case where the register has a total nuniber of stages S!= 3s+I, the first and last stages will be connected to different clocks. For example, if there are S = 3s+2 stages, stage I will be connected to CKI, and stage S will be connected to CK2. The clocks will be of the form shown in Figures 7 and 8. In this case, the start pulse may be applied to both ends of the register. Since it will overlap with only one of the clocks, only one end stage will be set, and the order of the clocks will dictate the end at which scanning begins.

However, in the case where there are S = 3s+ I stages, both ends of the register will be connected to CK1 and if the start pulse is connected to both stage 1 and stage S, both stages will be set when ("K I rises. In this case, an additional signal is required: either a second start pulse, such that stage I and stage S are connected to separate start pulses, or a signal similar to CH which controls the connection of the start pulse.As before, either option niay require one or two additional connections, depending on theinput circuits.

The clocks for such a shift register niay be generated on the display substrate, in order to reduce the number of connections. A known circuit suitable for generating the clocks is shown in Figure 9. The circuit is composed of a series of RSFFs 24, controlled by a single clock and a start pulse. It generates three clock signals, which are connected to the output CKI-3 pins according to the state of the direction signal DIR (which is analogous to the signal CH in Figure 5). Depending on the state of DIR, the outputs of the clock generator may he of the forni shown in Figure 7 or in Figure 8.

Although this approach reduces the number of connections to the display substrate, the direction signal still requires one or two additional connections.

In all cases, it is usual for the clock or clocks to be enabled only during the scan of the shifl register, as shown in Figure 10. During the scan periods 26 the clock is enabled.

During non-scan or blanking periods 27 the clock is disabled. This reduces the power consumption of the system.

Figure 11 shows a simplified schematic of a typical display module. Such a module may comprise a Display Controller chip 42 and a Display Substrate 52, on which are formed a pixel matrix 54 and a hi-directional scan driver 56, as described previously. The display controller 42 produces data signals 44, which are connected to the pixel matrix, and clock signals (CK) 46, a start pulse (SP) 48 and direction signal (DIR) 50 which are connected to the scan driver.

The clock and start pulse signals are as previously described. The direction signal DIR corresponds to the signal CH in Figure 5. These signals are generated by the display controller.

Figure 12 shows some of the input signals to a typical display module. There is typically a clock, whose frequency corresponds to the input data rate, and one or more sync signals, whose timing corresponds to the start of the frame refresh and / or the start

S

of each row. There is typically a clock generator block inside the display controller which uses these signals to generate shift register clocks such as CK in Figure 10.

A disadvantage of the known arrangements is that an additional signal DIR is required for control of the direction of the shift register and, when the shill register is formed on the display substrate, that this signal requires an additional connection or connections to the display substrate.

A known method for reducing the number of connections between electronic components is to place signals in serial with other data. For example, a typical interface to an electronically erasable programmable read-only memory (EEPROM) is shown in Figure 13 and Figure 14 (from Asahi Kasci data sheet AK93C4SB / 55B / 65B / 75B -hRP://www.asahi-kaseLco.ip/akrn/ca/product/eeprom/danio4co2,pdf; 1 7Eh October 2006). in this case, the third and fourth states on the data input pin, Dl, are 01' if a write operation is requested (as in Figure 13), or 10' if a read operation is requested (as in Figure 14). The following data AS -AO represent the address to be written or read in the memory and, in the case where data is to be written, data D15 -DO follow AO, representing the data to be written to the respective address. The clock is the same in both cases.

Such an approach is not possible for a walking one shift register, since there are no data connections.

According to a first aspect of the invention, there is provided an apparatus as defined in the appended claim 1.

According to a second aspect of the invention, there is provided an apparatus as defined in the appended claim 19.

According to a third aspect of the invention, there is a provided a system as defined in the appended claim 25.

According to a fourth aspect of the invention, there is provided a combination as defined in the appended claim 30.

According to a fifth aspect of the invention, there is provided a combination as defined in the appended claim 3 1.

Embodiments of the invention are defined in the other appended claims.

It is thus possible to reduce the number of connections, such as conductors, between an apparatus for transmitting a desired system state and an apparatus or system for receiving and responding to the desired state. For example, in the case where a display controller transmits the desired state, such as the shilling direction of a bi-directional shift register, to a display module including such a shift register, it is possible to reduce the number of conductive interconnections. This reduces the cost of such an arrangement and improves the reliability and robustness of such an arrangement.

The invention will be fiirther described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagrani illustrating a known type of active matrix display; Figures 2 and 3 are waveform diagrams illustrating the operation of a scan driver of the display of Figure 1 in normal and reverse modes of operation, respectively; Figures 4 to 6 are block diagranis of known types of shift registers for use in a known scan driver of a display; Figures 7 and 8 are waveform diagrams illustrating waveforms for the shill register of Figure 6 for shifting in the forward and reverse directions, respectively; Figure 9 is a block circuit diagram of a known type of clock generator for providing the waveforms shown in Figures 7 and 8; Figure 10 is a timing diagram illustrating the timing of a known type of shill register clock; Figure II is a diagram illustrating interconnections in a known type of display module; Figure 12 is a waveform diagram illustrating typical input signals of a known type of display module; Figures 13 and 14 are timing diagrams illustrating the timing of a known type of EEPROM interface; Figure 15 is a diagram illustrating a display constituting an embodiment of the invention; Figure 16 is a circuit diagram of part of the display controller of Figure 15 for encoding additional data onto a clock; Figure 17 is a waveform diagram illustrating operation of the arrangement shown in Figure 16; Figure 18 is a circuit diagram of the decoder olFigure IS; Figures 19 and 20 are waveform diagranis illustrating the operation of the decoder of Figure 18 for forward and reverse scanning or shifting directions; Figure 21 is a block schematic diagram of a shift register of the scan driver of Figure 15; Figure 22 is a circuit diagram of one of the stages of the shift register of Figure 21; Figure 23 is a waveform diagram illustrating the operation of the shift register of Figure 22; Figure 24 is a block schematic diagram of' a display module constituting a second embodiment of the invention; and Figure 25 is a block scheniatic diagram of part of a scan driver of the module of Figure 24.

Figure 15 is a block diagram of a display module, constituting a first embodiment. The module contains a display controller 62 which is connected to a display substrate 72 by a data connection 64, a clock CK 66, and a start pulse SP 68. The controller 62 embodies an apparatus for transmitting a defined state of a system.

Formed on the display substrate 72 are a pixel niatrix 74, to which the data 64 is connected, a scan driver 76 and a decoder circuit 78. The decoder circuit 78 has inputs CK and SP which are connected to the clock signal 66 and the start pulse 68, respectively; the decoder has outputs SPL and SPR which are connected to the STARTL and STARTR inputs of the scan driver 76, respectively. The scan driver also has an input CK connected to the clock signal 66.

The display substrate 72 and the circuitry formed on it form a system which receives and decodes the encoded desired state which, in this application, is the direction of shifting of a shill register of the scan driver 76. The display controller 62 is f'ornied on a different substrate from the display substrate 72 and is connected to it by a plurality of conductors.

Within the display controller, there is a circuit to add an additional pulse to the shift register clock line when one direction of scan is required and to omit it for the other.

Figure 16 shows a circuit suitable for this function.

The circuit comprises a counter 90, RSFFs 92 and 94, an AND gate 96, an OR gate 98 and a clock generator 99. There are three inputs, CK.IN, SYNC and DIR. The counter and the "second flip-flop" 92 embody a state pulse generator.

The CKIN input embodies a "second input" and is connected to the clock input CK of' the counter 90 and the clock input CKIN of the clock generator 99; the SYNC input is connected to the reset input R of the counter 90 and to the SYNC input of' the clock generator 99; the outputs of the counter 90, Cl, C3, C5 and C15 are connected as follows: Cl is connected to the set input S of RSFF 94 (enibodying the "first flip-flop"), C3 is connected to the set input S of RSFF 92, C5 is connected the reset input R of RSFF 94, and C15 is connected to the reset input R of RSFF 92; the output Q of RSFF 92 forms the SP output of the circuit; the output Q of RSFF 94 is connected to the first input of AND gate 96, the second input of AND gate 96 is connected to the DIR input which embodies a "first input"; the output of AND gate 96 is connected to the first input olOR gate 98, the second input of OR gate 98 is connected to the CKOUT output of the clock generator 99; the output of OR gate 98 forms the CKOUT output or "output clock signal" of the circuit.

The counter 90 and the RSFF 94 together with the gate 96 constitute an encoder for forcing the output clock signal to a level, which is dependent on the value of the signal at the first input DIR, during each time slot defined by pulses at the input SYNC.

The inputs CKIN and SYNC are connected to signals such as CK and SYNC shown in Figure 12. The counter 90 outputs Cl-IS are high when the count value within the counter is equal to the corresponding value: that is, CX is high while the count value is X, but returns low when the value reaches (X+1). The clock generator 99 operates to generate a typical shift register clock, such as CK in Figure 10. In this embodiment, it is assumed that this will generate a clock which is low before the falling edge of SYNC and which generates the first rising edge on the clock 10 CKIN cycles after the falling edge of SYNC, as shown in Figure 17.

The circuit operation is illustrated in Figure 1 7. The signals Q94 and CKOUT99 refer to the Q output of RSFF 94 and the CKOUT output of clock generator 99, respectively.

The operation is as follows. While SYNC is high, the counter 90 is reset, that is, its count value returns to zero (and all the CX outputs are low). When SYNC falls, the counter 90 begins to count. When the count value reaches 1, C I goes high, setting RSFF 94 and causing its Q output to rise. This enables AND gate 96 to pass the value of DIR to the input of OR gate 98. Since the second input of OR gate 98 is held low, the value of DiR is therefbre passed to the CKOUT output. When the count reaches 3, the C3 output of the counter 90 rises, setting RSFF 92 and causing the SP output of the circuit to rise. When the count reaches 5, the C5 output of counter 90 rises, resetting RSFF 94 and causing its Q output to fall. This disables AND gate 96, forcing its output low, so that DIR is no longer passed and the circuit output CKOUT becomes equal to the CKOUT output of the clock generator 99. When the count reaches 1 5, Cl 5 rises, resetting RSFF 92 and forcing the SP output low.

The circuit therefore superimposes the state of DIR onto the low phase of the scan driver clock, such that the superimposed state is held for a period starting before the rising edge of SP and finishing atier the rising edge of SP. The input DIR receives two state logic level signals fbr determining the shifting direction of a shift register. These levels correspond to the high and low levels of the clock pulses produced by the clock generator 99 to give "first and second levels".

The time slots during which the encoder forces the clock signal to the level which is dependent on the value of the input signal may be periodic and have-a repetition rate which is less than that of the clock pulses. The input SYNC receives a synchronising signal which determines the timing of the time slots. The generator 99 is inhibited during the time slots and is arranged to generate the output clock signal from an input clock signal at the input CKIN. The input clock signals have a higher repetition rate than the output clock signals.

It will be obvious to one skilled in the art that the count values used for illustration may be altered arbitrarily, whilst still giving a set of outputs that are substantially similar to those described, and that there are many alternative circuit implementations capable of generating these outputs.

The composition of the decoder circuit 78 is shown in Figure 18. The circuit is comprised of a D-typc flip-flop (DFF) 137, a reset-set flip-flop 138, inverters 132, 135 and 136, and AND gates 128, 130 and 134. The CK input enibodies a "first input" and is connected to the input of inverter 136 and to the D input of DFF 137; the SP input embodies a "second input" and is connected to the input of inverter 135, to one input of AND gate 134 and to the CK input of DFF 137; the output of inverter 136 is connected to the second input of AND gate 134; the output of AND gate 134 is connected to the set input of RSFF 138; the output of inverter 135 is connected to the reset input of RSFF 138; the output oIDFF 137, DIR, is connected to the first input of AND gate 128 and the input of inverter 132; the output of inverter 132 is connected to the first input of AND gate 130; the output of RSFF 138, SP', is connected to the second input of the AND gates 128 and 130; the outputs of AND gates 128 and 130 lomi the outputs of the decoder circuit SPL and SPR, respectively.

The input CK receives a clock signal encoded in at least one time slot with a level representing a desired state. In this embodiment, first and second levels arc detected representing first and second desired states, respectively, in the form of forward and reverse shilling directions. The input SP receives the start pulses, which act as synchronising signals for determining the timing of each time slot. The flip-flop 1 37 acts as a memory circuit forming a decoder for detecting the level of the clock signal during each time slot.

Figure 19 shows the inputs and outputs of the circuit of Figure 18 in the top-to-bottom mode of operation. When the start pulse SP rises, it causes the DFF 137 to latch the high value of the clock CK. This value is passed to the Q output. DIR, and is held until the next rising edge on SP, at the start of the next scan. This value controls the direction of scan of the scan driver. While the clock is high, the output of inverter 136 is low, and hence the output of AND gate 134 is low. Thus the set input of RSFF 138 is held low, irrespective of the state of SP, and RSFF 138 cannot be set. When the clock CK falls, the output of inverter 136 rises and the output of AND gate 134 rises in response to the high state of SP. RSFF 138 is therefore set and its Q output rises. Since DIR is high, AND gate 128 is enabled and passes the high state of the Q output of RSFF 138 to SPL, while AND gate 130 is disabled, and SPR is held low. When SP falls, the output of inverter 135 rises, and RSFF 138 is reset. This causes SP' and SPL to fall, such that the falling edge of SPL is synchronous with the falling edge of SP.

The STARTL input to the scan driver therefore rises and scanning starts from the top of the register.

Figure 20 illustrates the operation of the circuits in bottom-to-top mode. In this case, when the start pulse SP rises, it causes the DFF 137 to latch the low value of the clock CK, and DIR is held low. This enables AND gate 130 and disables AND gate 128.

Since the clock is low, the rising edge of SP also sets RSFF 1 38, such that its Q output rises, and is passed to SPR. The STARTR input to the scan driver therefore rises, and scanning starts from the bottom of the register. When SP falls, the output of inverter 135 rises, and RSFF 138 is reset. This causes SP' and SPR to fall, such that the falling edge of SPR is synchronous with the falling edge of SP.

It can be seen that inverter 132 and AND gates 128 and 130 operate as a multiplexer, directing the Q output of RSFF 138 to either the SPL or SPR pin and holding the other pin low.

The scan driver is of the type described in British patent application no. 0701709.8 and shown in Figures 2 1 and 22 and embodies an arrangement responsive to the "decoder" 137 Lbr selling the desired state, in this embodiment the direction of line scanning.

Figure 2 1 shows the connections between neighbouring stages of the register 28 -32.

Each stage has two inputs, IN I and 1N2, a clock input CK, a reset input RST, a "lock" output LOCK, and a main output OUT. Referring to stage n, IN I and IN2 are connected to the lock outputs of the neighbouring stages LOCK1+1 and LOCK11; CK is connected to the register clock CK; RST is connected to a global reset signal RST; LOCK is connected to the inputs of both neighbouring stages lN11 and 1N211+1; and OUT is connected to the nth output of the register, OUT.

In the case of the leftmost and rightmost stages 28 and 32, one of the inputs is connected to a start pulse. IN I of stage 28 is connected to a left start pulse START,; 1N2 of stage 32 is connected to a right start pulse STARTR.

Figure 22 shows the components of one stage in Figure 21. The inputs IN 1 and 1N2 are connected to the inputs of an OR gate 38, the output of which is connected to the set input, S, of the reset-over-set flip-flop 34 (ROSFF -a RSFF where an active signal on the reset input overrides an active signal on the set input). The Q output of ROSFF 34 is connected to one input of an AND gate 40, the other input of which is connected to the clock input CK. The output of the AND gate 40 is connected to the output of the stage, OUT, and is also connected to the set input of RSFF 36 and to the input of an inverter 41. The Q output of RSFF 36 and the output of inverter 41 are connected to the inputs of an AND gate 43. The output of AND gate 43 fornis the lock output LOCK and is connected to the first input of OR gate 39. The reset input RST is connected to the reset input of RSFF 36 and to the second input of OR gate 39. The output of OR gate 39 is connected to the reset input, R, of ROSFF 34.

Figure 23 illustrates the operation of the decoder and scan driver in top-to-bottom mode.

The signals Q refer to the node Q in Figure 22. The subscripts on the Q and LOCK signals refer to the labels in Figure 21.

At the start of operation, all ROSFFs 34 and RSFFs 36 arc in their reset slate, that is, their Q outputs are low. This may be achieved by raising the reset input RST to a high slate, which causes the output of OR gate 39 to rise, and thus applies a high stale to the R inputs oIROSFF 34 and RSFF 36.

The operation of the scan driver will be described with reference to an nth intemediate stage such as 30 in Figure 21. When one of the inputs INI and 1N2 (connected to nodes LOCK1 and LOCK+I) goes high, the output of the OR gate 38 in the nih stage 30 goes high and the ROSFF 34 of the nth stage 30 is set. This activates the nth stage 30. When ROSFF 34 is set, its Q output is high and the output of the AND gate 40 is equal to the state of its other input, CK. When the clock CK rises, this is passed through the AND gate 40 to the output OUT, forming the output pulse OUTH. When OUT is high, this drives the output of the inverler 41 low, which in turn drives the output of AND gate 43 low, and hence LOCK remains low. In addition, when OUT goes high, RSFF 36 is set, and its Q output is high. When the clock CK falls, the output of AND gate 40 falls and OUT falls. The output of inverter 41 rises and the output of AND gate 43, LOCK, rises.

The high state on LOCK persists until RST rises. The high state on LOCK resets ROSFF 34 and prevents it from being set again when 1N2 goes high.

The mode of operation will be similar for all stages and in both left-to-right and right-to-left mode, except that in left-to-right mode, the leftmost stage 28 will be activated by STARTI, and in right-to-left mode, the rightmost stage 32 will be activated by STARTR, rather than by the LOCK output of an adjacent stage.

Figure 24 is a block diagram of a display module constituting a second embodiment.

The diagram is similar to the first embodiment, except that the SPL and SPR outputs of decoder 78 are replaced by DIR and SP' outputs, and the STARTL and STARTR inputs to the scan driver 76 are replaced by DIR and START inputs. The DIR and SP' outputs of the decoder 78 are connected to the DIR and START inputs of the scan driver 76, respectively.

The decoder 78 is similar to that shown in Figure 1 8, with the omission of inverter 132 and AND gates 128 and 130. The nodes DIR and SP' form the outputs of the block. The operation of the block is as previously described.

The scan driver is embodied as shown in Figure 25. The driver is composed of a clock generator 80 of the type shown in Figure 9 and a shift register 82 of the type shown in Figure 6. The CKI-3 outputs of the clock generator 80 are connected to the corresponding CKI-3 inputs of the shift register 82; the SP pins of the clock generator and the shift register 82 are connected together and to the START pin of the scan driver; the CK and DIR pins of the clock generator 80 are connected to the CK and DIR pins of the scan driver, respectively.

It will be obvious to one skilled in the art that there are many possible implementations of the decoder and shift register.

The clock niay be latched at any pre-de!ined time and not on the edge of the shift register start pulse. For example, the clock controlling the data driver clock generator in Figure I may be latched on one edge of the scan driver start pulse. It will be obvious to one skilled in the art that there arc many alternative such timings. The signal from which the direction state is latched may not be a

unique shift register clock. In implementations where the shift register requires two or more clocks and where these clocks are generated externally to the display substrate, the state may be latched froni any one of the clock signals, or a state may be latched from each clock, and the resultant states logically conibined to give the direction state for the shift register, in addition to other states.

The direction state may be latched from another timing signal. For example, if the display substrate has only one clock connection and where this clock is internally used to synthesize the shift register clock, the direction state may be superimposed on the single clock connection.

Claims

CLAIMS: I. An apparatus for transmitting a desired state of a system to

the system, comprising a lirst input for receiving an input signal representing the desired state, a clock generator for generating an output clock signal comprising a sequence of clock pulses, and an encoder for forcing the output clock signal to a level, which is dependent on a value oithe input signal, during at least one time slot.
2. An apparatus as claimed in claim I, in which the system is physically separate from the apparatus.
3. An apparatus as claimed in claim 2, in which the system and the apparatus are formed on separate substrates.
4. An apparatus is claimed in any one of the preceding claims, in which the system is connected to the apparatus by at least one conductor.
5. An apparatus as clainied in any one of the preceding claims, in which the encoder is arranged to force the output clock signal to first and second levels when the value of the input signal represents first and second desired states, respectively.
6. An apparatus as claimed in claim 5, in which the first and second levels compnse high and low levels, respectively, of the clock pulses.
7. An apparatus as claimed in any one of the preceding claims, in which the at least one time slot comprises periodic time slots.
8. An apparatus as claimed in claim 7, in which the repetition rate of the time slots is less than the repetition rate of the clock pulses.
9. An apparatus as claimed in any one of the preceding claims, comprising a second input for receiving a synchronising signal for determining the timing of the or each time slot.
10. An apparatus as claimed in any one of the preceding claims, in which the generator is arranged to be inhibited during the or each time slot.
I 1. An apparatus as claimed in any one of the preceding claims, in which the generator is arranged to generate the output clock signal from an input clock signal.
12. An apparatus as claimed in claim 11, in which the input clock signal has a higher repetition rate than the output clock signal.
13. An apparatus as claimed in claim 12, in which the encoder comprises a counter arranged to count clock pulses of the input clock signal and to control a first flip-flop.
14. An apparatus as claimed in claim 13, in which the first flip-flop is arranged to control a gate for the input signal.
15. An apparatus as claimed in any one of the preceding claims, in which the desired state is the shifting direction of a shift register of the system.
16. An apparatus as claimed in claim 1 5, comprising a start pulse generator for generating a start pulse for the shift register.
17. An apparatus as claimed in claim 16 when dependent on claim 13 or 14, in which the state pulse generator comprises a second flip-flop arranged to be controlled by the counter.
18. An apparatus as claimed in any one of the preceding claims, comprising a display controller and in which the system comprises a display.
19. An apparatus for detecting a request for a desired state of a system, comprising a first input for receiving a clock signal encoded in at least one time slot with a level representing the desired state, and a decoder for detecting the level of the clock signal during the or each time slot.
20. An apparatus as claimed in claim 19, in which the decoder is arranged to detect first and second levels of the clock signals, during the or each time slot, representing first and second desired states, respectively.
21. An apparatus as claimed in claim 20, in which the first and second levels comprise high and low levels, respectively, of clock pulses of the clock signal.
22. An apparatus as claimed in any one of claims 19 to 21, comprising a second input for receiving a synchronising signal for determining the timing of the or each time slot.
23. An apparatus as claimed in claim 22, in which the decoder comprises a memory circuit for storing the level of the clock signal in response to the synchronising signal.
24. An apparatus as claimed in claim 23, in which the memory circuit comprises a flip-flop.
25. A system comprising an apparatus as claimed in any one of claims 19 to 24 and an arrangement responsive to the decoder for setting the defined state.
26. A system as claimed in 25, in which the arrangement comprises a bidirectional shift register and the desired state is the shifting direction.
27. A system as claimed in 26, comprising at least one of a scan driver and a data driver including the shift register.
28. A system as claimed in claim 27, comprising a display including the at least one driver.
29. A system as claimed in any one of claims 25 to 28 formed on a single substrate.
30. A combination of an apparatus as claimed in any one of claims I to 18 and an system as claimed in any one of claims 19 to 24.
31. A combination of an apparatus as claimed in any one of claims I to 18 and a system as claimed in any one of claims 25 to 29.