GB2445502B - Buffer circuit having electrostatic discharge protection - Google Patents

Buffer circuit having electrostatic discharge protection

Info

Publication number
GB2445502B
GB2445502B GB0806764A GB0806764A GB2445502B GB 2445502 B GB2445502 B GB 2445502B GB 0806764 A GB0806764 A GB 0806764A GB 0806764 A GB0806764 A GB 0806764A GB 2445502 B GB2445502 B GB 2445502B
Authority
GB
United Kingdom
Prior art keywords
buffer circuit
electrostatic discharge
discharge protection
protection
electrostatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0806764A
Other versions
GB2445502A (en
GB0806764D0 (en
Inventor
Chan-Hee Jeon
Bong-Jae Kwon
Eun-Kyoung Kwon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040008147A external-priority patent/KR100781537B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to GB0806764A priority Critical patent/GB2445502B/en
Priority claimed from GB0617597A external-priority patent/GB2430821B/en
Publication of GB0806764D0 publication Critical patent/GB0806764D0/en
Publication of GB2445502A publication Critical patent/GB2445502A/en
Application granted granted Critical
Publication of GB2445502B publication Critical patent/GB2445502B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
GB0806764A 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection Active GB2445502B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0806764A GB2445502B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020040008147A KR100781537B1 (en) 2004-02-07 2004-02-07 Semiconductor device for protecting electrostatic discharge and semiconductor integrated circuit employing the same
US10/986,771 US7271629B2 (en) 2004-02-07 2004-11-15 Buffer circuit having electrostatic discharge protection
GB0617597A GB2430821B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection
GB0806764A GB2445502B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection

Publications (3)

Publication Number Publication Date
GB0806764D0 GB0806764D0 (en) 2008-05-14
GB2445502A GB2445502A (en) 2008-07-09
GB2445502B true GB2445502B (en) 2008-08-13

Family

ID=39523731

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0806764A Active GB2445502B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection
GB0806766A Active GB2445327B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0806766A Active GB2445327B (en) 2004-02-07 2004-12-30 Buffer circuit having electrostatic discharge protection

Country Status (1)

Country Link
GB (2) GB2445502B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855863A (en) * 1986-07-30 1989-08-08 Nec Corporation Integrated circuit having two circuit blocks therein independently energized through different power supply terminals
US4883978A (en) * 1987-03-23 1989-11-28 Kabushiki Kaisha Toshiba Semiconductor device having reduced potential fluctuations
US5646548A (en) * 1994-08-31 1997-07-08 Oki Semiconductor, Inc. Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages
US6075686A (en) * 1997-07-09 2000-06-13 Industrial Technology Research Institute ESD protection circuit for mixed mode integrated circuits with separated power pins
US6631061B2 (en) * 1999-12-24 2003-10-07 Seiko Epson Corporation Semiconductor integrated device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789917A (en) * 1987-08-31 1988-12-06 National Semiconductor Corp. MOS I/O protection using switched body circuit design
US5381059A (en) * 1993-12-30 1995-01-10 Intel Corporation CMOS tristateable buffer
US5892377A (en) * 1996-03-25 1999-04-06 Intel Corporation Method and apparatus for reducing leakage currents in an I/O buffer
US6327126B1 (en) * 2000-01-28 2001-12-04 Motorola, Inc. Electrostatic discharge circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855863A (en) * 1986-07-30 1989-08-08 Nec Corporation Integrated circuit having two circuit blocks therein independently energized through different power supply terminals
US4883978A (en) * 1987-03-23 1989-11-28 Kabushiki Kaisha Toshiba Semiconductor device having reduced potential fluctuations
US5646548A (en) * 1994-08-31 1997-07-08 Oki Semiconductor, Inc. Efficient method and resulting structure for integrated circuits with flexible I/O interface and power supply voltages
US6075686A (en) * 1997-07-09 2000-06-13 Industrial Technology Research Institute ESD protection circuit for mixed mode integrated circuits with separated power pins
US6631061B2 (en) * 1999-12-24 2003-10-07 Seiko Epson Corporation Semiconductor integrated device

Also Published As

Publication number Publication date
GB2445327B (en) 2008-08-13
GB2445502A (en) 2008-07-09
GB0806764D0 (en) 2008-05-14
GB0806766D0 (en) 2008-05-14
GB2445327A (en) 2008-07-02

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