GB2443003A - An adjustable linearized MOS differential transconductance amplifier - Google Patents
An adjustable linearized MOS differential transconductance amplifier Download PDFInfo
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- GB2443003A GB2443003A GB0620984A GB0620984A GB2443003A GB 2443003 A GB2443003 A GB 2443003A GB 0620984 A GB0620984 A GB 0620984A GB 0620984 A GB0620984 A GB 0620984A GB 2443003 A GB2443003 A GB 2443003A
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
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- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
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Abstract
A FET differential transconductance amplifier comprises a degeneration network comprising an impedance Zdeg and two FETs M7,M8 or M3,M4. The transconductance gm of the amplifier may be adjusted by altering Vbias to control the current source. The gates of the degenerating transistors may be driven alternatively by the drain nodes of the input transistors (figure 11) or the source nodes of the opposite input transistors (figure 16). The amplifiers may be used in LC-VCOs, mixers and filters in RF transceivers.
Description
1 2443003 Applications of Three Novel Differential Transconductors to
the Design of RF Transceivers' Building Blocks and Electronic Circuits
TECHNICAL FIELD
[001] This invention relates generally to all electronic circuits, specially to radio frequency (RF) transceivers' major building blocks, and more specifically to monolithic radio frequency (RF) IC's working at Giga Hertz range frequencies. It secures desirable features such as linearity, low power, low noise/phase noise, and wide tuning range for those circuits and ICs.
As well, it makes the design of analog building blocks of those IC's much easier, as its key elements (i.e. the differential transconductor topologies) are more control friendly compared to the conventional differential pair topology. While having a general application to the design of electronic circuits, the novel differential transconductor topologies used here, either in their original shapes or as negative resistors, are mainly used in analog circuits and filters.
BACKGROUND
[002] With the advent of sub-micron technologies, the demand for electronic circuits/systems in integrated form has generally increased. In wireless applications, due to the emerging needs for mobile communications such as GSM-900, GSM 1800 (DCS 1800), DECT cordless phones, PCS-1900, and the very fast evolving IEEE standardized Wi-Fi and Wi-MAX systems, the trend has moved towards cheap and dense high performance integrated RF transceivers capable of meeting the stringent requirements of GHz range frequencies, especially at ISM bands.
[003] Among all technologies, CMOS technology, due to its low cost and high density has become the most challenging technology for the realization of integrated monolithic circuits, especially RF transceivers' major building blocks.
[004] As it is clear in figuresla,b depicting typical generic wireless transceiver systems, the Phase-Lock-Loop (PLL) building block (drawn in figure2), as the frequency synthesizer to produce the local carrier needed for the mixing action for up/down conversion of the frequency, is the major building block. In addition to this, PLL has been used as the frequency synthesizer in analog circuits such as Q-enhanced active filters. In general, wherever in an electronic system a frequency synthesizer is needed, PLL may have an application. Hence, a significant challenge in realization of integrated CMOS based transceivers is the realization of PLL frequency synthesizer capable of meeting the design requirements.
[005] As it is observed in figure 2, VCO (Voltage Controlled Oscillator) as the local oscillator (LO) is the major building block of a PLL and hence a transceiver system. Generally, in Silicon based technologies, among all the building blocks of the transceiver systems working at high frequencies, VCO has received a significant attention. This is because, VCO is the oscillating block expected to provide the required as pure as possible sinusoidal waveform. It is well known that the purity of the PLL output signal and its tunability is primarily dictated by the VCO topology used in it. Hence, a widely tunable, low noise/phase noise, and low power monolithic VCO topology is a significant target.
[006] In recent years, in economically superior Silicon based technologies, considering the parasitics and technology limitations especially at high GHz range frequencies, LC-VCO architecture (figure 3) has proven to be capable of yielding high performance monolithic topologies (with and/or without Q-tuning capability). The major drawback however has been the technology limitations in securing high-Q reactive elements (especially spiral inductors).
As the LC tank in LC-VCO building block is passive and its storage elements (L and C) are lossy, usually active devices named transconductor are used in their negative resistor shape to compensate the losses and produce the positive feedbacklenergy required for the oscillation to start and be maintained. It is well known that LC-VCO's inherit most of their characteristics from the transconductor topologies used in their designs. As well, because of their inherent gain, ability to suppress 2' order Harmonic Distortion (HD2) and common mode noise, differential transconductor topologies are generally the desirable choice. Hence, noble control-friendly, widely tunable (Q and frequency), linear, low noise, and low power differential transconductor topologies can result in high performance monolithic LC-VCO's. Finally, if generally speaking, since differential transconductors are the fastest and most basic electronic elements after a single transistor, they play a fundamental role in electronic circuit designs, and hence they pass their advantages to every electronic circuit in which they are used.
This Invention [007] Figures 4a,b depict the P-type and N-type conventional differential pair transconductor topologies, here in this work called Diff as well. Figure 5 depicts the N-type Duff connected to act as negative resistor.
[008] Figures 6a,b depict the P-type and N-type of the first of the three novel differential transconductor topologies concerned in this invention named GGD (God Given Design).
Figure 7 depicts the N-type GOD transconductor topology connected to act as negative resistor.
[009] Hspice Simulation results in Figures 8, 9, and 10 depict respectively linearity, power, and noise performances of the conventional differential pair transconductor topology (Diff) compared to GOD transconductor topology.
[010] Figures 11 a,b depict the P-type and N-type of the second of the three novel differential transconductor topologies concerned in this invention named GGD2 (God Given Design 2).
Figure 12 depicts the N-type GGD2 transconductor topology connected to act as negative resistor.
[0111 Hspice Simulation results in Figures 13, 14, and 15 depict respectively linearity, power, and noise performances of the conventional differential pair transconductor topology (Diff) compared to GGD2 transconductor topology. Notice that, despite what is indicated in figure 15, in reality and based on literature, GGD2 appears less noisy than the conventional differential pair, if the noise is measured at the right place. This fact is elaborated in [014].
[012] Figures l6a,b depict the P-type and N-type of the third of the three novel differential transconductor topologies concerned in this invention named GGD3 (God Given Design 3).
Figure 17 depicts the N-type GGD3 transconductor topology connected to act as negative resistor.
[013] Hspice Simulation results in Figures 18, 19, and 20 depict respectively linearity, power, and noise performances of the conventional differential pair transconductor topology (Diff) compared to GGD3 transconductor topology.
[014] Based on the literature and simulations, compared to the conventional differential pair, all the three novel transconductor topologies (i.e. GGD, GGD2, and GGD3) are less noisy, less power consuming, more control and design friendly, and their tuning range is wider. GGD2 and GGD3 are always more linearized, and GGD can be more linearized under the same power consumption.
In relation to GGD2's noise performance depicted in figure 15 in which GGD2 appears noisier than the conventional differential pair, it is to be said that, despite this figure, GGD2 is less noisy. The reason as has been explained in a paper published at PATMOS2005 under the name of the inventor of this work is that, in this figure the measurement has been made around the degeneration resistor (Rdeg). Because of the added value that GGD2 provides for the source degeneration means, the noise measured around Rdeg appears more than its real value at the output current. If noise is measured at the output, GGD2 appears less noisy than the conventional differential pair. Figure 15 has been taken directly from the papers published at ICECS2003 and ISCAS2004 under the name of the inventor of this work. This part of those papers has been modified in the above mentioned paper published at PATMOS2005.
[015] Figures 21-a to 21-c depict some of the possible LC-VCO topologies using the conventional differential pair transconductor (Diff).
[016] Figures 22-a to 22-g depict some of the possible LC-VCO topologies using the GGD differential transconductor.
[017] Figures 23-a to 23-g depict some of the possible LC-VCO topologies using the GGD2 differential transconductor.
[018] Figures 24-a to 24-g depict some of the possible LC-VCO topologies using the GGD3 differential transconductor.
[019] Clearly, based on the foregoing discussions especially in [0061, and based on the literature as well, compared to the LC-VCO topologies in [015] using conventional differential pair transcoriductor (Diff), LC-VCO topologies in [016], [017], and [018] using GOD, GGD2, and GGD3 transconductors are all less noisy and power consuming, more control and design friendly, and their tuning range is wider.
[020] Also, it can be proven that, compared to the LC-VCO topologies using conventional differential pair, the LC-VCO topologies using GOD, GGD2, and GGD3 transconductors can yield less phase noise, if the design is made properly.
[021] As per the discussions made in [006] and [019] on the dependence of the characteristics of LC-VCO on the transconductor topology used in its design, any other possible LC-VCO topologies using either of GGD, GGD2, or GGD3 transconductors inherit their advantages.
[022] All the advantages of GOD, GGD2, and GGD3 remain the same, wherever in electronic circuit designs they are used as a Gm cell andlor an amplifier.
[0231 Two other important building blocks in a transceiver (figures la,b) and PLL (figure 2) are Mixer and Filter.
[024] Mixers are used for up/down conversion of the frequency to be processed. In modem transceivers, Mixers must have large dynamic range. Dynamic range is determined by two extremes. The lower extreme is the noise floor determining the minimum level of the signal to be processed. The upper extreme is the system's tolerable nonlinearity which limits the maximum signal level allowed to the input of the Mixer. From the two above extremes, linearity is much more effective in Mixer's performance as it is a major limiting factor to the linearity of transceiver. As such, the linearization of Mixers has been a design challenge since 1960s.
[025] In figure 25 the standard form of Gilbert Mixer using MOS transistors is depicted.
Gilbert Mixer is still the backbone of most of the recent Mixers. Clearly, the lower and upper parts of this figure as VRF (Radio frequency) and VLO (Local Oscillator) stages are using the conventional differential pair transconductor (Diff).
[026] For Gilbert Mixers used nowadays, VLO signal is common to be large enough to switch the tail current from one side of the RF stage to the other at LO frequency. It is proven that the linearity of the Mixer depends mainly on the input range of VRF. Therefore, if the RF stage is linearized properly, the Gilbert Mixer is linearized.
[027] Figure 26 is the Gilbert Mixer with its differential RF stage linearized (source degenerated). As the RF stage in this figure is the copy of the conventional differential pair (Diff) discussed earlier, if it is replaced with high performance linearized differential transconductor topologies such as GOD, GGD2, or GGD3, the resulted Mixers will inherit their features. Hence, high performance linear Mixers can be obtained in this way.
[028] Figure 27 depicts Gilbert Mixer using N-type GGD transconductor topology as its linearized RF stage.
[029] Figure 28 depicts Gilbert Mixer using N-type GGD2 transconductor topology as its linearized RF stage.
[030] Figure 29 depicts Gilbert Mixer using N-type GGD3 transconductor topology as its linearized RF stage.
[031] Clearly, figures 27, 28, and 29 in this invention are the new Gilbert Mixer topologies with the advantages obtained from using GGD, GGD2, and GGD3 differential transconductors as the RF stage. Based on the added value that GGD2 and GGD3 produce for the source degenerating means (Zdeg) used for linearization, more linearization than normal can be obtained for the Mixers using them as the RF stage. Also, since GOD can be made more linear than the conventional differential pair (Diff) under the same power consumption, the Mixer using it as the RF stage (as in figure 27) can be made more linear than figure 26 in which the linearized conventional differential pair (Diff) is used.
[032) Filters are to select the frequency band at which the transceiver works. As per recent literature, when in VCO indirect tuning the Filter is to be tuned, LC-VCO topologies proposed in this invention using GGD, GGD2, and GGD3 differential transconductors will show their discussed advantages (e.g. easier design and tunability). The same is true for Gm-C Filters and their derivatives.
Claims (1)
- Claims [033] As the most basic electronic elements in electroniccircuits after a single transistor, either of the three GOD, GGD2, or GGD3 named differential transconductor topologies used in this invention has a general application to the design of high performance electronic circuits.Based on the literature and due to the simple topology, GGD, GGD2, and GGD3 are among the very few high performance transconductor topologies capable of meeting the stringent circuit design requirements at 0Hz range frequencies. Using GGD, GGD2, and GGD3 transconductor topologies, high performance tunable, Low power, low noise/phase noise LC-VCO's are achievable. Using GGD, GGD2, and GGD3 transconductor topologies high performance linearized Mixers are achievable. Using GGD, GGD2, and GGD3 transconductor topologies high performance tunable analog filters are achievable. Applications of GGD, GGD2, and GGD3 transconductor topologies to the design of LC-VCO's, Mixers, and Filters open a promising road towards high performance GHz range integrated RF transceivers.
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GB0620984A GB2443003A (en) | 2006-10-21 | 2006-10-21 | An adjustable linearized MOS differential transconductance amplifier |
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GB0620984A GB2443003A (en) | 2006-10-21 | 2006-10-21 | An adjustable linearized MOS differential transconductance amplifier |
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GB2443003A true GB2443003A (en) | 2008-04-23 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633447B2 (en) * | 2001-05-25 | 2003-10-14 | Infineon Technologies Ag | Method and apparatus for compensation of second order distortion |
US6967538B2 (en) * | 2002-11-28 | 2005-11-22 | Hynix Semiconductor Inc. | PLL having VCO for dividing frequency |
EP1681764A2 (en) * | 2000-02-15 | 2006-07-19 | Broadcom Corporation | Variable transconductance variable gain amplifier utilizing a degenerated differential pair |
-
2006
- 2006-10-21 GB GB0620984A patent/GB2443003A/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1681764A2 (en) * | 2000-02-15 | 2006-07-19 | Broadcom Corporation | Variable transconductance variable gain amplifier utilizing a degenerated differential pair |
US6633447B2 (en) * | 2001-05-25 | 2003-10-14 | Infineon Technologies Ag | Method and apparatus for compensation of second order distortion |
US6967538B2 (en) * | 2002-11-28 | 2005-11-22 | Hynix Semiconductor Inc. | PLL having VCO for dividing frequency |
Non-Patent Citations (3)
Title |
---|
ICECS 2003 pp 412-415. * |
ISCAS 2004 pp I-1020 to I-1023. * |
PATMOS 2005 pp 714-723 * |
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GB0620984D0 (en) | 2006-11-29 |
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