GB2442071A

GB2442071A - Calibration of interleaved ADCs without interruption

Info

Publication number: GB2442071A
Application number: GB0621190A
Authority: GB
Inventors: Peter Richard Cronshaw; David Paul Thompson; Stuart Pooley
Original assignee: DREAMPACT Ltd
Current assignee: DREAMPACT Ltd
Priority date: 2006-08-08
Filing date: 2006-10-25
Publication date: 2008-03-26
Also published as: GB0621190D0; GB0615674D0

Abstract

A method for continuous calibration of a plurality of interleaved ADC's comprises adding a calibration signal to a measurement signal, wherein the calibration signal is in a frequency band other than the frequency band occupied by the measurement signal. After conversion of the combined signal, by each of the ADC's, the calibration signal and measurement parts of the signal being processed separately 28,32 with the processed calibration signal providing information to enable an error(s) to be corrected. The calibration method equalizes the relative path gains up to and including the input of each ADC, minimizes the voltage offset of each ADC and optimizes the sample instant timing of each ADC for time interleaved operation.

Description

)escription

Background of the Invention

There is a requirement for ever faster data acquisition circuits.

By temporally combining the outputs of multiple ADCs that are each converting a version of the same input signal and where each is sampling at a different sample instant from the others, but at the same sample rate, the combined output has a higher resultant sample rate.

As ADC devices sample at ever higher rates, it becomes more difficult to control the sample instant timing between multiple such ADCs, so that when their outputs are combined temporally together, a performance degradation may result if there is no correction to each ADCs sample instant timing in order to equalise the time periods between the combined output sample instances.

Also with muliple channels (Figure 10) in a system, the difficulty arises that the gain may differ between channels (Figure 10) so that a performance degradation may result if channel outputs were to be combined without any correction being applied to equalise the individual gain of the channels (Figure 10).

Components in a channel (Figure 10), such as ADCs or amplifiers, may have a finite voltage offset. If this offset is different between channels (Figure 10) whose outputs are to be combined, then a performance degradation may result if no compensation were to be applied to minimise the effect of voltage offset.

Calibration methods and means that minimise sample instant timing errors, gain errors, and voltage offset errors of time interleaved data acquisition circuits that result from, for example, temperature effects, device performance variations and aging effects on components are a major contributor to the resultant performance of such circuits.

Prior art

Some time interleaved data acquisition systems employ a factory calibration or a scheduled calibration period whereby an external signal, or one generated locally to the data acquisition system, is used to characterise the relative positions of the sample instant timing of time interleaved ADCs and to characterise the relative channel gain differences and to characterise the relative channel voltage offsets. The results of such characterisations are used to set time delay elements to position sample instant timing, to set analogue attenuators or digital multipliers to adjust channel path gains and to add analogue offsets to the ADC inputs or add a digital value to ADC outputs to adjust channel voltage offset.

Patent number US5294926 describes methods to calibrate multiple time interleaved ADCs where the output of the ADCs are monitored individually prior to being combined and where a calibration sine wave is applied to the input of each ADC. The frequency of the calibration sine wave is slightly offset from an integer multiple of the ADC sampling frequency. By observing the zero crossings of the calibration sine wave in the time domain after it has been converted by each ADC, a calibration routine alters one or more ADC sample clock delay elements to position the sample instances of each ADC such that they are properly staggered for combining into a time interleaved output. Similarity amplitude differences between the ADC outputs of the converted calibration sine wave can be corrected by a calibration routine that adjusts the full scale range available to the ADCs, for example, by modifying the digital output.

Such an approach requires a calibration period during which, the multiple time interleaved ADCs are not available for normal data acquisition operation. Also, such an approach requires the generation of a calibrating sine wave whose frequency has the limitation imposed on it that it be a slight offset from an integer of the ADC sample clock which complicates its generation.

Patent number US6556156 describes a method to calibrate the sample instant timing of multiple ADCs whose outputs are time interleaved by measuring a calibration signal with pairs of ADCs. Interpolation calculations are performed on the output of one ADC at the sample instant times of the other ADC. These interpolated values of the one ADC are compared to the actual outputs of the other ADC, and since they both relate to the same sample instants (one by calculation and the other by consequence) their difference is a measure of the difference in the correct sample instant timing between them and can be used to modify sample clock delay elements to minimise the timing error between them. For a system of more than two ADCs, one ADC can act as a reference and all of the other ADCs, in turn, can be calibrated against it using this method.

Such an approach requires a scheduled calibration period during which, the multiple time interleaved ADCs are not available for normal data acquisition operation.

Patent number W02006/0344 15 describes methods to calibrate the sample instant timing and the path gains of multiple time interleaved ADCs whereby a calibration sine wave of specific frequency is added to the signal of interest and this combined signal is supplied to all of the ADCs. Each of the ADC outputs is transformed to the frequency domain by an fast fourier transform (FFT) circuit and the calibration sine wave amplitude and phase is measured by each of these FFTs. A calibration routine measures compares the calibration sine wave amplitudes between the ADC channels and suitably adjusts ADC gains to minimise differences. Similarily, a calibration routine adjusts time delay elements in the sample clock timing of each of the ADCs to optimally position the sample instants.

Such an approach either requires a scheduled calibration period during which, the multiple time interleaved ADCs are not available for normal data acquisition operation or the calibration signal is left on during normal data acquisition and the calibration sine wave is left combined with the signal of interest, which limits the number of applications for which it can be used.

What is required is a calibration method which can continuously monitor and compensate for changes to the relative temporal positions of the sample instant timing of multiple time interleaved ADCs, changes to the voltage offsets of mutliple channels (Figure 10) and changes to the gain of such channels (Figure 10).

A key performance driver to the operation of such a calibration method is the accuracy to which the relative sample instant timing can be measured and corrected for.

The method and means of this invention addresses these requirements.

Introduction to the Drawings

Figure 1.1, Figure 1.2 and Figure 1.3a represent a non-exclusive implementation of the invention where four channels are shown for the purposes of illustration. "A" to "I" represent the interconnections between these Figures, where "A" on Figure 1.1 connects to "A" on Figure 1.2, "B" on Figure 1.1 connects to "B" on Figure 1.2, and so on. Similarly "ZI" on Figure 1.1 connects to "ZI" on Figure 1.3a and so on.

A desired signal (1) is combined with a calibration signal (26) in a combining circuit (2).

Optionally, both the desired signal (1) and the calibration signal (26) may be conditioned by passing each through respective filter circuits (3 and 4).

The calibration signal is generated by a calibration signal generator (5).

The combined signal (52) is split by a circuit (6) into "n" multiple outputs, where "n" is an integer greater than or equal to two.

These "n" outputs of the splitter (6) then feed the "n" channels.

The realisation of the circuitry may be actual hardware, in terms of an integrated circuit device or devices, or, additionally, may be implemented using software running on a processing means, such as a digital signal processor (DSP) or, additionally, may be in the form of a hardware description language to be implemented in a field programmable gate array (FPGA) device or other compatible device or a combination of the above methods.

The ADCs (7.. 10) are clocked with sample clocks from a sample clock generation circuit (11) that are all derived from a single frequency reference oscillator (12), but whose relative delay with respect to each other can be adjusted by a bank of "n" variable delay elements (13) in a manner determined by the calibration data processor (37).

Optionally there may be amplifiers (14.. 17) and/or filters (18..21) in the signal path before each ADC (7.. 10).

The digital outputs of the ADCs (7.. 10) can be modified by digital gain and offset adjust elements (22. .25) to adjust the gain of each of the channels and to adjust the ADC offset voltage of each of the channels.

The outputs of the digital gain and offset adjust elements (22. .25) send data to the desired signal filters (28. .31) which extract the desired signal (1) from the combined signal incident to theADC (7..10) input.

The outputs of the digital gain and offset adjust elements (22. .25) also send data to the calibration digital downconverters (32. .35) which convert the real data to complex data at 0 Hertz and which perform digital filtering to extract the calibration signal (26) from the combined signal incident to theADC (7..10) input.

The outputs of the desired signal filter (28..31) are passed to the desired signal data processor (36) to produce the desired signal output with an elevated sample rate (55) and those of the calibration digital downconverters (32. .35) are passed to the calibration data processor (37).

The clock used by the desired signal data processor (36) and by the calibration data processor (37) is generated by the signal and calibration processor clock generator (38) and it is derived from the single frequency reference oscillator (12).

Figure 1.1, Figure 1.2 and Figure 1.3b represent another embodiment of the invention where four channels are shown for the purposes of illustration. "A" to "I" represent the interconnections between these Figures, where "A" on Figure 1.1 connects to "A" on Figure 1.2, "B" on Figure 1.1 connects to "B" on Figure 1.2, and so on. Similarly "ZI" on Figure 1.1 connects to "ZI" on Figure 1.3b and so on. In this embodiment an extra sample an hold circuit or device, or similar circuit or device (65), is included between the combiner and splitter. The downstream circuitry of this embodiment, namely the splitter (6), the amplifiers (14.. 17) and filters (18..21) may not have the same performance characteristics as the previously described embodiment, and the amplifiers (14..17) and filters (18..21) may be optionally included in the circuit. The sample and hold circuit or device, or similar circuit or device (65) is clocked by the sample clock generation circuit (11) with a clock that is phase locked to the reference oscillator (12). In the embodiment of Figures 1.1, 1.2 and I.3a, this clock is not used.

Figure 2 illustrates a non-exclusive example of the relative positions in frequency of the desired signal (1) and the calibration signal added to the desired signal at the combiner (2). In this example, the desired signal band (48), occupied by the desired signal (1) lies below the calibration band (49) in frequency.

The frequency fi in Figure 2 may or may not be zero Hz. The frequency f2 in Figure 2 lies within the analogue frequency response of the signal path up to and including the input of each ADC (7.. 10), namely the combination of the combiner (2), each arm of the splitter (6) the optional amplifiers (14.17), the optional path filters (18..21) and the ADCs (7..10).

Figure 3 shows a non-exclusive example of a constellation diagram of calibration data from the output of one of the channels (Figure 10). For the purposes of illustration, the arrow (54) from the origin to the sample represents a phasor of that sample that can be expressed in polar co-ordinates (r, ). The value of ra represents the magnitude of the vector (54) and the value of 6a represents the phase of the vector (54).

The orientation of the sample (50) with respect to the I and Q axis has been chosen arbitrarily in this example for the purposes of illustration.

Similarily Figures 4. .6 represent illustrations of the same type as Figure 3, except that, for the purposes of illustration, different orientations of samples have been shown and different effects on these samples of circuit imperfections have been shown.

Figure 7 shows a superposition of Figures 4. .6 without any calibration applied.

Figure 8 shows a superposition of Figures 4. .6 with calibration applied.

Figure 9 is an example of an implementation of the calibration digital downconverter (32. .35). It provides two paths for the calibration data.

One path extracts the calibration signal (26) from the combined signal incident to the ADC (7.. 10) input by using a filter (27). The output of this path is the filtered calibration signal (40).

The other path extracts the calibration signal (26) from the combined signal incident to the ADC (7.10) input by using real data to complex data circuitry (57), for example implemented by a Hubert transform, downconverting to 0 Hertz using a mixer (58) and numerically controlled oscillator (59) and using a filter (60) to extract the calibration signal (26). The output of this path is the downconverted calibration signal (39).

Figure 10 is a non-exclusive example of a single channel.

In the context of this document and for the convenience of the descriptions of this invention, but not to limit the applicability of the invention, a channel shall comprise of a single arm of the splitter (41), an optional amplifier (42), an optional filter (43), an ADC (44), the digital gain and offset adjust circuitry (45) for that channel and the connections between these components. Where an optional component is not present, a connection shall exist in its place.

A channel shall also include the desired signal filter (47) that takes the output of the digital gain and offset adjust circuitry (45) to provide a desired signal (51) output from the channel.

Additionally a channel shall include a calibration digital downconverter (46) that takes the output of the digital gain and offset adjust circuitry (45) to provide two calibration data outputs (39 and 40) from the channel as described in Figure 9.

Figure 11 is an illustration of the complex output amplitude of one of the calibration digital downconverters (32. .35).

Figure 12 is an illustration of the output amplitude of one of the desired signal filters (28..31).

Detailed Description of the Invention

To effect the continuous calibration of multiple channels (Figure 10) whose outputs are temporally combined to produce a single higher rate output (55), this invention describes methods and means whereby a calibration signal (26) is added to the desired signal (I) by a signal combiner (2), where this calibration signal (26) is located in a frequency band that is outwith the frequency band occupied by the desired signal (1).

In the non-exclusive example of Figure 2 the calibration signal (26) occupies a bandwidth (49) which is shown to be positioned above the desired signal (1) which is shown to be occupying the lower bandwidth (48).

By sampling the combined signal (52) and then separating the calibration signal from the desired signal (1) in each of the channels (Figure 10) by means of digital signal processing, it is possible to calculate the amplitude and phase of data samples of the calibration signal (26) for the outputs of each of the channels (Figure 10).

In the non-exclusive example of Figure 1.1, Figure 1.2 and Figure 1.3a, an aspect of the signal processing is shown to be complex digital downconversion implemented in the calibration digital downconverters (32..35) of each channel (Figure 10).

Each channel (Figure 10) calibration signal is converted to zero Hz and filtered, such that the calibration data band (61) is centred on zero Hz and where the desired signal bandwidth (62) has been effectively removed, as shown in Figure 11.

The resultant output signal from the calibration digital downconverters (32. .35) is comprised to a greater extent of calibration data (61) whose amplitude and phase may then be calculated.

An example of a calibration digital downconverter (32. .35)is illustrated in Figure 9, where it is shown that the real desired signal (56) to the digital downconverter is converted by circuitry (57) to a complex form, using a method such as an Hubert transform, then mixed down to, for example, 0 Hertz, by a complex mixer (58) that performs the digital downconversion process on this complex data by using the output sine and cosine data from a numerically controlled oscillator (59) as a mixing frequency. The resultant downconverted output from the mixer (58) may then be filtered by a digital filter (60) and, optionally, the filter (60) may perform decimation, such that the data rate into the filter (60) is greater that that exiting the filter (60). The complex output from the filter (60) is the downconverted calibration signal (39) that is used by the calibration data processor (37).

Also, the calibration digital downconverter (32. .35) circuit filters out the desired signal (1) from the combined desired and calibration signals to leave only the filtered calibration signal (40).

As shown in Figure 12, the output of the desired signal filter (28..31) is comprised to a greater extent of the desired signal data bandwidth (63) than calibration data bandwidth (64) as the result of filtering.

In a calibrated example of the invention, the magnitude of the phasors of the output samples from each of the calibration digital downconverters (32.. 35) should have the same value to within a tolerance of acceptability.

The values of magnitude and phase of the phasors of samples at the output of the calibration digital downconverters (32.. 35) may be calculated by the calibration data processor (37), using, for example, a method such as the cordic algorithm.

The calibration signal (26) is generated by a calibration signal generator (5), such as a digital upconverter circuit, and the calibration signal could have different signal formats in terms of its frequency or amplitude, or whether it is modulated, such as modulating a carrier using quadrature phase shift keying or unmodulated, such as a sine wave. The calibration signal (26) shall not have any mean DC content.

The calibration signal generator (5) uses the clock from a single frequency reference oscillator (12) to produce a calibration signal such that it is phase locked to the reference oscillator (12).

In order to perform a calibration to minimise the voltage offset of each channel (Figure 10), it is possible for the calibration data processor (37) to average the filtered calibration signal (26) from each of the calibration digital downconverter (32.. 35) outputs in order to determine the DC offset of each channel (Figure 10). Based on the DC offsets calculated for each channel output, the digital gain and offset adjust circuitry (22. .25) may be controlled by the calibration data processor (37) to modify each ADC (7..10) output data by adding compensating values to the data in each channel (Figure 10).

In another embodiment of the invention, the voltage offset of a channel (Figure 10) may be calculated by measuring the magnitude and phase of the downconverted calibration signal (39) for a given calibration signal (26) phase. The phase of the calibration signal (26) should then be changed and again the magnitude and phase of the downconverted calibration signal (39) should be measured. This process should be repeated, preferably until the downconverted calibration signal phase has been rotated through 360 degrees. From these measurements of magnitude and phase the calibration data processor (37) may perform a curve-fitting function to the measurments to locate the origin of the circle that they describe. The offset of this circle from zero represents the DC offset present in that channel (Figure 10). Based on the DC offsets calculated for each channel output, the digital gain and offset adjust circuitry (22. .25) may be controlled by the calibration data processor (37) to modify each ADC (7..10) output data by adding compensating values per channel (Figure 10).

In order to perform a calibration to equalise the gain differences between the channels (Figure 10), the method and means already described to minimise the voltage offset of each of the channels (Figure 10) should be performed before commencing the following gain equalisation calibration procedure.

By calculating and comparing the phasor magnitudes for each of the downconverted calibration signal (39) outputs in the calibration data processor (37), it is possible for the calibration data processor (37) to calculate the required changes to the values of gain correction of the digital gain and offset adjust elements (22. .25) for each channel (Figure 10)to restrain the values of these calculated phasor magnitudes to within an acceptable range and to effect these changes in the digital gain and offset adjust elements (22. .25) by a multiplication of the data.

In another embodiment of the invention, analogue gain adjust circuitry in the channel (Figure 10) upstream of each ADC (7.. 10) may be used instead of or in addition to the digital gain and offset adjust elements (22. .25).

To combine the signals of each of the desired channel outputs (51) temporally in the signal data processor (36) in order to provide an output (55) that has an elevated sample rate, it is nesessary to ensure that the combined sample instants of the output (55) are spaced equally in time to within an acceptable tolerance.

Both the signal data processor (36) and the calibration data processor (37) use clocks that are phase locked to the reference oscillator (12) which in some implementations of the invention may be an external reference frequency.

The sample clocks to each ADC (7.. 10) are phase locked to the reference oscillator (12) and are produced by the clock generation circuitry (11). They may be delayed by different amounts with respect to each other by using variable delay elements (13) under the control of the calibration data processor (37).

Each ADC output clock is used to clock its own data through the downstream processing functions, such as digital gain and offset adjust elements (22. .25).

In order to perform a calibration to optimise the sample instant timing of the ADCs (7.. 10) the method and means already described to minimise the voltage offset of each of the channels (Figure 10) should be performed before commencing the following sample instant timing calibration procedure.

As a result of the phase locked relationship between the calibration signal (26) and the downconversion process to zero Hz that takes place in each of the channels (Figure 10), it follows that for each of the downconverted calibration signals (39), the phase of any sample calculated by the calibration data processor (37) is represented by phase differences between the sample instant timing of that ADC (7.. 10) from which the sample was derived, and the phase of the calibration signal incident to the input of that ADC (7..10).

The phase of the sample instant timing of that ADC (7.. 10) from which the sample was derived may be varied by changing the time delay introduced by the variable time delay element (13) of that ADC (7..10), thereby changing the angular position on a constellation diagram of any sample whose phase has been calculated by the calibration data processor (37) to an extent that is proportionate to the change of the time delay.

The combined input and calibration signal that is incident to the ADCs (7.. 10) may be subjected to phase modifications which are different from channel to channel and which are caused by variations between the circuitry in the different channels (Figure 10).

Phase differences between the ADC (7..10) sample clocks could also be present as a result of tolerances in the sample clock generation circuitry (11), the sample clock variable delay elements (13) and the interconnections between these circuits, such as PCB tracks.

For the phase of any downconverted calibration signal (39) sample calculated by the calibration data processor (37), both of these sources of phase modifications result in an angular phase position on a constellation diagram which includes a phase offset whose value is proportionate to these channel specific phase differences.

When performing the sample instant timing calibration procedure, since these channel phase differences are included in the measurement of phase for the samples of each channel (Figure 10), the sample instant timing calibration procedure may compensate for them.

By comparing the phase of samples calculated by the calibration data processor (37) for each of the downconverted calibration signals (39) with respect to each of the other channels (Figure 10), it is possible to adjust the sample clock variable delay elements (13) to ensure that samples that are taken from the outputs of the calibration digital downconverters (32. .35) in a round robbin manner are separated from each other by 360/n degrees, where "n" is the number of channels (Figure 10), to within an acceptable tolerance and within the range and resolution of the sample clock variable delay elements (13).

The comparison of the phases of the downconverted calibration signal (39) samples between channels (Figure 10) could be performed on a sample per sample basis across the channels (Figure 10) or in a batched manner, where a number of samples for each channel (Figure 10) are used for each comparison.

In a non-exclusive example of this invention that has four channels (Figure 10), Figures 3. .6 represent constellation diagrams of each of the four channels downconverted calibration signals (39) before any calibration has been applied.

In this non-exclusive example, the calibration signal is a sine wave.

Figures 5 and 6 illustrate the effects of there being different gains in their channels compared to those of Figure 3 and 4.

Figure 4 also illustrates the effect of there being a voltage offset on a channel (Figure 10).

To describe the circle as shown in Figure 4, which has a non-zero origin, the phase of the calibration signal (26) should be rotated through multiple phases, however only a single phase of the calibration signal (26) has been shown in this example for the purposes of clarity.

Figure 7 overlays the constellations of the four channels of Figures 3. .6 where no calibration has been applied to the channels.

Figure 8 overlays the constellation of the four channels where calibration for DC offset, channel gain and sample instant timing between channels has been applied. As there are four channels (Figure 10) in this non-exclusive example, the angular separation between the sample phases of the downconverted calibration signals (39) of sequential channels (Figure 10) has been adjusted to 90 degrees by the calibration process.

The output data (55) is produced by temporally combining the samples of the desired signal filters (28..31) of each channel (Figure 10) in the desired signal data processor (36).

These samples represent data from the desired signal (1) filtered to reduce the presence of the calibration data as shown in Figure 12 where signal data band (63) is dominant over the calibration data band (64).

In another embodiment of this patent for a continuous calibration of multiple time interleaved analogue to digital converters (ADCs), the ADCs (7.. 10) could be replaced by a sampling device, such as a sample and hold amplifier, followed by an analogue to digital converter. Such a combination allows a wider analogue bandwidth to be converted to digital, when the analogue components in the channel (Figure 10) have equivalent analogue bandwidths to such a sampling device, than would be the case with an ADC alone.

In yet another embodiment of this patent, illustrated by Figure 1.1, Figure 1.2 and Figure 1.3b, a sample and hold circuit or device or similar circuit or device (65) is used to sample the combined signal (52) at theoutput of the combiner (2). The sample rate of this sample and hold circuit or device or similar circuit or device (65) is "n times the sample rate of each of the ADCs (7..10) where "n" is the number of ADCs (7..10).

The ADC (7.. 10) sample clocks produced by the sample clock generation circuit (11) and the variable delay elements (13) are controlled by the calibration data processor (37) by the method previously described in this patent, such that the output of the sample and hold circuit or device or similar circuit or device (65) is sampled by the ADCs (7.. 10) within the time period when the sample is held stable by the sample and hold circuit or device or similar circuit or device (65). The ADCs (7.. 10) sample the output of the sample and hold circuit or device or similar circuit or device (65) in a time interleaved manner. This embodiment relaxes the timing accuracy requirement of the sample clocks produced by the sample clock generation circuit (11) and the variable delay elements (13) compared to when no sample and hold circuit or device or similar circuit or device (65) is used.

Claims

Claims What is claimed is 1. a method and means of continuous

calibration of two or more time interleaved analogue to digital converters whose outputs are temporally combined to produce a single digital representation of the measurement signal, whereby a calibration signal is added to the measurement signal that is to be sampled by the time interleaved analogue to digital converters, where the calibration signal occupies a frequency band other than the frequency band occupied by the measurement signal, and after conversion at each analogue to digital converter, the calibration signal and measurement signals are processed separately such that the processing applied to the calibration signal provides information to correct gain, voltage offset and sample instant timing errors between the analogue to digital converters 2. a method and means of calibration according to claim 1, in which the calibration signal is derived from and phase locked to the same reference frequency that is used to generate the analogue to digital converter sample clocks that effect the sample instant timing of the time interleaved analogue to digital converters 3. a method and means of calibration according to claim 2, in which, for each of the time interleaved analogue to digital converter outputs, by applying digital filtering to the .sampled combination of the calibration signal and the measurement sgnal, the calibration signal is separated from the measurement signal in the digital domain 21. a method and means of calibration according to claim 3, in which by using digital downconverter techniques and amplitude and phase measuring techniques, the sampled *::::and filtered version of the calibration signal in each of the time interleaved analogue to 1igital converter channels is converted to baseband, where a measure of its magnitude is * : bbtained and a measure of its phase is obtained with respect to the sample instant timing of the analogue to digital converter by which it was sampled a method and means of calibration according to claim 4, in which the phase measurement made in each of the time interleaved analogue to digital converter channels s compared by a processing means to quantify the offset of each with respect to the other or others 6. a method and means of calibration according to claim 2, in which the sample clocks to each analogue to digital converter are phase adjusted by phase adjusting elements that are controlled by a processing means in order to alter the sample instant timing of each analogue to digital converter 7. a method and means of calibration according to claims 5 and 6, in which the processing means calculates the required phase adjustment to be applied to each analogue to digital converter sample clock and effect each such phase adjustment by controlling phase adjusting elements to position the sample instant timing of each analogue to digital converter with respect to the other or others such that they are temporally equidistant when they have been combined to make them time interleaved 8. a method and means of calibration according to claim 4, in which the magnitude measurement made in each of the time interleaved analogue to digital converter channels is compared by a processing means to quantify the difference of each with respect to the other or others 9. a method and means of calibration according to claim 8, in which the processing means calculates the required multiplication factor to be applied to the samples at the output of each analogue to digital converter to equalise the channel gains across all of the time interleaved analogue to digital converter channels 10. a method and means of calibration according to claim 2, in which the calibration signal phase is adjusted to generate different values of calibration signal phase 11. a method and means of calibration according to claims 7, 8 and 10, in which the processing means calculates the amplitude and phase of the calibration signal in each of the time interleaved analogue to digital converter channels for a sufficient number of different values of calibration signal phase such that the processing means calculates the position of the centre of the circle described by the vector representation of each calibration signal phase value.

12. a method and means of calibration according to claim 11, in which the processing means calculates the required offset factor to be applied to the samples at the output of each analogue to digital converter to minimise the DC voltage offset of each of the time interleaved analogue to digital converters S. * *.* ***. * I S... S... * . *..

*..S.. * S S. * * *. * ** * S.. * S S...