GB2440467A - A semiconductor device having a gate dielectric of different blocking characteristics - Google Patents

A semiconductor device having a gate dielectric of different blocking characteristics Download PDF

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Publication number
GB2440467A
GB2440467A GB0720856A GB0720856A GB2440467A GB 2440467 A GB2440467 A GB 2440467A GB 0720856 A GB0720856 A GB 0720856A GB 0720856 A GB0720856 A GB 0720856A GB 2440467 A GB2440467 A GB 2440467A
Authority
GB
United Kingdom
Prior art keywords
semiconductor device
gate dielectric
blocking characteristics
different blocking
gate insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0720856A
Other versions
GB0720856D0 (en
GB2440467B (en
Inventor
Karsten Wieczorek
Michael Raab
Karla Romero
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102005020058A external-priority patent/DE102005020058B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0720856D0 publication Critical patent/GB0720856D0/en
Publication of GB2440467A publication Critical patent/GB2440467A/en
Application granted granted Critical
Publication of GB2440467B publication Critical patent/GB2440467B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

By locally adapting the blocking capability of gate insulation layers 205A, 205B for N-channel transistors, and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions 205A, 205B.
GB0720856A 2005-04-29 2006-04-19 A semiconductor device having a gate dielectric of different blocking characteristics Expired - Fee Related GB2440467B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102005020058A DE102005020058B4 (en) 2005-04-29 2005-04-29 Production method for a semiconductor device with gate dielectrics with different blocking properties
US11/284,270 US20060244069A1 (en) 2005-04-29 2005-11-21 Semiconductor device having a gate dielectric of different blocking characteristics
PCT/US2006/014628 WO2006118787A1 (en) 2005-04-29 2006-04-19 A semiconductor device having a gate dielectric of different blocking characteristics

Publications (3)

Publication Number Publication Date
GB0720856D0 GB0720856D0 (en) 2007-12-05
GB2440467A true GB2440467A (en) 2008-01-30
GB2440467B GB2440467B (en) 2009-11-25

Family

ID=36809568

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0720856A Expired - Fee Related GB2440467B (en) 2005-04-29 2006-04-19 A semiconductor device having a gate dielectric of different blocking characteristics

Country Status (3)

Country Link
KR (1) KR20080011215A (en)
GB (1) GB2440467B (en)
WO (1) WO2006118787A1 (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5596218A (en) * 1993-10-18 1997-01-21 Digital Equipment Corporation Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation
WO1999052151A1 (en) * 1997-02-28 1999-10-14 Intel Corporation A cmos integrated circuit having pmos and nmos devices with different gate dielectric layers
US20020163011A1 (en) * 1998-07-21 2002-11-07 Lee Tae-Jung Transistors including gate dielectric layers having different nitrogen concentrations and related structures
JP2002334939A (en) * 2001-05-10 2002-11-22 Fujitsu Ltd Semiconductor device and method of manufacturing the same
US20020185693A1 (en) * 2001-06-12 2002-12-12 Yuri Yasuda Semiconductor device and method for manufacturing the same
US6521527B1 (en) * 1993-09-02 2003-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating the same
US20040067619A1 (en) * 2002-10-04 2004-04-08 Hiroaki Niimi Method for non-thermally nitrided gate formation for high voltage devices
US20040171209A1 (en) * 2000-08-17 2004-09-02 Moore John T. Novel masked nitrogen enhanced gate oxide
US20040232499A1 (en) * 2002-10-29 2004-11-25 Hynix Semiconductor Inc. Transistor in semiconductor devices and method of fabricating the same
US20040232516A1 (en) * 2001-07-18 2004-11-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
WO2005036641A1 (en) * 2003-09-09 2005-04-21 International Business Machines Corporation Method for separately optimizing thin gate dielectric of pmos and nmos transistors within the same semiconductor chip and device manufactured thereby
WO2006031425A2 (en) * 2004-08-27 2006-03-23 Texas Instruments Incorporated Cmos device having different nitrogen amounts in nmos and pmos gate dielectric layers

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521527B1 (en) * 1993-09-02 2003-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of fabricating the same
US5596218A (en) * 1993-10-18 1997-01-21 Digital Equipment Corporation Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation
WO1999052151A1 (en) * 1997-02-28 1999-10-14 Intel Corporation A cmos integrated circuit having pmos and nmos devices with different gate dielectric layers
US20020163011A1 (en) * 1998-07-21 2002-11-07 Lee Tae-Jung Transistors including gate dielectric layers having different nitrogen concentrations and related structures
US20040171209A1 (en) * 2000-08-17 2004-09-02 Moore John T. Novel masked nitrogen enhanced gate oxide
JP2002334939A (en) * 2001-05-10 2002-11-22 Fujitsu Ltd Semiconductor device and method of manufacturing the same
US20020185693A1 (en) * 2001-06-12 2002-12-12 Yuri Yasuda Semiconductor device and method for manufacturing the same
US20040232516A1 (en) * 2001-07-18 2004-11-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US20040067619A1 (en) * 2002-10-04 2004-04-08 Hiroaki Niimi Method for non-thermally nitrided gate formation for high voltage devices
US20040232499A1 (en) * 2002-10-29 2004-11-25 Hynix Semiconductor Inc. Transistor in semiconductor devices and method of fabricating the same
WO2005036641A1 (en) * 2003-09-09 2005-04-21 International Business Machines Corporation Method for separately optimizing thin gate dielectric of pmos and nmos transistors within the same semiconductor chip and device manufactured thereby
WO2006031425A2 (en) * 2004-08-27 2006-03-23 Texas Instruments Incorporated Cmos device having different nitrogen amounts in nmos and pmos gate dielectric layers

Also Published As

Publication number Publication date
GB0720856D0 (en) 2007-12-05
KR20080011215A (en) 2008-01-31
GB2440467B (en) 2009-11-25
WO2006118787A1 (en) 2006-11-09

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20120419