GB2439115A

GB2439115A - ADC filter

Info

Publication number: GB2439115A
Application number: GB0611810A
Authority: GB
Inventors: Robert Carter
Original assignee: Siemens PLC
Current assignee: Siemens PLC
Priority date: 2006-06-15
Filing date: 2006-06-15
Publication date: 2007-12-19
Also published as: GB0611810D0

Abstract

A decimation filter for use with a delta-sigma analogue-to-digital converter comprises a finite impulse response (FIR) filter and a first-order sinc filter. The sinc filter comprises a counter adapted to receive an input clock and a decimation clock as well as input data, a latch adapted to receive the decimation clock and the input data following passage through the FIR filter, an adder/subtractor adapted to receive the output from the latch as well as the outputs from the counter and the FIR filter, and a register adapted to receive the output from the adder/subtractor and the decimation clock.

Description

ADC Filter This invention relates to Analogue to Digital Converters

(ADC's), and in particular to delta sigma ADCs.

Figure 1 shows a Delta Sigma A/D converter comprising Delta-Sigma modulator portion 1 and decimation filter portion 2.

Figure 2 a) and b) show the architecture and hardware respectively of a order filter arrangement of a A/D converter. Input X(z) a stream of bits either I s or Os (zeros), which represent an analogue value. Output from the filter arrangement is Y(z) which represents an integer. The filter essentially comprises latches 3 and 4. Input to the first latch 3 (essentially a counter) is an input clock and input to the second latch is a decimation clock. Essentially the purpose of the decimation clock is to allow the sampling of the input over a finite period. The hardware implementation of this is very simple. However the problem with such a 1st order system is that it gives limited resolution.

In ordered to improve the accuracy 2' order decimation filters are known. This gives twice the comparable resolution of the 1st order filter. Figures 2 a) and b) show architecture and hardware a second order filter arrangement also typically used in ADC's. It comprises a counter 3 and a number of latches 4, 5 and 6, the latter two of which act as differentiators. As can be seen the two decimation clocks are required as well as three adder/subtractors. The disadvantage of this arrangement is that the filter is complex and large in comparison. For example the adder! subtractor requirements make the 2nd order filter substantially more complex.

As a compromise between the two types of filter, a known solution is to use an intermediate order decimation filter as it gives a useful increase in accuracy without the extra V2 sample period delay inherent in the 2 order decimation filter. The intermediate design has been achieved by delaying the second decimation clock with

L

respect to the main decimation clock in the ordinary 2h1 order design. Effectively the intermediate order filter is created by separating the two decimation clocks into two decimation registers. However the output is not available until after the 2nd decimation clock has happened. Thus a problem with the intermediate design however is that it gives awkward timing problems. It is an object of the invention to provide a relatively simple hardware implementation for a filter.

Figure 4 shows a comparison of the various impulse responses of the various aforementioned filters. The thick arrows where appropriate represent the first decimation clock (or decimation clock where there is only one) and the thin arrows represent the second decimation clock; as can be seen the response in the first order filter is a step, i.e. the output is at one level or zero. The reposed in the 2 order system is a pyramid type response, where the output ramps up in variable fashion to a peak and then ramps down. The intermediate filter response has a response which could be described as a hybrid between the two; it ramps up to a plateau and then ramps down again.

it is an object of the invention to overcome the above problems arid provide a decimation filter which is simple in terms of architecture yet provides improved performance in terms of resolution and response.

The invention comprises a filter comprising a FIR filter and a 1 order sine filter.

The 1St order sinc filter comprises a counter, adapted to receive an input clock and a decimation clock as well as input data, and a register adapted to receive the decimation clock and a measure of the output of the counter.

The FIR filter provides to a stepped response to an impulse of one or more steps.

The design of the intermediate decimation filter according to the invention creates an enhancement to a 1st order decimation filter using Finite Impulse Response (FIR) filter techniques to give a useful resolution increase of up to about 5 bits in a practical system. The normal decimation filter timing problems (2nd order clock is delayed from the 1st order clock) are avoided because the FIR filter part uses data clocked previously.

Figure 5a shows an simple embodiment of the invention that adds one bit resolution.

It simply comprises a counter 8, into which is input the digital data stream, as well as a clock and a decimation clock. The output of the counter is input to the adding part of an adder. Further the input data and decimation clock are input to a latch 9, the output of which is also input to the add part of a adder/subtractor. The output of the adder/subtractor is input to the register along with the decimation clock. The Finite Impulse Response of this arrangement is shown in figure 6a.

Figure 5b shows a more practical embodiment of the invention which adds two extra bits resolution. A counter 8, latch 9 and adder/subtractor are present as before. There are two latches 11 and 12 which effectively form a shift register. Multipliers 13 and 14 multiply the input data and output from latch 12 by 3 and 2 respectively, these are then summed and input to the subtraetor part of the adder/subtractor, as well as the register/latch. As before the output of the latch is input to the adder part of the adder/s ubtractor. When an impulse is input into the counter the output of the counter is shifted to the left by 2 positions giving an output factor of 4 (i.e. a move by 2 binary places). The 3x multiplier outputs a 3 to the subtractor part of the adder and together with the 4, this results in a step of 1. At the next clock count the x2 multiplier kicks in together with the output of I from the second latch of the pair to give a of 3. This continues and the finite impulse response of the arrangement is shown in figure 6b.

Figure 5c shows a further embodiment of the invention which provides 3 extra bits resolution. The FIR filter portion, shown by dotted line includes a shift register of six latches, and multipliers as shown. This continues and the finite impulse response of the arrangement is shown in figure 6c.

The FIR filter section is shift register + multipliers + summing part (adder).

For the "1 extra bit" case, the shift register has zero length and the multiplier is xl (ie effectively just a bit of wire) and the adder only has the one input.

Claims

Claims 1. A filter comprising a FIR filter and a 1st order sinc

filter.

2. A filter as claimed in claim I wherein said 1st order sinc filter comprises a counter, adapted to receive an input clock and a decimation clock as well as input data, and a register adapted to receive the decimation clock and a measure of the output of the counter.

3 A filter as claimed in claim I or 2 where said FIR filter provides to a stepped response to an impulse of one or more steps.

4. A filter as claimed in claim 1 wherein said FIR filter includes a primary latch and an adder/subtractor, said latch adapted to receive an input clock and a decimation clock, said adder adapted to receive the output from the counter, the latch and the input data, and where the register adapted to receive the output from the adder.

5. A filter as claimed in claim 1, said filter comprising a counter, adapted to receive an input clock and a decimation clock as well as input data, a counter/latch adapted to receive the decimation clock and the input data, an adder/subtrátor adapted to receive the output from the latch, the input data and the output from a latch and a register, the decimation clock and the output from the adder.

6. A filter as claimed in claim 6 including shift register and a plurality of multipliers, and a summer.

7. A filter as darned in claim 6 wherein one of the multipliers is located between input data line and the summer, and at least one multiplier is located between the shift register and the summer. c

8. A filter wherein said shift register comprises a cascaded series of latches and wherein the connection between each of them connects to a multiplier.

9. A filter as claimed in wherein said the output to said summer is fed to both the adder/subtractor and the primary latch.

10. A filter as claimed in any preceding claim which is a decimation filter for an ADC.