GB2426133A

GB2426133A - Clock generation circuit mixing two oscillator signals

Info

Publication number: GB2426133A
Application number: GB0609026A
Authority: GB
Inventors: Michael Louis Frank; Mark A Unkrich
Original assignee: Avago Technologies General IP Singapore Pte Ltd
Current assignee: Avago Technologies International Sales Pte Ltd
Priority date: 2005-05-13
Filing date: 2006-05-05
Publication date: 2006-11-15
Also published as: CN1972127A; TW200700958A; JP2006318478A; CN1972127B; GB0609026D0; JP4926539B2; TWI402658B

Abstract

A first and a second resonator (12A, 14A) are fabricated monolithically adjacent to one another. The first resonator (12A) is the reference resonator. The resonant frequency of the second resonator (14A) is offset by a difference frequency Fo from the first resonator. Each resonator (12A, 14A) is included within an oscillator (12, 14). A mixer (16) receives the output of both oscillators (12, 14). A low pass filter (18) receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo. The resonators may be film bulk acoustic resonators (FBARs). The circuit may comprise a first and second register 26, 28 for storing a preferred oscillator and temperature compensation setting which adjust at least one of the oscillators. The oscillators may be adjusted by a modulation source. The oscillators may be VCOs or DCOs.

Description

CLOCK GENERATION CIRCUIT AND DEVICE

The present invention relates to a clock generation circuit and to a device including a clock generation circuit.

Several methods exist to generate low frequency system reference clocks.

Currently the most common uses a crystal-based oscillator utilizing quartz for the crystal element. Crystal oscillators can be temperature compensated. The fundamental resonant frequency of the crystal typically ranges from below 10MHz up to perhaps 70MHz. This tone is then used in a phase lock ioop to control a higher frequency voltage controlled oscillator that generatel the desired frequency of operation of the system. The temperature controlled crystal oscillator typically costs between $0.30 and $1.00 depending upon performance requirements and is considered a commodity in many markets with manufacturers competing primarily on price.

In addition to the cost impact, a crystal oscillator is slow to start, as the crystal itself must go through many periods before there is sufficient energy to support the oscillation.

This start up time is inefficient as the radio cannot function until it is done.

The present invention seeks to provide improved clock generation and improved devices which rely upon a clock.

According to an aspect of the present invention, there is provided a clock generation circuit as specified in claim 1.

According to another aspect of the present invention, there is provided a device as specified in claim 8.

The preferred embodiment provides an energy efficient, small, and inexpensive clock for use in integrated circuit designs. In a preferred embodiment, a first and a second resonator are fabricated monolithically adjacent tó one another. The first resonator is the reference resonator. The resonator frequency of the second resonator is offset by a difference frequency Fo from the first resonator. Each resonator is included within an oscillator. A mixer receives the output of both oscillators. A low pass filter received the mixer output and generates a clock signal whose frequency is equal to the difference frequency Fo.

Embodiments of the present invention are described below, by way of example only, with reference to the accompanying drawings, in which: Figure 1 shows an embodiment of clock generation circuit; Figure 2 shows an embodiment of programmable clock generation circuit; Figure 3 shows another embodiment of programmable clock circuit; and Figure 4 shows another embodiment of programmable clock circuit.

Figure 1 shows an embodiment 10 of clock circuit. A first and a second resonator 12A, 14A, are fabricated monolithically adjacent to one another. The first resonator 12A is the reference resonator. The resonator frequency of the second resonator 14A is offset by a difference frequency Fo from the first resonator 12A. Each resonator 12A, 14A is included within an oscillator 12, 14, respectively. A mixer 16 receives the output of both oscillators 12, 14. A low pass filter 18 receives the mixer output and generates a clock signal whose frequency is equal to the difference frequency, Fo. In principle, this offset frequency can range from DC to many GHz. A practical frequency offset includes the typical range of crystal oscillators and may be considerably extended in range at high frequencies. Thus, this scheme could easily generate a frequency between 10 and 500MHz.

The oscillation frequencies are determined by the resonant frequency of the respective resonator. The mixer output signal includes a high frequency component in the range of the resonant frequencies and low frequency component having a frequency proportional to the difference frequency Fo of the two oscillators. The low frequency component may be extracted using a low pass filter to generate the desired lower frequency clock signal.

The resonators may be Film Bulk Acoustic Resonators (FBARs). The FBAR can be built on a semiconductor substrate, such as silicon. Similarly, the rest of the oscillator circuit, excluding the FBAR, is built on a semiconductor substrate using CMOS, Bipolar, or BICMOS processes. This allows for a variety of manufacturing packaging and integration strategies to create a clock generation circuit. The resonator may be directly attached to the rest of the oscillator during the packaging process by flip-chip interconnect of the FBAR device or die stacking and wire bonding the devices together, for example. Alternatively, by combining the semiconductor processing, the FBAR device may be integrated directly with the oscillator circuit on the same substrate.

Alternately, the FBAR device may be adjacent to the oscillator circuit together on a separate substrate, with electrical connections provided by flip-chip interconnect or wire * 3 bonding and electrically connected to the substrate through wire bonding. The resonators can be fabricated to have tracking different coefficients of temperature drift. In a preferred embodiment, the temperature coefficients are designed such that so that the * difference.frequency is constant with temperature.

The oscillator clock generation circuit may be attached to a substrate as a separate die, e.g. to using as an illustrative example flip-chipping or die stacking technology. in this embodiment, a die, that includes The oscillator clock generatiOn circuit is attached by either flipping the oscillator component onto a transceiver integrated circuit (IC) and also connecting the l/Opacls or attaching it fhce up and using bond wires to make the connections. Alternatively, the oscillator clock generation circuit may be fabricated on the same substrate as an as integrated circuit.

Figure 2 illustrates another embodiment, in which programmability of the. output frequency is included while improving the accuracy and temperature characteristics of the oscillator. A temperature monitoring circuit 20 and a temperature control circuit 22 provide inputs to a VCO control circuit 24. A first register 26 stores a selected oscillator frequency ofthet setting. A second register 28 stores a temperature compensation setting.

The YCO control circuit 24 receives the values from the first and the second registers 26, 28.

The second oscillator 14 is a voltage controlled oscillator (VCO) or digitally controlled oscillator that allows the frequency of the oscillation to be modified by changing a control voltage or digital control value. A corresponding change in the output clock frequency occurs with a change in the frequency of the second oscillator 14 since the output clock frequency is equal tO the difference between the difference of the two oscillators.

When a specific output clock frequency in manufacturing is desired, it may be set by measuring the output clock frequency for various control values, e.g. voltage or digital. In the next step, the desired output frequency is programmed and may be stored in a register.

With inclusion of a temperature monitoring and control circuits 20, 22 on the substrate, the effects of temperature may be cancelled out. Sensing temperature using diodes or other semiconductor devices built into the substrate is well known. The sensed temperature of the substrate provides a control values to the temperature control circuit.

Typically, this responds in a linear manner to a linear change in control value bjy but may be non- linear depending upon the requirements of the system if the temperature monitor is non- linear or the VCO control is non- linear. By measuring the output clock frequency at a second temperature, a second register, may be programmed and adjusted until the output frequency matches the desired frequency. This second register provides temperature compensation of the output clock frequency.

Figure 3 illustrates another embodiment. The first and second oscillators 12, 14 may both be VCOs receiving the output of the VCO control circuit 24. This provides symmetric design of the oscillators used to generate the difference frequency for the output clock frequency. By matching the design of the VCOs, the frequency changes due to process variataions wilI. track To maintain the matching of the biasing of the VCOS VCOs requires symmetric application of the control for to both of them.

To illustrate, if the first oscillator 12 can adjust between frequency F1A and FiB, where F1A <FiB, and the second oscillator 14 can adjust between frequency F2A and* F2B, where F2A< F2B and F1A< F1B<F2A< F2B, then for one extreme of the control value, the first oscillator 12 would operate at frequency F1A and the second oscillator 14 would operate at frequency F2B yielding the maximum value for the difference frequency F2B - F1A at the output. At the other extreme of the control value, the first oscillator 12 would operate at frequency FIB and the second oscillator 14 would operate at frequency F2A yielding the minimum value of the difference frequency F2A - FiB at the output. Symmetric design would match the amount of change in the first oscillator 12 with that of the second oscillator 14 in a continuous manner.

Figure 4 illustrates another embodiment. An input signal is added to the VCO control circuit 24. The input signal may be a modulation source whereby the data represented at the signal Vin will modulate the carrier frequency, e.g. a simple form of Frequency Shift Keying (P5K). At the output, the output clock is now the carrier frequency with a modulated FSK signal on top of the carrier. 5.

The disclosures in United States patent application nos. 60/681,198 and 11/232,581, from which this application claims priority, and in the abstract accompanying this application are incorporated herein by reference.

Claims

1. A clock generation circuit including: a first oscillator including a resonator providing a first resonant frequency and an oscillator output; a second oscillator including a resonator providing a second resonant frequency and an oscillator output; wherein the first and second resonant frequencies are separated by a difference frequency; a mixer operable to receive each of the oscillator outputs and to generate a mixer output signal; and a low pass filter operable to receive the mixer output signal and to generate a clock signal that is proportional to the difference frequency.

2. A clock generation circuit according to claim 1, wherein the resonators are selected from a group that includes film bulk acoustic resonators.

3. A clock generation circuit according to claim 1 or 2, including a substrate that integrates the first and second oscillators, mixer, and low pass filter.

4. A clock generation circuit according to any preceding claim, including: a first register for storing a preferred oscillator setting; one of the first and the second oscillators being adjustable by the preferred oscillator setting.

5. A clock generation circuit according to claim 4, including: a second register for storing a temperature compensation setting; the one of the first and the second oscillators being adjustable by the temperature compensation setting.

6. A clock generation circuit according to claim 5, wherein the other of the first and the second oscillators is adjustable by at least one of the preferred oscillator setting and the temperature compensation setting.

7. A clock generation circuit according to claim 6, wherein one of the first and the second oscillators is adjustable by a modulation source.

8. A device including: a substrate; and a clock generation circuit, positioned proximate to the substrate, including, a first oscillator including a resonator providing a first resonant frequency and an oscillator output, a second oscillator including a resonator providing a second resonant frequency and an oscillator output, wherein the first and second resonant frequencies are separated by a difference frequency, a mixer operable to receive each of the oscillator outputs and to generate a mixer output signal, and a low pass filter operable to receive the mixer output signal and to generate a clock signal that proportional to the difference frequency.

9. A device according to claim 8, wherein the clock generation circuit is monolithically integrated in the substrate.

10. A device according to claim 8, wherein the clock generation circuit is attached to the substrate using flip chip technology.

11. A device according to claim 8, wherein the clock generation circuit is attached to the substrate using die stacking technology.

12. A device according to claim 8, 9, 10 or 11, wherein the clock generation circuit is adjacent to the substrate using a common leadframe.

13. A device according to any one of claims 8 to 12, including: a first register for storing a preferred oscillator setting; one of the first and the second oscillators being adjustable by the preferred oscillator setting.

14. A device according to claim 14, including: a second register for storing a temperature compensation setting; the one of the first and the second oscillators being adjustable by the temperature compensation setting.

15. A device according to claim 15, wherein the other of the first and the second oscillators is adjustable by at least one of the preferred oscillator setting and the temperature compensation setting.

16. A device according to claim 15, wherein one of the first and the second oscillators is adjustable by a modulation source.

17. A clock generation circuit substantially as hereinbefore described with reference to and as illustrated in any one of the accompanying drawings.

18. A device including a clock substantially as hereinbefore described with reference to and as illustrated in any one of the accompanying drawings.