GB2423166A - Simulating a hard disk - Google Patents

Simulating a hard disk Download PDF

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Publication number
GB2423166A
GB2423166A GB0519078A GB0519078A GB2423166A GB 2423166 A GB2423166 A GB 2423166A GB 0519078 A GB0519078 A GB 0519078A GB 0519078 A GB0519078 A GB 0519078A GB 2423166 A GB2423166 A GB 2423166A
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Prior art keywords
read
hard disk
memory
write
write signal
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Granted
Application number
GB0519078A
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GB2423166B (en
GB0519078D0 (en
Inventor
An-Sheng Chang
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Giga Byte Technology Co Ltd
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Giga Byte Technology Co Ltd
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Priority to GB0519078A priority Critical patent/GB2423166B/en
Publication of GB0519078D0 publication Critical patent/GB0519078D0/en
Publication of GB2423166A publication Critical patent/GB2423166A/en
Application granted granted Critical
Publication of GB2423166B publication Critical patent/GB2423166B/en
Expired - Fee Related legal-status Critical Current
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

A device and a method for simulating a hard disk are disclosed. The device has a core logic chip, a main memory module and a setting module. The setting module is used to set the main memory module to have a memory access area and a hard disk access area. The core logic chip has a memory controller and a conversion interface controller for controlling data reading of the memory access area and the hard disk access area, respectively. When the core logic chip receives a read/write signal sent to the main memory module from a computer system, it determines whether this read/write signal is a memory read/write signal or a hard disk read/write signal. If the read/write signal is for memory, it is sent to the memory controller; if the read/write signal is for hard disk, it is sent to the conversion interface controller.

Description

DEVICE AND METHOD FOR SIMULATING A RARD DISK
The present invention relates to a device and method for simulating a hard disk and, more particularly, to a device and method using a memory to simulate a hard disk.
With the continued popularity of computers, the computer functions have become more and more powerful, and more and more peripherals have been developed which are supported by computers, such as card readers, USB devices, IEEE 1394 devices, and so on. With the enhancement of software technology and availablility of various kinds of software in the market, users have become accustomed to using computers more and more frequently. Computers have become indispensable tools in everyday life, and they usually store various kinds of data for user access.
However, it still takes a lot of time for a computer to search for data. Much data is stored on the hard disk of a computer. Due to the structure of a hard disk, much of the access time is wasted in the seek-time for moving the magnetic head and the rotation time of the spindle motor.
These are the primary reasons that the data access speed for a hard disk is not comparable to that for solid state memory. Therefore, when a computer accesses data in a hard disk, even though the central processor is fast, it still needs to wait for the data processing time of the hard disk.
In order to increase the speed of hard disk, US Pat. No. 5,594,926 discloses a hard disk accelerating system for a computer, in which an 10 instruction issued by a conventional central processor is separated into a read operation and a write operation that can be performed simultaneously. Moreover, a programmable hardware register adjusts the hard disk 10 cycle time to achieve maximum compatibility with different hard drive speeds. The above US patent still stores data in hard disks. Therefore, when accessing data in a hard disk, the waste in the seek-time for moving the magnetic head and the rotation time of the spindle motor cannot be avoided.
An object of the present invention is to provide a device and method for simulating a hard disk, in which a simulated hard disk is provided in a solid state memory (e.g. main memory module) to increase the speed of the computer.
The invention is defined in the independent claims.
In one embodiment, the present invention provides a device for simulating a hard disk and used in a computer system. The device for simulating a hard disk comprises a main memory module, at least including a memory, a setting module used to set the main memory module to have a memory access area and a hard disk access area, and a core logic chip. The core logic chip comprises a core logic body for controlling read/write of data of the main memory module, a memory controller connected to the core logic body and used for receiving a memory read/write signal to control read/write of data of the memory access area, and a conversion interface controller connected to the core logic body and used for receiving a hard disk read/write signal to control read/write of data of the hard disk access area. The conversion interface controller also converts the hard disk read/write signal to the memory read/write signal. When the core logic chip receives a read/write signal sent to the main memory module from the computer system, it determines whether the read/write signal is a memory read/write signal or a hard disk read/write signal. The read/write signal will be sent to the memory controller if it is a memory read/write signal, and the read/write signal will be sent to the conversion interface controller it if is a hard disk read/write signal.
In a preferred embodiment, the present invention also provides a method for simulating a hard disk and used in a computer system. The method for simulating a hard disk comprises the steps of: setting a main memory module in the computer system to have a memory access area and a hard disk access area; providing a core logic chip having a memory controller for controlling data access of the memory access area and a conversion interface controller for controlling data access of the hard disk access area; using the core logic chip to receive a read/write signal sent to the main memory module from the computer system and determine whether the read/write signal is a memory read/write signal or a hard disk read/write signal; sending the read/write signal to the memory controller if it is a memory read/write signal; and sending the read/write signal to the conversion interface controller if it is a hard disk read/write signal.
In this manner a simulated hard disk is provided in e.g. the main memory module. Data can be stored in the simulated hard disk to effectively increase the speed of the computer.
Preferred embodiments of the invention are described below by way of example only with reference to Figures 1 to 3 of the accompanying drawings wherein: Fig. 1 is a system architecture diagram of a device for simulating a hard disk according to a preferred embodiment of the present invention; Fig. 2 is a system architecture diagram of a device for simulating a hard disk according to another preferred embodiment of the present invention; and Fig. 3 is a flowchart of a method for simulating a hard disk according to a preferred embodiment of the present invention.
The preferred embodiments allow the memory of a computer system to have the function of hard disk access.
Part of the capacity in the solid state memory is used as a simulated hard disk, and data is stored in this partition.
Because the data access speed of solid state memory is much faster than that of a hard disk, the speed of a computer can be enhanced.
As shown in Fig. 1, a device for simulating a hard disk according to a preferred embodiment of the present invention comprises a central processor 10, a core logic chip 11, a main memory module 12, a setting module 13, a south bridge chip 14 and a hard disk 15. The core logic chip 11 further comprises a core logic body 111, a memory controller 112 and a conversion interface controller 113. The memory controller 112 and the conversion interface controller 113 are connected to the core logic body 111. The core logic body 111 is used to control data read/write of the main memory module 12. The conversion interface controller 113 is used to receive a memory read/write signal, and controls read/write of data stored in the main memory module 12 based on this memory read/write signal. The conversion interface controller 113 is used to receive a hard disk read/write signal, and provides format conversion for this hard disk read/write signal and converts it to a memory read/write signal compatible with the main memory module 12. The conversion interface controller 113 then controls read/write of data stored in the main memory module 12 based on this converted memory read/write signal. The core logic chip 11 can receive a read/write signal sent to the main memory module 12 from the computer system and determines whether this read/write signal is a memory read/write signal or a hard disk read/write signal. If the read/write signal is a memory read/write signal, it is sent to the memory controller 112; if the read/write signal is a hard disk read/write signal, it is sent to the conversion interface controller 113.
The main memory module 12 is connected to the core logic chip 11, and is used to receive a memory read/write signal output by the memory controller 112 or the conversion interface controller 113. The main memory module 12 is composed of a plurality of solid state memories 121. These memories 121 belong to the category of volatile memories with faster read speeds such as SDRAM, DDRAM, and so on. In this embodiment, in addition to providing storage of data or program for execution of the computer system, the main memory module 12 can also be used as a simulated hard disk.
The setting module 13 sets the main memory module 12 to have a memory access area as the primary memory in the computer system and a hard disk access area as the simulated hard disk. The computer system discriminates the main memory system 12 according to this setting. Because the memories 121 used in the main memory module 12 are volatile, in order to avoid loss of data due to no power source when the computer system is turned off, a power source 16 is also provided for the main memory module 12 to ensure that the hard disk access area used as a simulated hard disk in the main memory module 12 can still keep data. This power source is a backup power source in the computer system or a battery (e.g. a mercury cell) In this embodiment, the setting module 13 is connected to the south bridge chip 14. While setting the main memory module 12, the above memory access area and hard disk access area are partitioned with the memory 121 in the main memory module 12 as the unit. After being set by the setting module 12 and rebooted, the computer system can discriminate between the hard disk 15 connected to the south bridge 14 and the simulated hard disk in the main memory module 12.
This embodiment uses the main memory module 12 to simulate a hard disk. For this computer system, performing data read/write to this simulated hard disk is just like performing data read/write to a common hard disk. When the central processor 10 sends out a hard disk read/write signal, if the data to be accessed by this hard disk read/write signal are in the hard disk 15, this hard disk read/write signal will be transferred to the hard disk 15 via the south bridge chip 14; if the data to be accessed by this hard disk read/write signal are in the hard disk access area in the main memory module 12, this hard disk read/write signal will be transferred to the hard disk access area in the main memory module 12 via the conversion interface controller 113.
The above core logic chip 11 is a north bridge chip.
The conversion interface controller 113 is a hard disk interface to memory interface controller. The hard disk interface can be IDE or SATA interface. The setting module 13 is a basic input/output system (BIOS) Fig. 2 is a system architecture diagram of a device for simulating a hard disk according to another preferred embodiment of the present invention. This embodiment is different from the above embodiment in that the core logic chip 17 is a chip integrating north bridge and south bridge, and the setting module 13 and the hard disk 15 are connected to the core logic chip 17. The operation of the simulated hard disk in this embodiment is the same as in the above embodiment. That is, a hard disk access area as a simulated hard disk is formed in the main memory module 12.
Fig. 3 is a flowchart of a method for simulating a hard disk according to a preferred embodiment of the present invention. The method for simulating a hard disk of the present invention comprises the following steps. First, the computers is booted (Step S30l) . The setting module is then entered (Step S303) . Next, the size of the simulated hard disk is set (Step S305) . The computer partitions the main memory module according to the set size of the simulated hard disk (Step S307) . Subsequently, a simulated hard disk is generated in the main memory module 12 (Step S309) . At this time, the main memory module 12 has a memory access area and a hard disk access area. Finally, the setting module 13 stores the above setting (Step S311) . Therefore, after the computer is rebooted, it can discriminate the simulated hard disk in the main memory module 12.
The above device and method allow a main memory module in a computer to function as a virtual hard disk. A large amount of data that will be used in the conventional hard disk can be placed in the virtual (i.e. simulated) hard disk in the main memory module to enhance greatly the speed of the computer.
Besides, using the hardware architecture of the main memory module to simulate a hard disk has the following advantages.
1. The read/write speed of the simulated hard disk is synchronous with the processing speed of the main memory, hence having no wait time.
2. The setting of the simulated hard disk is accomplished with the BIOS, and the computer can automatically discriminate the simulated hard disk after setting without using a driver.
3. Data read/write control of the simulated hard disk is managed by the conversion interface controller without any waste of the resources of the computer system.
4. The preferred embodiments of the present invention are compatible with any operating system.
5. There is no cost burden.
Although the present invention has been described with reference to preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined the appended claims.

Claims (20)

  1. CLAIMS: 1. An arrangement for simulating a hard disk used in a computer
    system, comprising: a main memory module, at least including a memory; a setting module used to set said main memory module to have a memory access area and a hard disk access area; and a core logic chip comprising: a core logic body for controlling read/write of data of said main memory module; a memory controller connected to said core logic body and used for receiving a memory read/write signal to control reading and writing of data of said memory access area; and a conversion interface controller connected to said core logic body and used for receiving a hard disk read/write signal to control reading and writing of data of said hard disk access area, said conversion interface controller also converting said hard disk read/write signal to said memory read/write signal; whereby in use said core logic chip receives a read/write signal sent to said main memory module from said computer system and determines whether said read/write signal is a memory read/write signal or a hard disk read/write signal, wherein said read/write signal is sent to said memory controller if said read/write signal is a memory read/write signal, and said read/write signal is sent to said conversion interface controller if said read/write signal is a hard disk read/write signal.
  2. 2. The arrangement as claimed in claim 1, wherein said memory is a volatile memory.
  3. 3. The arrangement as claimed in claim 1 or claim 2, wherein said setting module is a BIOS.
  4. 4. The arrangement as claimed in any preceding claim, wherein said core logic chip is a north bridge chip.
  5. 5. The arrangement as claimed in any of claims 1 to 3, wherein said core logic chip is a chip integrating a north bridge and a south bridge.
  6. 6. The arrangement as claimed in any preceding claim, wherein said conversion interface controller is a hard disk interface-to-memory interface controller.
  7. 7. The arrangement as claimed in any preceding claim, further comprising a power source connected to said main memory module.
  8. 8. The arrangement as claimed in claim 7, wherein said power source is a backup power source in said computer system or a battery.
  9. 9. A method for simulating a hard disk used in a computer system, the method comprising the steps of: setting a main memory module in said computer system to have a memory access area and a hard disk access area; providing a core logic chip having a memory controller for controlling data access of said memory access area and a conversion interface controller for controlling data access of said hard disk access area; using said core logic chip to receive a read/write signal sent to said main memory module from said computer system and determine whether said read/write signal is a memory read/write signal or a hard disk read/write signal; sending said read/write signal to said memory controller if said read/write signal is a memory read/write signal; and sending said read/write signal to said conversion interface controller if said read/write signal is a hard disk read/write signal.
  10. 10. The method as claimed in claim 9, wherein a BIOS of said computer system is used to set said main memory module in said step of setting said computer system.
  11. 11. The method as claimed in claim 9 or claim 10, wherein said core logic chip is a north bridge chip.
  12. 12. The method as claimed in claim 9 or claim 10, wherein said core logic chip is a chip integrating a north bridge and south bridge.
  13. 13. The method as claimed in any of claims 9 to 12, wherein said conversion interface controller is a hard disk interface-to-memory interface controller.
  14. 14. The method as claimed in any of claims 9 to 13, further comprising a step of providing a power source for said main memory module.
  15. 15. The method as claimed in claim 14, wherein said power source is a backup power source in said computer system or a battery.
  16. 16. A virtual hard disk arrangement for a computer, the arrangement comprising a solid state memory partitioned into a hard disk area, a conversion interface controller arranged to receive hard disk read/write signals, convert them to memory read/write signals, and to send said memory read/write signals to said hard disk area.
  17. 17. A computer comprising an arrangement as claimed in any of claims 1 to 8 or 16, the computer being arranged to store setting information of said hard disk area and to retrieve said information to partition said memory on re-booting.
  18. 18. A method of simulating a hard disk in a computer, the method comprising converting hard disk read/write signals to memory read/write signals and sending said memory read/write signals to a hard disk area into which a solid state memory is partitioned.
  19. 19. A virtual hard disk arrangement substantially as described hereinabove with reference to Figure 1 or Figure 2 in conjunction with Figure 3 of the accompanying drawings.
  20. 20. A method of simulating a hard disk arrangement substantially as described hereinabove with reference to Figures 1 and 3 or Figures 2 and 3 of the accompanying drawings.
    20. A method of simulating a hard disk arrangement substantially as described hereinabove with reference to Figures 1 and 3 or Figures 2 and 3 of the accompanying drawings.
    Amendments to the claims have been filed as follows CLAIMS: 1. A virtual hard disk arrangement for a computer, the arrangement comprising a computer main memory partitioned into a hard disk area, and a conversion interface controller arranged to receive hard disk read/write signals, convert them to memory read/write signals, and to send said memory read/write signals to said hard disk area.
    2. A virtual hard disk arrangement for a computer as claimed in claim i, further comprising: a main memory module, including said computer main memory; a setting module used to partition said main memory module into a memory area and said hard disk area; and a core logic chip comprising: a core logic body for controlling read/write of data of said main memory module; a memory controller and said conversion interface controller both Connected to said core logic body; wherein in use said core logic chip receives read/write signals sent to said main memory module from said computer system and determines whether said read/write signals are memory read/write signals or hard disk read/write signals, wherein said read/write signals are sent to said memory controller if said read/write signals are memory read/write signals, to control reading and writing of data of said memory area; and said read/write signals are sent to said conversion interface controller if said read/write signals are hard disk read/write signals.
    3. An arrangement as claimed in claim 1 or claim 2, wherein said computer main memory is a volatile memory.
    4. An arranqeme as claimed in claim 2 or claim 3, wherein said setting module is a BIOS.
    5. An arrangement as claimed in any of claims 2 to 4, wherein said core logic chip is a north bridge chip.
    6. An arrangement as claimed in any of claims 2 to 4, wherein said core logic chip is a chip integrating a north bridge and a south bridge.
    7. An arrangement as claimed in any Preceding claim, wherein said conversion interface controller is a hard disk interfacetomemory interface controller.
    8. An arrangement as claimed in any of claims 2 to 7, further comprising a power source connected to said main memory module.
    9. An arrangement as claimed in claim 8, wherein said power source is a backup power source in said computer system or a battery.
    10. A method of simulating a hard disk in a computer, the method comprising converting hard disk read/write signals to memory read/write signals and sending said memory read/write signals to a hard disk area into which a main memory of the computer is partitioned 11. A method as claimed in claim io, further comprising the steps of: Partitioning a main memory module which includes at least one said main memory in said computer system into a memory area and said hard disk area; providing a core logic chip having a memory controller for controlling data access of said memory area and a conversion interface controller for controlling data access of said hard disk area; using said core logic chip to receive read/write signals sent to said main memory module from said computer system and determine whether said read/write signals are memory read/write signals or hard disk read/write signals; sending said read/write signals to said memory controller if said read/write signals are memory read/write signals; and sending said read/write signals to said conversion interface controller if said read/write signals are hard disk read/write signals.
    12. A method as claimed in claim 11, wherein a BIOS of said computer system is used to partition said main memory module in said step of partitioning said main memory module.
    13. A method as claimed in claim 11 or claim 12, wherein said core logic chip is a north bridge chip.
    14. A method as claimed in claim 11 or claim 12, wherein said core logic chip is a chip integrating a north bridge and south bridge.
    15. A method as claimed in any of claims 11 to 14, wherein said conversion interface controller is a hard disk interface-to-memory interface controller.
    16. A method as claimed in any of claims 11 to 15, further comprising a step of providing a power source for said main memory module.
    17. A method as claimed in claim 16, wherein said power source is a backup power source in said computer system or a battery.
    18. A computer comprising an arrangement as claimed in any of claims 1 to 9, the computer being arranged to store setting information of said hard disk area and to retrieve said information to partition said memory on rebooting.
    19. A virtual hard disk arrangement substantially as described hereinabove with reference to Figure 1 or Figure 2 in conjunction with Figure 3 of the accompanying drawings.
GB0519078A 2005-09-19 2005-09-19 Device and method for simulating a hard disk Expired - Fee Related GB2423166B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020129204A1 (en) * 2001-03-06 2002-09-12 Lance Leighnor Hypercache RAM based disk emulation and method
US20040210716A1 (en) * 2003-04-21 2004-10-21 Aaeon Technology Inc. Apparatus and method for simulating virtual floppy disk and virtual hard disk

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020129204A1 (en) * 2001-03-06 2002-09-12 Lance Leighnor Hypercache RAM based disk emulation and method
US20040210716A1 (en) * 2003-04-21 2004-10-21 Aaeon Technology Inc. Apparatus and method for simulating virtual floppy disk and virtual hard disk

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GB0519078D0 (en) 2005-10-26

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Effective date: 20220919