GB2420421A - Method and apparatus for an embedded time domain reflectometry test - Google Patents

Method and apparatus for an embedded time domain reflectometry test Download PDF

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Publication number
GB2420421A
GB2420421A GB0508079A GB0508079A GB2420421A GB 2420421 A GB2420421 A GB 2420421A GB 0508079 A GB0508079 A GB 0508079A GB 0508079 A GB0508079 A GB 0508079A GB 2420421 A GB2420421 A GB 2420421A
Authority
GB
United Kingdom
Prior art keywords
recited
test
pad
data
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0508079A
Other languages
English (en)
Other versions
GB0508079D0 (en
Inventor
David L Linam
Jeffrey R Rearick
Guy Harlan Humphrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of GB0508079D0 publication Critical patent/GB0508079D0/en
Publication of GB2420421A publication Critical patent/GB2420421A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
GB0508079A 2004-11-23 2005-04-21 Method and apparatus for an embedded time domain reflectometry test Withdrawn GB2420421A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/996,113 US7640468B2 (en) 2004-11-23 2004-11-23 Method and apparatus for an embedded time domain reflectometry test

Publications (2)

Publication Number Publication Date
GB0508079D0 GB0508079D0 (en) 2005-06-01
GB2420421A true GB2420421A (en) 2006-05-24

Family

ID=34654497

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0508079A Withdrawn GB2420421A (en) 2004-11-23 2005-04-21 Method and apparatus for an embedded time domain reflectometry test

Country Status (3)

Country Link
US (1) US7640468B2 (https=)
JP (1) JP2006145527A (https=)
GB (1) GB2420421A (https=)

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US7250784B2 (en) 2005-06-29 2007-07-31 Marvell International Ltd. Integrated systems testing
KR100692529B1 (ko) * 2005-07-01 2007-03-09 삼성전자주식회사 최적화된 딜레이 타임 결정 방법, 장치 및 최적화된 딜레이타임 결정 프로그램이 기록된 컴퓨터로 판독 가능한기록매체
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US8024631B1 (en) * 2006-11-07 2011-09-20 Marvell International Ltd. Scan testing system and method
US8117460B2 (en) 2007-02-14 2012-02-14 Intel Corporation Time-domain reflectometry used to provide biometric authentication
DE102007037377B4 (de) 2007-08-08 2018-08-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Detektion von durch Unterbrechungen charakterisierbare Fehlstellen in Leitbahnnetzwerken
CN102165328A (zh) * 2008-09-26 2011-08-24 Nxp股份有限公司 用于测试部分地组装的多管芯器件的方法、集成电路管芯和多管芯器件
US9043662B2 (en) * 2009-03-30 2015-05-26 Cadence Design Systems, Inc. Double data rate memory physical interface high speed testing using self checking loopback
WO2010140344A1 (ja) * 2009-06-03 2010-12-09 株式会社アドバンテスト 試験装置
US8489947B2 (en) * 2010-02-15 2013-07-16 Mentor Graphics Corporation Circuit and method for simultaneously measuring multiple changes in delay
JP2012189396A (ja) * 2011-03-09 2012-10-04 Mitsubishi Electric Corp Ｉｃチップ、半導体部品、検査用プローブ、ハンディマルチテスター、及び通信装置
US9640280B1 (en) * 2015-11-02 2017-05-02 Cadence Design Systems, Inc. Power domain aware insertion methods and designs for testing and repairing memory
US10666540B2 (en) 2017-07-17 2020-05-26 International Business Machines Corporation Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
US10564219B2 (en) * 2017-07-27 2020-02-18 Teradyne, Inc. Time-aligning communication channels
JP7404646B2 (ja) * 2019-04-23 2023-12-26 ブラザー工業株式会社 入出力基板及び工作機械
US10890623B1 (en) 2019-09-04 2021-01-12 International Business Machines Corporation Power saving scannable latch output driver
US10897239B1 (en) 2019-09-06 2021-01-19 International Business Machines Corporation Granular variable impedance tuning
DE102023205733B4 (de) * 2023-06-20 2025-05-22 Infineon Technologies Ag Testsignalschaltung zum testen einer hochfrequenzempfängerschaltung, ein halbleiterchip und ein system, umfassend die testsignalschaltung

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576921A1 (de) * 1992-06-30 1994-01-05 Siemens Aktiengesellschaft Elektronischer Baustein mit einer taktgesteuerten Schiebregisterprüfarchitektur (Boundary-Scan)
US20020095633A1 (en) * 2000-10-05 2002-07-18 Ulf Pillkahn Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board
US6617869B1 (en) * 1999-08-12 2003-09-09 Siemens Aktiengesellschaft Electrical circuit with a testing device for testing the quality of electronic connections in the electrical circuit
US20030208734A1 (en) * 2002-05-01 2003-11-06 Coelho Jefferson Athayde Time domain measurement systems and methods
US20040049721A1 (en) * 2002-09-09 2004-03-11 Kevin Laake Method and apparatus for improving testability of I/O driver/receivers
US20040153276A1 (en) * 2001-08-22 2004-08-05 Combs Michael L. Method and apparatus for reduced pin count package connection verification

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Publication number Priority date Publication date Assignee Title
US5254942A (en) * 1991-04-25 1993-10-19 Daniel D'Souza Single chip IC tester architecture
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US6020757A (en) * 1998-03-24 2000-02-01 Xilinx, Inc. Slew rate selection circuit for a programmable device
US6266793B1 (en) * 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
US6397361B1 (en) * 1999-04-02 2002-05-28 International Business Machines Corporation Reduced-pin integrated circuit I/O test
US6477674B1 (en) * 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
US6714021B2 (en) * 2001-01-11 2004-03-30 Sun Microsystems, Inc. Integrated time domain reflectometry (TDR) tester
US6862546B2 (en) * 2002-02-22 2005-03-01 Intel Corporation Integrated adjustable short-haul/long-haul time domain reflectometry
JP3798713B2 (ja) * 2002-03-11 2006-07-19 株式会社東芝 半導体集積回路装置及びそのテスト方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576921A1 (de) * 1992-06-30 1994-01-05 Siemens Aktiengesellschaft Elektronischer Baustein mit einer taktgesteuerten Schiebregisterprüfarchitektur (Boundary-Scan)
US6617869B1 (en) * 1999-08-12 2003-09-09 Siemens Aktiengesellschaft Electrical circuit with a testing device for testing the quality of electronic connections in the electrical circuit
US20020095633A1 (en) * 2000-10-05 2002-07-18 Ulf Pillkahn Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board
US20040153276A1 (en) * 2001-08-22 2004-08-05 Combs Michael L. Method and apparatus for reduced pin count package connection verification
US20030208734A1 (en) * 2002-05-01 2003-11-06 Coelho Jefferson Athayde Time domain measurement systems and methods
US20040049721A1 (en) * 2002-09-09 2004-03-11 Kevin Laake Method and apparatus for improving testability of I/O driver/receivers

Also Published As

Publication number Publication date
JP2006145527A (ja) 2006-06-08
US20060123305A1 (en) 2006-06-08
US7640468B2 (en) 2009-12-29
GB0508079D0 (en) 2005-06-01

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Legal Events

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WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)