GB2418272A

GB2418272A - Processor arrangement having a stack memeory

Info

Publication number: GB2418272A
Application number: GB0420686A
Authority: GB
Inventors: Graham Butler
Original assignee: Marconi Communications Ltd; Marconi Co Ltd
Current assignee: Marconi Communications Ltd; BAE Systems Electronics Ltd
Priority date: 2004-09-17
Filing date: 2004-09-17
Publication date: 2006-03-22
Also published as: GB0420686D0; WO2006029997A1

Abstract

A processor 10 including a control unit 12, a program ROM 14 in communication with the control unit 12 for loading program instructions, and a stack memory 22 for storing data during execution of a program, wherein the stack memory 22 is adapted to handle data on a first in last out basis. Such a stack memory 22 can be used as a primary data storage mechanism in the processor 10 and can be used to replace the internal registers and conventional RAM of the prior processor.

Description

24 1 8272 Processor Arrangement The present invention relates to a

processor arrangement and in particular to a processor arrangement having a stack memory. s

A typical processor architecture uses a combination of internal registers and conventional Random Access Memory (RAM) to provide a working storage for data.

The data can be written to and read from such storage during the execution of a program as required. Typically the RAM is used as a primary working storage for data so that the 0 data can be loaded onto the RAM and freely accessed. Such free access to the data requires a complex addressing system for effective location and retrieval of the data.

Several problems are associated with the prior processor arrangement. Use of such a complex addressing system adds to the complexity of operation of the processor and inherently limits the minimum size of the operating overhead of the processor. This in turn limits the overall efficiency and speed of operation of the processor. Furthermore due to the inherent architecture of the processor a relatively complex programming language is required which is relatively intolerant to errors and is complex to learn.

20What is required is a processor arrangement having a simplified architecture and which requires a simplified programming language.

According to the invention there is provided a processor arrangement including a processing unit for co-ordinating timing and data flow activities, a program memory in communication with the processing unit for storing program instructions, and a data memory in communication with the processing unit for storing data during execution of a program, characterised in that the data memory is arranged to handle data on a first in last out basis.

Such a data memory can be used as a primary working storage for data in the processor and can be used to replace the internal registers and conventional RAM of the prior processor. In this specification a data memory is defined as a data storage and retrieval system whereby information is handled on a first in last out basis such that the 0 data that was last written to the data memory is the first to be read from the data memory. In contrast, in the prior processor data in the conventional RAM can be freely accessed. A processor according to the invention has the advantage that the data memory requires less logic and less complex programming than the prior processor since the complex addressing system for data is reduced. Accordingly fewer instructions are required for operation of the processor which permits faster cycle times and hence a greater throughput of data can be achieved. A processor so arranged has a simplified architecture and is relatively more compact than the prior processor which is particularly advantageous when printed circuit board space is limited. A further consequence of such simplified architecture is that power consumption requirements of the processor are kept to a minimum.

In a preferred embodiment the processor arrangement includes an incrementing means and a counting means for reading and writing data to the data memory.

The data memory may be provided in a single-port random access memory, the single port being adapted for reading and writing data to the data memory.

In a preferred embodiment a plurality of data memories are provided in communication with the processing unit. Use of more than one data memory permits multi-tasking to be performed by the processor since a plurality of different execution tasks can be performed simultaneously. Using more than one data memory also enables interrupts to be handled more efficiently.

lo In a preferred embodiment the plurality of data memories are provided in at least one dual-port random access memory, each random access memory having a first port for writing data to the memory, and a second port for reading data from the memory.

Using a dual-port random access memory permits data to be handled with less clock cycles than using a single-port random access memory.

Preferably each data memory is provided with a respective counting means.

Preferably a particular data memory is selected by a select signal which is input to one of the first port and the second port, in use, and in a preferred embodiment the select signal enables a write address input and a read address input of the dual-port RAM.

Preferably data is written to a respective data memory when a single clock pulse is issued, in use.

Preferably data is read from a respective data memory when a single clock pulse is issued, in use.

Advantageously data is written lo the respective data memory and read from the respective data memory in a single clock pulse, in use.

Optionally the processor arrangement further includes an arithmetic logic unit in communication with the processing unit. Such an arithmetic logic unit permits 0 mathematic or logical operations to be performed if required.

Optionally the processor arrangement further includes an input/output control in communication with the processing unit. Such an input/output control permits data transfer to or from external hardware if required.

Preferably a respective data memory is arranged to communicate with the processing unit in parallel with the input/output control. This permits data to be written directly to the input/output control from a particular data memory in one clock pulse whereby the processing unit is bypassed.

In a preferred embodiment the processor arrangement further including a further data memory in communication with the program memory such that when the processing unit performs one of calling a program instruction and issuing an interrupt, the current program location is stored by the further data memory, wherein the further s data memory is arranged to handle data on a first in last out basis. Such an arrangement permits the current program to be quickly restored at a later time when required.

Preferably the program memory is a read only memory.

Preferably the processor arrangement is adapted to use 16-bit arithmetic.

In one embodiment the processor arrangement is implemented in a field programmable gate array.

In another embodiment the processor arrangement is implemented in an application specific integrated circuit.

Optionally the processor arrangement has a device adapted to perform one of l s detection and prevention of an overflow of the up/down counter.

The device may also be adapted to perform one of detection and prevention of an underflow of the up/down counter.

Other features of the invention will be apparent from the following description of a preferred embodiment shown by way of example only in the accompanying drawings, in which; Figure 1 is a schematic diagram of the architecture of a processor arrangement according to the present invention.

Figure 2 is a schematic diagram illustrating the operation of a stack memory of the processor arrangement of Figure 1.

s - Figure 3 is a schematic representation of a single bank.

Figure 4 is a schematic representation showing four banks.

Referring to Figure 1 there is shown a schematic diagram of the architecture of a processor arrangement according to the present invention, generally designated 10. The 0 processor 10 can be implemented in the form of a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) as required. In Figure 1 the processor 10 includes a control unit 12, or processing unit, which co-ordinates all timing and data flow activities of the processor 10. The control unit 12 communicates with a program Read Only Memory (ROM) 14 to store program instructions as required. Program instructions are obtained one after another from the program ROM 14 under the control of the control unit 12. When the control unit 12 calls program instructions or issues an interrupt, the current program location is adapted to be stored by a program stack 16. The program stack 16 is configured as described below. The program stack 16 is in communication with the ROM 14 and stores the address of the current program to permit the current program to be restored at a later time when required.

Some program instructions may require mathematical or logical operations to be performed. Such operations are performed by an Arithmetic Logic Unit (ALU) 18 which is in communication with the control unit 12. Other program instructions may require data transfer to or from external hardware (not shown). Such data transfer is handled via an input/output control 20 which is in communication with the control unit 12. s

Figure I also shows a stack memory 22 which is arranged to communicate with the control unit 12 in parallel with the input/output control 20. Such a parallel communication permits data to be written from the stack memory 22 directly to the input/output control 20 in one clock cycle thereby bypassing the control unit 12. The stack memory 22 stores data on which mathematic or logical operations are to be performed by the ALU 18. Such a stack memory 22 is configured as described below.

In Figure 1 connections between the components 12, 14, 16, 18, 20, 22 of the processor are shown in bold lines to indicate that each connection permits data to be transmitted which is 16 bits wide.

In this specification a stack memory is defined as a data storage and retrieval system whereby information is handled on a first in last out basis. That is data that is last input to the stack will be read first. The program stack 16 and the stack memory 22 are configured to operate in this manner. Only two operations can be performed on such a stack memory, namely a push operation and a pop operation. A push operation places data on the top of the stack memory and increments a memory access pointer. A pop operation removes a data item from the top of the stack memory and decrements the memory access pointer. The detailed operation of the stack memory 22 and how the memory access pointer is incremented and decremented are discussed below with reference to Figure 2.

In Figure 2 the stack memory 22 comprises a dual-port RAM 24, an incrementer s 26 and an up/down counter 28. The dual-port RAM 24 and the up/down counter 28 are connected to a common clock but these details are well known to the skilled person and have been omitted from Figure 2 to simplify the diagram. The incrementer 26 is implemented in the form of logic gates and is therefore not clocked. The dual-port RAM 24 is partitioned into four banks, each bank capable of storing 256 data items with each 0 data item being 16-bits wide. In Figure 2 the dual-port RAM 24 has a first port 25 labelled as [9..8] [7..0], and a second port 27 labelled as [9..8] [7..0]. Each of the first port 25 and the second port 27 are 10- bits wide. Two bits are used to point to a particular bank and the other 8-bits are used as the memory access pointer on that bank.

It will be appreciated that the dual-port RAM 24 could be partitioned into as many banks as required and that each bank has a respective up/down counter 28. Only one up/down counter 28 is shown in Figure 2 for simplicity. The up/down counter 28 contains the memory access pointer which has just been written to and the incrementer 26 generates the next available address in a given bank, i.e. the top of the stack. It will also be appreciated that whilst a plurality of stack memories have been described the processor 10 will work with a single stack memory.

In Figure 2 a push operation is performed in the following manner. The data to be pushed onto the dual-port RAM 24 is sent from the control unit 12 of Figure 1 and is input to the dual-port RAM 24 of Figure 2 at data input 30. The data input 30 is labelled as 1150] to indicate that the data input is 16 bits wide and is a bus containing signals labelled from 15 down to 0. When a single clock pulse is issued by the clock (not shown) a single push pulse is input at 32. The push pulse is also input to each of an increment input 34 of the up/down counter 28, and a write enable input 36 of the dual s port RAM 24. The up/down counter 28 outputs at 42 to the incrementer 26 which in turn outputs to a write address 46 of the dual-port RAM 24. The write address 46 is labelled as [7..0] to indicate that the data is 8 bits wide and is a bus containing signals labelled from 7 down to 0. The data at the data input 30 is then written to memory location N+l, where N is the current value of the up/down counter 28. At the same 0 time, the up/down counter 28 is incremented such that N becomes N + 1. Such a push operation takes just one clock cycle.

When a pop operation is performed the data being popped from the dualport RAM 24 is already available at a data output 38. The data output 38 is labelled as [15 0] to indicate that the data is 16 bits wide. When a single clock pulse is issued by the clock a single pop pulse is input to a decrement input 40 of the up/down counter 28.

The up/down counter 28 is then decremented such that N becomes N - 1. The up/down counter 28 then outputs at 42 to a read address input 44 of the dual-port RAM 24. The read address 44 is labelled as [7..0] to indicate that the data is 8 bits wide and is a bus containing signals labelled from 7 down to 0. The data at the data output 38 is then popped from the dual-port RAM 24. If the dual-port RAM 24 is implemented to enable synchronous read then the new data on the top of the dual-port RAM 24 will take two clock cycles to become available. One cycle decrements the up/down counter 28 and a second cycle is used for the dual-port RAM 24 to respond to its new address.

One of the four banks of the dual-port RAM 24 is selected by a bank select signal which is input at 48 from the control unit 12. The bank select signal enables a write address input 50 and a read address input 52 which are each labelled as 19..8]. The label [9..8] indicates that there are two bank addressing bits which relate to the bank number in the manner illustrated in the table below. The addresses [9..8] and [7..0] in Figure 2 comprise the 10-bit address of the dual-port RAM 24. A plurality of banks permits the control unit 12 to switch between different execution tasks so that true multi-tasking can be performed. The address where data was last written to or read from 0 of a particular bank is remembered by its respective up/down counter so that data space is utilised efficiently. Since the banks are provided within the processor hardware there is no additional overhead associated with the core operation of the processor 10.

Bank select signal Bank number 01 2 3 l 4 If K is the number of bank addressing bits (shown in Figure 2 as 2), S is the number of stack addressing bits (shown in Figure 2 as 8) and W is the number of data bits (shown in Figure 2 as 16) then: Number of banks = 2K Data items per bank = 2S Total data items of RAM = 2(K + S) Total bits of RAM = (W) 2(K + S) = 16 ' 2(2 + 8) = 16384 The number 16384 corresponds to the number of bits of available block RAM in a standard FPGA or ASIC so that the available memory is used in the most efficient way. A consequence of using the block RAM in an efficient way is that the physical size of the stack memory is kept to a minimum which is important for reducing power lo consumption and for minimising crowding on printed circuit boards.

The stack memory 22 is programmed using its native assembler language which is very simple. Combinations of push and pop operations can be performed as required to perform arithmetic and logic operations. For example an increment operation is Is performed by firstly popping a data item off the stack, incrementing the data item by 1, and then pushing the incremented data item back onto the stack. A similar operation can be performed to decrement a data item. Two data items can be added together by firstly popping one data item off the stack, then popping a second data item off the stack, adding the two data items together, and then pushing the sum back onto the stack.

Similar operations can be performed for a subtract operation, a logical AND operation, a logical OR operation, or a logical-Exclusive-OR operation. The skilled person will know the requirements for programming the processor 10. The number of clock cycles required to perform different operations may be different depending on the number of push and pop operation in a particular operation.

In Figure 2 the stack memory 22 does not have a mechanism to detect or prevent an overflow or underflow of the up/down counter 28. Such a mechanism could be included although it is not essential to the operation of the stack memory 22. In the example of Figure 2 if there is an overflow or underflow of the up/down counter 28 it resets to zero.

Figure 3 shows a schematic representation of a single bank, generally designated 60. An input 62 to the bank 60 has an 8-bit address so that the bank 60 has 256 address lo locations labelled at 64. Each address location 64 can be filled with a 16-bit word. In Figure 3 the address location 255 contains the word 111101000011100 at the bottom of the bank 60, and the address location 254 contains the word 101000001111101 at the top of the bank 60. If a pop operation is performed on the bank 60 the word at address location 254 is popped from the bank 60 via the an output 66.

Figure 4 shows a schematic representation of four banks generally designated 70. The four banks 70 are contained in the dual-port RAM 24 of Figure 2. In Figure 4 the four banks are labelled 60, 72, 74 and 76. The bank labelled as 60 corresponds to the bank labelled 60 in Figure 3. In Figure 4 each of the banks 72, 74 76 are identical to the bank 60 and have a 10- bit address of which [9 8] select the address of the required bank, and bits labelled [7..0] select the address within that bank. Each bank 60, 72, 74, 76 has a common 8-bit address labelled at 78, and is individually selected by a 2-bit bank select address labelled at 80. 13,

The processor arrangement 10 of the invention finds particular application in a Dense Wavelength Division Multiplexing (DWDM) optical communications system.

When the processor 10 is embedded into an FPGA it can be used to control a communications laser which is part of a DWDM optical communications network. In use the processor 10 can be used for fine tuning the laser operating temperature, optical wavelength and output power. The processor 10 can also be used to control subsidiary tasks such as filtering and processing readings from analogue to digital converters, controlling receive and transmit optical attenuators, monitoring and reporting alarm conditions, and providing a serial communications interface for testing purposes.

In such a DWDM system using the processor arrangement 10 of Figure 2 the first bank is adapted to handle interrupts and the remaining three banks are used to handle tasks. Interrupts are typically of high priority that need to be done in real time.

Task one is for general communications, task two is to control the voltage of a laser, and task three is to control the laser wavelength. In this manner it can be seen that the processor 10 is particularly suited to handling tasks which are short term or subject to many interrupts. A processor of this kind is suited to being embedded into a FPGA for coprocessing of tasks.

The stack memory 22 can be used as a primary data storage mechanism inside a processor which has the advantage that the stack memory 22 requires minimal logic and programming. Accordingly fewer programming instructions are required which permits faster cycle times of the processor and hence greater throughput of data can be achieved. A further consequence is that the programming used by the stack memory is easier to learn and thereby is more error tolerant than a conventional assembly code.

Claims

Claims A processor arrangement including a processing unit for co-

ordinating timing s and data flow activities, a program memory in communication with the processing unit for storing program instructions, and a data memory in communication with the processing unit for storing data during execution of a program, characterized in that the data memory is arranged to handle data on a first in last out basis.

lo
2. A processor arrangement according to claim 1, and further including an incrementing means and a counting means for reading and writing data to the data memory.
3. A processor arrangement according to claim 1 or claim 2, wherein the data memory is provided in a single-port random access memory, the single port being adapted for reading and writing data to the data memory.
4. A processor arrangement according to claim 1, 2 or claim 3 and further provided with a plurality of data memories in communication with the processing unit.
5. A processor arrangement according to claim 4, wherein each data memory is provided with a respective counting means.
6. A processor arrangement according to claim 4 or claim 5, wherein the plurality of data memories are provided in at least one dual-port random access memory, each random access memory having a first port for writing data to the memory, and a second port for reading data from the memory. s
7. A processor arrangement according to claim 6, wherein a particular data memory is selected by a select signal which is input to one of the first port and the second port, in use.

lo
8. A processor arrangement according to claim 7, wherein the select signal enables a write address input and a read address input of the dualport random access memory.
9. A processor arrangement according to any preceding claim, wherein data is written to a respective data memory when a single clock pulse is issued, in use.
10. A processor arrangement according to any of claims 1 - 8, wherein data is read from a respective data memory when a single clock pulse is issued, in use.
11. A processor arrangement according to claim 9 or claim 10, wherein data is written to the respective data memory and read from the respective data memory in a single clock pulse, in use.
12. A processor arrangement according to any preceding claim and further including an arithmetic logic unit in communication with the processing unit.
13. A processor arrangement according to any preceding claim and further including an input/output control in communication with the processing unit.
14. A processor arrangement according to claim 13, wherein a respective data memory is arranged to communicate with the processing unit in parallel with the input/output control.
15. A processor arrangement according to any preceding claim, wherein a further lo data memory is provided in communication with the program memory such that when the processing unit performs one of calling a program instruction and issuing an interrupt, the current program location is stored by the further data memory, the further data memory being arranged to handle data on a first in last out basis.
16. A processor arrangement according to any preceding claim, wherein the program memory is a read only memory.
17. A processor arrangement according to any preceding claim, wherein the processor arrangement is adapted to use 16-bit arithmetic.
18. A processor arrangement according to any preceding claim, wherein the processor arrangement is implemented in a field programmable gate array.
19. A processor arrangement according to any of claims 1 - 17' wherein the processor arrangement is implemented in an application specific integrated circuit.
20. A processor arrangement as substantially described herein with reference to s Figures I - 4 of the accompanying drawings.