GB0420686D0 - Processor arrangement - Google Patents

Processor arrangement

Info

Publication number
GB0420686D0
GB0420686D0 GB0420686A GB0420686A GB0420686D0 GB 0420686 D0 GB0420686 D0 GB 0420686D0 GB 0420686 A GB0420686 A GB 0420686A GB 0420686 A GB0420686 A GB 0420686A GB 0420686 D0 GB0420686 D0 GB 0420686D0
Authority
GB
United Kingdom
Prior art keywords
processor arrangement
processor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0420686A
Other versions
GB2418272A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Co Ltd filed Critical Marconi Co Ltd
Priority to GB0420686A priority Critical patent/GB2418272A/en
Publication of GB0420686D0 publication Critical patent/GB0420686D0/en
Priority to PCT/EP2005/054518 priority patent/WO2006029997A1/en
Publication of GB2418272A publication Critical patent/GB2418272A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
GB0420686A 2004-09-17 2004-09-17 Processor arrangement having a stack memeory Withdrawn GB2418272A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0420686A GB2418272A (en) 2004-09-17 2004-09-17 Processor arrangement having a stack memeory
PCT/EP2005/054518 WO2006029997A1 (en) 2004-09-17 2005-09-12 Processor arrangement with a first in last out data memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0420686A GB2418272A (en) 2004-09-17 2004-09-17 Processor arrangement having a stack memeory

Publications (2)

Publication Number Publication Date
GB0420686D0 true GB0420686D0 (en) 2004-10-20
GB2418272A GB2418272A (en) 2006-03-22

Family

ID=33306741

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0420686A Withdrawn GB2418272A (en) 2004-09-17 2004-09-17 Processor arrangement having a stack memeory

Country Status (2)

Country Link
GB (1) GB2418272A (en)
WO (1) WO2006029997A1 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0167241B1 (en) * 1984-05-08 1993-12-15 Advanced Micro Devices, Inc. Microprogramme sequence controller
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US6088786A (en) * 1997-06-27 2000-07-11 Sun Microsystems, Inc. Method and system for coupling a stack based processor to register based functional unit
WO1999009469A1 (en) * 1997-08-18 1999-02-25 Koninklijke Philips Electronics N.V. Stack oriented data processing device
US6256725B1 (en) * 1998-12-04 2001-07-03 Agere Systems Guardian Corp. Shared datapath processor utilizing stack-based and register-based storage spaces
US6742112B1 (en) * 1999-12-29 2004-05-25 Intel Corporation Lookahead register value tracking
EP1387247A3 (en) * 2002-07-31 2007-12-12 Texas Instruments Inc. System and method to automatically stack and unstack java local variables

Also Published As

Publication number Publication date
GB2418272A (en) 2006-03-22
WO2006029997A1 (en) 2006-03-23

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)