GB2418035A

GB2418035A - Power factor correction for an AC-DC power supply

Info

Publication number: GB2418035A
Application number: GB0420345A
Authority: GB
Inventors: Roger John Kemp
Original assignee: IO Ltd
Current assignee: IO Ltd
Priority date: 2004-09-13
Filing date: 2004-09-13
Publication date: 2006-03-15
Anticipated expiration: 2024-09-13
Also published as: GB2418035B; GB0420345D0

Abstract

A controller (fig 3, 15) measures and stores input voltage, output voltage, output current and the supply cycle period over a predetermined time span. These values are used to determine controller characteristics which are applied to control the output (fig 3, S) of the power factor correction circuit over a future time span. The circuit may include a rectifier (fig 3 BR1) one or two inductor(s) (fig 3, L) controlled by switch(es) (fig 3, 20) in boost or fly-back mode. In the case of two switched inductors these are arranged in parallel with a common output and may be operated, one at a time in a pulsed fashion. The predetermined time span may be a half-cycle of the supply (fig 3, 12) and the input voltage may be sampled four or more times over that period by means such as an analogue to digital converter. A timer may be used to measure the supply cycle period. The future time span may be one full cycle ahead of the time span during which the stored values are measured.

Description

24 1 8035 Method and apparatus for power conversion The present invention

relates to a method and apparatus for power conversion. It is particularly, but not exclusively concerned with methods and apparatuses for power conversion which provide high power factors and low supply line emissions. Preferably the methods and apparatuses can operate continuously over a wide range of supply frequencies.

Power factor correction (PFC) is now a requirement for AC-DC power supplies in all applications. The requirements are regulated through various international commercial, aircraft and military standards. To meet these requirements at typical line frequencies of 50 and Hz, it is possible to use either passive or active PFC. Passive PFC designs use large inductive components and these can become unrealistically bulky and cumbersome for applications above about 100 W. Active PFC based on voltage boost through a switched inductor has thus become popular and has led to the development of commercial control devices such as that described in US 6 275 397B. These devices are typified by acting as single function PFC circuits, characterized by large high frequency deviations in the supply current.

Such high frequency current changes result in electro magnetic interference (EMI) which must then be filtered to meet the Electromagnetic Compatibility (EMC) standards.

Figure 1 shows a block diagram of a common form of PFC showing the associated functional blocks. AC supply input 110 is first rectified by bridge rectifier BR1 to produce a haversine voltage input. This input then passes through a switched inductor circuit comprising inductor L1, controller 115 which provides an analogue control loop, switch 120, diode D1 and capacitor C1 to produce a corrected DC output 130.

The controller 115 typically works by continuous monitoring of the input voltage as a reference for the controller current. Based on the instantaneous value of the input voltage A, multiplied by a fixed reference conditioned by the output voltage B. a value is set for the switch current limit. The switch 120 is turned on by output S. and the current increases until the current sensor input C as detected by current sensor 125 reaches the instantaneous set value. The switch 120 is then turned off and the current decreases to some other value, normally zero, at which point the switch is turned on again and the process repeats.

Such controller operation results in an output current of the form shown in Figure 2.

Due to the use of a continuous analogue feedback and monitoring loop, the frequency response of such a controller must be tailored so that selfgenerated noise can be filtered out. For example existing devices, such as that described above with reference to Figure 1, generally use instantaneous monitoring of the output voltage. However, due to the constant switching, this voltage will contain many transients which, if the frequency bandwidth is not controlled will lead to noise at the monitoring point, which could result in erroneous output from the controller or even unstable feedback.

Even high quality PFC circuits, such as the VI-HAM made by VICOR, are specifically "tuned" to a particular frequency (normally 50-60 Hz (47-63 Hz in the case of the VI-HAM) and are stated to not function correctly at higher frequencies).

Thus the existing methods are limited to a narrow input frequency range in order to maintain a reliable control input.

The existing conversion method also causes large fluctuations in the supply line current, as shown in Figure 2, which produces large amounts of EMI. This can be reduced by placing radio-frequency (RF) filters on the supply side but, for most applications and particularly for aircraft implementations, such filters are heavy and bulky and therefore undesirable.

The present invention seeks to address the above problems and provide a method and apparatus for power factor correction that reduces the supply line current fluctuations and thus reduces the EMI created by the correction.

Accordingly a first aspect of the present invention provides a method of controlling a power factor correction circuit, the method including the steps of: measuring and storing values of the input voltage, output voltage and output current of the circuit over a predetermined time span; measuring and storing the value of the supply cycle period over the same time span; determining controller characteristics for a future time span based on the stored values; applying the determined controller characteristics to control the output of the power factor correction circuit during the future time span.

By using values from an earlier time span to control the circuit in a successive time span, more noise free control of the output of the circuit may be achieved.

The output requirements of the circuit may thus be determined or predicted in advance and so control of the output tailored to those requirements rather than relying on instantaneous feedback from the output.

By removing the need for instantaneous DC output feedback, the need for bandwidth control may also be relaxed.

When the power factor correction circuit includes a switch-controlled inductor, the step of applying the determined controller characteristics may include operating said switch in a pulsed fashion.

When the power factor correction circuit includes two switch-controlled inductors arranged in parallel with a common output, the step of applying the determined controller characteristics may include operating both said switches in a pulsed fashion. Preferably the step of determining the controller characteristics determines said characteristics such that, apart from a starting condition, only one of said inductors is switched on at any time.

By providing inductors operating in parallel, each can deliver half the required current. This can reduce the electrical stress in the components, and may also reduce the noise in the input current due to the interleaving of the switching of the inductors.

By controlling the switch through a predetermined sequence, the switch may be operated at a high switching rate without the associated local noise affecting the control loop.

Preferably the step of determining the controller characteristics determines said characteristics such that the input current at any point in the future time span is within a bound, of at most 10% of the rated current, above or below the optimum instantaneous input current at that point. More preferably the input current is within a bound of at most 5%, or even 1%, of the rated current.

Preferably said predetermined time span is one half-cycle of the supply. This may give full details of the characteristics of the supply, whilst allowing the determined controller characteristics to be applied to control the output with little delay, thus reducing errors due to changes in the operating conditions.

The supply cycle period may be measured by measuring a fraction (e.g. a half) or a multiple of the cycle period.

The step of determining the controller characteristics may use either the period or a fraction or multiple of the period.

Preferably said input voltage is measured by sampling.

Sampling of the supply voltage may be performed at any number of different points, but measurement at a plurality of points allows for a better estimate of the average input voltage. Measuring at 4 points gives a theoretical estimation accuracy of the average of the supply voltage of 5% (i.e. the error between the theoretical value of an 4-interval measurement and a true average measurement, ignoring other factors such as measurement uncertainties). Measuring at 8 points gives a theoretical accuracy of about 1.5% whilst measuring at 16 points gives a theoretical accuracy of 0.35%.

For digital storage and binary arithmetic, the number of samples taken is preferably a power of two. It has been discovered that the choice of 8 measurement sub-intervals provides a good compromise between controller overhead (and thus cost) and measurement accuracy.

Thus the input voltage is preferably sampled at at least four points in said time span and more preferably at at least eight points in said time span. Sampling of the input voltage may substantially reduce or even eliminate noise in that measurement.

In one implementation, said future time span is one full cycle ahead of the time span in which the stored values are measured. This may allow any asymmetry in the supply cycle to be automatically accounted for as the values for that are measured in one half cycle and for which controller characteristics are calculated in a second half cycle are used in to control the circuit in a third half cycle.

Whilst increasing the delay between the time span in which the stored values are measured and the future time span may be generally undesirable, half-cycle or full cycle delay will generally be acceptable, and can be achieved using relatively low cost components. However, alternative implementations may implement the method of the present invention through trending, where variations in cycle to cycle measurements are taken into account to mitigate the effects of the delay.

A second aspect of the present invention provides a controller for a power factor correction circuit, the controller comprising: a first memory device for storing as stored values the input voltage, output voltage and output current of the circuit over a predetermined time spans a second memory device for storing as a further stored value the value of the supply cycle period over the same time span; a processor adapted to determine controller characteristics for a future time span based on the stored values in said first and second memory devices; a third memory device for storing said controller characteristics; and an output device for outputting a control signal containing the determined controller characteristics to control the output of the power factor correction circuit during the future time span.

The first, second and third memory devices of this aspect may in fact be combined in a single memory device, for example in a single RAM device, or in any combination in two memory devices. Specific areas of the single memory device may be allocated to serve as the memory devices described above. All the memory devices may be provided on the same chip or integrated circuit as the processor, or provided separately.

The controller may further comprise a timer device for measuring said period and/or means for measuring the input voltage. Preferably the means for measuring the input voltage samples the input voltage, preferably at at least four points in said time span and more preferably at at least eight point in said time span. Sampling of the input voltage may substantially reduce or even eliminate noise in that measurement.

Preferably the controller is a digital controller, which may be implemented in a specific integrated circuit. The controller may further comprise an analogue to digital converter for converting analogue measurements to generate said stored values.

Preferably the processor determines said controller characteristics such that the input current at any point in the future time span is within a bound, of at most 10% of the rated current, above or below the optimum instantaneous input current at that point. More preferably the input current is within a bound of at most 5%, or even 1%, of the rated current.

In one implementation of this aspect, said future time span is one full cycle ahead of the time span in which the stored values are measured.

The power factor correction circuit may include a switch- controlled inductor and the control signal may then be a sequence of binary control values for operating said switch in a pulsed fashion. A further control signal may be provided so that the switch is actively driven between "on" and "off" states r thus reducing transient times.

In a development of this aspect, the power factor correction circuit includes two switch-controlled inductors arranged in parallel with a common output, and the controller outputs two control signals, each of which are a sequence of binary control values for operating a respective one of said switches.

Another aspect of the present invention provides a power factor correction circuit having: a supply input; an output an inductor connected between the supply input and the output; a switch operative to control the current flowing through said inductor; and a controller controlling the operation of said switch, the controller being a controller according to the previous aspect.

A further aspect of the present invention provides a power factor correction circuit having: a supply input; an output a pair of inductors connected in parallel between the supply input and the output; a pair of switches each operative to control the current flowing through a respective one of said inductors; and a controller controlling the operation of said switches, the controller being a controller according to the development of the second aspect above.

The controllers of the above two aspects may have any combination of the preferred and/or optional features of the previous aspect.

The inductor(s) may be operating in boost or fly-back mode. The circuit may include a full-wave rectifier between said supply input and said inductor.

Load fluctuations are typically dealt with by having an output storage component capable of delivering for at least one half cycle. By monitoring the output load current, the present invention allows the controller to take note of any load fluctuation before the output voltage changes.

Another aspect of the present invention provides a power supply having a power factor correction circuit according to the previous aspect.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a circuit block diagram of a power factor correction circuit of the prior art and has already been described) Figure 2 is a graph showing the current output of the power factor correction circuit of a prior art circuit and has already been described; Figure 3 is a circuit block diagram of an embodiment of the present invention; Figure 4 is a schematic diagram of a controller of an embodiment of the present invention; Figure 5 is a flow chart showing a method of calculating the switch values used in embodiments of the invention; Figure 6 is a schematic diagram of the switch controller used in embodiments of the present invention; Figure 7 is a graph showing the current output of the power factor correction circuit of an embodiment of the present invention; and Figure 8 shows the relative timing of an arrangement of switch driver circuits as used in the second embodiment of the present invention.

An embodiment of a power factor correction circuit of the present invention (and incorporating an embodiment of a controller of the present invention and) is shown in Figure 3. An embodiment of a method of the present invention will also be described in relation to the power factor correction circuit of Figure 3.

Many elements of the circuit are common to the power factor correction circuit of the prior art discussed above.

The circuit uses a series inductor L1 operating in boost or fly-back mode. The circuit is a switched mode supply with switch 20 and diode D1 providing the two switches.

A capacitor C1 is provided as the energy storage buffer for the output, and maintains the output voltage through fluctuations in the inductor current.

The principles of the present invention can be applied equally to other circuit configurations, and such circuits are also embodiments of the present invention.

For example a double wound inductor may be operated in a "push-pull" mode, an auxiliary winding may also be used for the controller power supply. Buck mode configurations are possible, but do not give control at low input voltages.

Parallel operation of synchronized, sequentially switched circuits is made possible by the precise switch timing and the summed input current can thus have lower ripple.

A further alternative would be the control of coupled inductors for further input ripple protection (see, for example, S. Cuk and Z. Zhang, "Coupled Inductor Analysis and Design", PESC Conf. Proc. 1986).

In the present embodiment, digital controller 15 comprises a microcomputer unit (MCU) 42, a logic block 44 and a switch driver 46 as shown in Figure 4.

With a more powerful MCU having dual memory interfaces, some elements of the controller such as the data routing could be embedded in the MCU.

The MCU 42 takes measurements of the supply voltage B. the output voltage D and the output current E (as measured by current sensor 25) through an analogue to digital converter (ADC) incorporated in the MCU 42.

These values are stored by the MCU 42 as described below.

During each half cycle of the input supply, the supply voltage (B) is measured at 8 points which are taken at equal sub-intervals of the half cycle period as previously measured. These measurements are summed and stored by the MCU 42. If voltage measurements are taken at equal intervals across a half cycle then the resulting sum of these measurements is approximately proportional to the true average with no assumption about the input waveform.

Sampling at various points reduces the effect of any noise in the circuit, and so no noise effects are fed back to the controller.

The period of the supply half cycle in which the voltage measurements are taken, is also measured and stored as a digital value by the MCU 42. A voltage comparator 29 is used as a zero crossing detector for controller input A and also provides an over-voltage detector (input F). In addition to providing half cycle timing points, the comparator also provides a control input for a period of some tens of micro-seconds either side of the zero crossing point, the zero crossing time (ZX).

During this zero crossing time, the controller outputs S/S1 are inactive as the input current is at or near zero, resulting in no local noise. The output voltage and current measurements are advantageously made and stored digitally at this point.

This allows the controller 15 to synchronize to the input cycle at zero phase. The MCU 42 also uses this period to initialize the controls for the next half cycle.

Operating conditions or values for the switch controller can then be calculated, based on the stored measurements.

These values are stored in one of two blocks of a memory device 48 (shown in Figure 4). In the present embodiment these are random access memory devices 48A and 48B, but could equally be serial access memory or any other form of writable memory, and could be located internal to or external to the MCU 42. These values can then be provided as switch control values to the switch controller during a subsequent half cycle.

In the present embodiment, the measurements are made during a first half cycle, switch values are calculated during a second half cycle and these values are used to control the switch during a third half cycle. This results in a delay of a full cycle between measurement and application of the results of the measurement, but has the benefit that any lack of symmetry in the supply waveform is automatically dealt with.

Calculation of the "on" and "off" timings for the switch 20 uses knowledge of the input voltage and period previously stored, the expected output voltage and a constant factor related to the value of the inductor L1.

In one embodiment of the present invention, the incremental algorithm used by the controller 15 to calculate the switch timings is as set out below.

The following symbols will be used in describing the algorithm: Va = Measured and averaged input voltage (from Controller input A).

VOut = Measured and averaged output voltage (from Controller input D).

lout = Measured and averaged output current (from Controller input E).

TO = Half sine period measured at input.

L = Inductance value of series inductor L1.

Vs = Instantaneous value of input voltage.

k = Correction factor for transfer efficiency and component tolerance.

fin = Adjusted average input current.

Is = Instantaneous value of input current (also the current through inductor L1).

For the following calculation steps it is assumed that the input current waveform is to be a true sine-wave and that the calculations are performed on a single half- wave.

Firstly the initial values for the half-wave calculations are set up: Va x In x k = VoUt X Iout I _ you' X Iout/ in - /Va Xk This value is then used to scale the instantaneous reference current (i.e. the optimum output current): Ir()=Inxsin(t) for O<mt< (note that in a strict construction there should be a further scaling factor to allow for the fact that the input values are AC averaged and the output values are DC. In the above it is assumed that this factor is included in the reference factor k).

Since the algorithm in question uses a constant time increment, the reference input current can also be expressed at N incremental fractions of the input half sine period: Tc=Nx where St is the time increment Ir (n) = IN x sin(n IN) The instantaneous voltage can be expressed similarly as: V,.(n)= bra xl.55xsin(nX/N) with explicit scaling of the peak voltage to account for Va being an approximation to the average voltage.

To calculate the synthesised input current, the charge and discharge characteristics of the inductor L1 are accumulated over the N increments of a half cycle. The synthesized current is constrained to remain within an arbitrary but small difference value from the reference current. In this example fit is fixed so N will vary with the frequency. Ideally N is kept as large as possible within the practical limitations imposed by, for example, the transition time of the switch 20. The difference value (or error bound "err") will for a similar reason be frequency dependent with an absolute minimum value resulting from the fixed time intervals.

The exact value of this error bound "err" may be determined on a case-bycase basis depending on the proposed use of the circuit and the standards to which the power supply has to conform. The error bound may be an absolute value for the particular method/controller/ circuit or may be a relative value such as a fraction of the peak rated current. Ideally the error bound is at most 10% of the peak rated current, more preferably at most 5% and may be chosen to be 1% or less of the peak rated current. An error bound of 10% represents a significant improvement in the ripple and thus the conducted noise effects.

The exact error bound may be chosen depending on the use to which the method or circuit is to be put and the standards to be satisfied. In circumstances where the reduction in ripple is not sufficient to satisfy the noise standards, it still works to significantly reduce the requirement for EMI filtering (compared to the equivalent 200% error bound of the prior art circuits discussed above, a 10% error bound will reduce the filter requirement by 20 times or 26 dB).

During each time increment the switch drive is either "on" or "off" - i.e. the switch is respectively either closed or open. L1 charges during the "on" increments and discharges during the "off" increments.

The charging voltage is the time varying input voltage, approximated to the incremental end value.

The discharging voltage is the time varying input voltage less the output voltage. The output voltage is controlled to be larger than the input voltage (excepting start-up conditions) and may be adjusted dependent on the input voltage peak value, or may be fixed (as in this

example).

The basic formula for the inductor current increment is: HI =Vx(/L) or for constant fit: Al = V x YI where Yl = (/L) . Thus for any arbitrary step, the inductor current is: Is(n)=V(n)xYl+Is(n-l) if the inductor is charging, or I(n)=(V(n)-VOu)xYl+I,(n-l) if the inductor is discharging.

Thus a process of generating the switch values from the stored data, as used in embodiments of the present invention, is illustrated in the flow chart of Figure 5.

At the beginning of any half sine period, the inductor current (i.e. Is(0) ) is assumed to be zero and the switch value dS is set to "1" or "on" for the first time increment (n=O) - step 201.

Then in a repeating loop, the increment n is increased by 1 (n++). After checking that the half cycle has not been completed (? n<N) - step 202, the process then calculates the inductor current for the current increment (Is(n)) - steps 204 and 205. This calculation will depend on whether the inductor is charging or discharging as described above and the status of the inductor is determined by the current switch value - step 203.

The final decision stage in both arms of the loop determines whether the switch value is to be changed or not. If the inductor is charging (dS = 1) , then the switch is opened (dS set = 0) - step 208 - if Is(n) is equal to or greater than the reference current at that increment Ir(n) plus a predetermined bound "err" - step 206. Conversely if the inductor is discharging (dS = 0), then the switch is closed (dS set = 1) - step 209 if Is(n) is less or equal to the reference current minus a predetermined bound "err" - step 207.

The sequence of switch values dS(n) generated by the above process is stored.

Thus for each successive time increment, the calculated value for the synthesised current is compared with the corresponding reference value and the next switch value is set according to this comparison.

Each switch value is thus represented by a single bit of stored data. For use with standard data storage devices, the switch values for each set of eight time increments are stored as octets.

To prevent end point oscillation, the switch algorithm may be enhanced to trap current values calculated as negative. To implement this, for all values of n after a negative calculated current, the switch values are set to "O" or "off".

The above process or algorithm may be further optimised to use comparatively low throughput embedded microcontrollers.

The "on" and "off" timings for switch 20 are chosen such that the output current is continuous and increments through many small fluctuations up to a calculated peak value and then returns to zero in a similar fashion as shown in Figure 7. The exact switching requirements to determine this behaviour are calculated for each half cycle by the controller using the previously stored values for the supply and output conditions. This allows small current fluctuations in the supply to be achieved and hence a reduction in conducted supply noise emissions.

Such a pattern of switching also substantially reduces or even eliminates the bandwidth limitations associated with the prior art feedback control systems. By measuring the input voltage "off line", and in particular when using a sampling or averaging method to measure the input voltage, the methods/controllers of the present invention are not concerned with any higher frequency fluctuations of this input.

During each half cycle the controller 15 can thus deliver to the DC output 30 an amount of energy based on the measurements of supply and output loading, such that the output voltage will be substantially at a predetermined value. This behaviour depends on the supply voltage and frequency fluctuations being relatively small, and the output load characteristics being relatively constant over the time scale of one cycle or one half cycle of the supply (i.e. the delay between measurement of the conditions and implementation of the determined controllercharacteristics), which is predominantly the case.

In the event that there is little or no change in the operating conditions measured by the controller 15, the controller could be arranged to re-use pre-existing stored switch values.

In instances when the supply voltage fluctuates suddenly (either causing a brown-out or an over-voltage condition), controller safeguards are provided.

Input over-voltage detection (controller input F) provides instantaneous disabling of the switch driver (e.g. through control of the switch sequencer 50 described below), as does switch over-current detection.

Input surge protection and long-term over-voltage are dealt with using additional devices which are chosen to suit the expected operating conditions.

The logic block 44 of the controller 15 of Figure 3 will be described in more detail with reference to Figure 4.

The principal functions provided by the logic block 44 are a switch sequencer 50 and a router of RAM data 52.

Switch control data is stored in the memory device 48 as a sequential bit pattern, with each bit representing an on or off state of the switch 20. A switch sequencer 50 is provided between the memory device 48 and switch driver 46 to buffer this data.

The benefits of using the switch sequencer 50 are that the sequencer can automatically clock the RAM bit stream without intervention from the MCU 42, thus reducing the loading on the MCU, and by monitoring the bit stream, the sequencer 50 can deliver a secondary output signal following each bit state transition from 1 to 0. This secondary output together with the buffered bit stream provides a differential, bi-polar drive for the switch 20, thus decreasing switch transition times. This effect is shown in Figure 5 where the sequenced bit stream is represented by signal A and the secondary output by signal B. Furthermore, the sequencer 50 can be cut off independently of the RAM bit stream and any other timings by various override signals. In particular these include during the zero crossing period ZX and when over-voltage or over-current is detected as described above. When cut off the sequencer 50 provides a fail safe off state for the switch driver 46.

The output of the switch driver 46 delivers a bi-polar signal with sufficient amplitude to rapidly activate and de-activate the switch 20. This aids efficiency by reducing the transient times of the switch 20.

The logic block 44 also provides a RAM data routing function. This allows the MCU 42 to access either of the two RAM blocks 48A and 48B, while the other RAM block can be read simultaneously by the switch sequencer 50.

A further potential function which can be performed by the logic block 44 is the cross routing of data for a second MCU 54. This allows processing overhead to be shared between two components. In such a mode of operation, one MCU may be used as the calculation engine while the other MCU carries out input measurement and output control. The data router 52 allows simultaneous access to the memory device 48 by either MCU. Such an arrangement allows lower performance, and thus lower cost, components to be used as the MCUs.

In another embodiment of the present invention, the power factor correction circuit has two parallel switched inductor circuits between the rectifier and the output, with each circuit outputting to a common storage capacitor at the output. The two circuits are controlled by a single controller having an MCU and an enhanced sequencing circuit.

The controller determines the switch control data so that each of the circuits delivers an approximation to a sinusoidal current at half the required level. The enhanced sequencer operates to ensure that only one of the driver circuits is on at any time (with the exception of the half cycle starting condition). Figure 8 shows the relative timing of such an arrangement of switch driver circuits.

This embodiment has the advantages that since each switch and driver circuit is working at half the total input/output, there is less electrical stress on the components, and that although the total current at the input and output are as in the previous embodiment, the incremental effects on the input current are reduced by interleaving of the switch operations thus further reducing the noise.

Claims

1. A method of controlling a power factor correction circuit, the method including the steps of: measuring and storing values of the input voltage, output voltage and output current of the circuit over a predetermined time span; measuring and storing the value of the supply cycle period over the same time span; determining controller characteristics for a future time span based on the stored values; applying the determined controller characteristics to control the output of the power factor correction circuit during the future time span.

2. A method according to claim 1 wherein the power factor correction circuit includes a switch-controlled inductor and the step of applying the determined controller characteristics includes operating said switch in a pulsed fashion.

3. A method according to claim 2 wherein the power factor correction circuit includes two switch-controlled inductors arranged in parallel with a common output, and the step of applying the determined controller characteristics includes operating both said switches in a pulsed fashion.

4. A method according to claim 3 wherein the step of determining the controller characteristics determines said characteristics such that, apart from a starting condition, only one of said inductors is switched on at any time.

5. A method according to any one of the preceding claims wherein the step of determining the controller characteristics determines said characteristics such that the input current at any point in the future time span is within a bound, of at most 10% of the rated current, above or below the optimum instantaneous input current at that point.

6. A method according to any one of the preceding claims wherein said predetermined time span is one half cycle of the supply.

7. A method according to any one of the preceding claims wherein said input voltage is measured by sampling.

8. A method according to claim 7 wherein said input voltage is sampled at at least four points in said time span.

9. A method according to claim 8 wherein said input voltage is sampled at at least eight points in said time span.

10. A method according to any one of the preceding claims wherein said future time span is one full cycle ahead of the time span in which the stored values are measured.

11. A controller for a power factor correction circuit, the controller comprising: a first memory device for storing as stored values the input voltage, output voltage and output current of the circuit over a predetermined time span; a second memory device for storing as a further stored value the value of the supply cycle period over the same time span; a processor adapted to determine controller characteristics for a future time span based on the stored values in said first and second memory devices) a third memory device for storing said controller characteristics; and an output device for outputting a control signal containing the determined controller characteristics to control the output of the power factor correction circuit during the future time span.

12. A controller according to claim 11 further i comprising a timer device for measuring said period.

13. A controller according to claim 11 or claim 12 further comprising means for measuring the input voltage.

14. A controller according to claim 13 wherein the means for measuring the input voltage samples the input voltage.

15. A controller according to claim 14 wherein the means for measuring the input voltage samples the input voltage at at least four points in said time span.

16. A controller according to any one of claims 11 to 15 which is a digital controller.

17. A controller according to claim 16 further comprising an analogue to digital converter for converting analogue measurements to generate said stored values.

18. A controller according to any one of claims 11 to 17 wherein the processor determines said controller characteristics such that the input current at any point in the future time span is within a bound, of at most 10% of the rated current, above or below the optimum instantaneous input current at that point.

19. A controller according to any one of claims 11 to 18 wherein said predetermined time span is one half-cycle of the supply.

20. A controller according to any one of claims 11 to 19 wherein said future time span is one full cycle ahead of the time span in which the stored values are measured.

21. A controller according to any one of claims 11 to 20 wherein the power factor correction circuit includes a switch-controlled inductor and the control signal is a sequence of binary control values for operating said switch in a pulsed fashion.

22. A controller according to any one of claims 11 to 20 wherein the power factor correction circuit includes two switch-controlled inductors arranged in parallel with a common output, and the controller outputs two control signals, each of which are a sequence of binary control values for operating a respective one of said switches.

23. A power factor correction circuit having: a supply input; an output an inductor connected between the supply input and the output; a switch operative to control the current flowing through said inductor; and a controller controlling the operation of said switch, the controller being a controller according to claim 21.

24. A power factor correction circuit having: a supply input) an output a pair of inductors connected in parallel between the supply input and the output; a pair of switches each operative to control the current flowing through a respective one of said inductors; and i a controller controlling the operation of said switches, the controller being a controller according to claim 22.

25. A power factor correction circuit according to claim 23 or claim 24 wherein the inductor is operating in boost or fly-back mode.

26. A power factor correction circuit according to any one of claims 23 to 25 further including a rectifier between said supply input and said inductor(s).

27. A power supply having a power factor correction circuit according to any one of claims 23 to 26.

28. A method for controlling a power factor correction circuit substantially as any one herein described with reference to Figures 3 to 8.

29. A controller for a power factor correction circuit substantially as any one herein described with reference to, or as illustrated in, Figures 3 to 8.

30. A power factor correction circuit substantially as any one herein described with reference to, or as illustrated in, Figures 3 to 8.