GB2415799A

GB2415799A - Independent processor resetting in a multiprocessor system

Info

Publication number: GB2415799A
Application number: GB0414679A
Authority: GB
Inventors: Andrew Wilkes
Original assignee: NEC Technologies UK Ltd
Current assignee: NEC Technologies UK Ltd
Priority date: 2004-06-30
Filing date: 2004-06-30
Publication date: 2006-01-04
Also published as: GB0414679D0

Abstract

A method for resetting a processor in a multiprocessor system comprises issuing a request reset signal from a first processor to an interrupt request input on at least one other processor. The request reset signal notifies the other processor or processors that the first processor has requested a reset. A reset signal is then applied to a reset input of the first processor. An acknowledgement could be sent back to the first processor before the reset is initiated. This method could be used in a mobile communications system where one processor could be an applications processor and a second processor could be a communications processor.

Description

Software reset in dual processor mobile phone This invention relates to a

system and method for controlling the software initiated reset of a multi processor electronic device, preferably a mobile communications device.

It is common for both the hardware and software on mobile telephones to be partitioned into more than one part, for example an applications part and a modem part.

The application part runs any user application such as a web browser, telephone index book, or camera software. The modem part controls the connection of the device with the radio network. In this case each part may have its own processor, for example an Applications CPU (ACPU) and a Communications CPU (CCPU). Each of these processors may encounter situations in which a reset of the processor is required in order to achieve stable operation of the system. For example, the applications CPU may be running a browser which is stuck in a software loop. A watchdog timer is then used to recover the central processing unit (CPU) from the software loop by providing a reset signal to the CPU upon expiry of the timer.

Additionally the communications CPU may encounter a problem when synchronizing the local oscillator to the base station which may cause it to freeze. Similarly, the expiry of a watchdog timer triggers a reset of the CPU.

Conventional systems provide a reset control line to overcome this problem, which is a common signal linked to all devices that may require a reset such as the ACPU or the CCPU. If any one of the devices requires a reset, then a signal is sent via the common signal, and all the devices will be reset. This means that the processor will be restarted from a known good state, such as one with the program counter at zero, for example. This is known as a system reset. Another form of reset is the software reset, which may be triggered by a software related event, such as the expiry of a watchdog timer caused by software stuck in a loop. In conventional systems, this also triggers a system reset so that all devices are reset even if only one of them requires it.

The problem with the conventional reset system in a dual-CPU mobile telephone is that the whole system is reset even when only one part has experienced a problem. This means that all software processes have to restart and the previous state of the mobile phone is then lost. For example a bug in a web browser running on the ACPU could cause the modem to disconnect from the radio network. This is annoying for the user and it is time consuming to have to re-establish a connection with the radio network.

Similarly, a problem in the modem could cause an application to be reset, possibly losing valuable data such as a captured camera images.

Independent resetting of partitions within a computer system is also known. US patent no. 5717942 describes a system in which each partition contains one or more data processing resources such as processors and storage structures. A system controller manages the allocation of the processing resources to each partition. The allocation of resources to each partition is based on the task each partition is required to perform. For example, if the current task being performed by a partition requires more memory, and the system as a whole has free available memory, the system controller will allocate more memory to that partition. Since the resources are shared so that two partitions contain interconnected hardware, an interface to connect these resources is required. Each of the partitions can then send a reset signal to the interface block which will reset the input and output logic associated with that partition without affecting the other partitions. Since each partition has variable resources depending upon the current task, the system controller has to track which resources are allocated to which partition in order to know which resources should be reset if that partition requests it.

A problem with this type of system as applied to mobile communications devices is that the full flexibility of allocateable resources adds additional hardware (e.g. a system controller and interconnecting hardware), increasing the size and power consumption of the device, which is highly undesirable. Furthermore, since the range of tasks being performed on a portable communication device is much more restricted than those performed on a personal computer, full flexibility to be able to allocate resources to individual partitions is not required Preferred embodiments of the present invention overcome these problems.

The inventors have appreciated that dedicated data processing resources may be provided for specific processing tasks so as to improve performance. In this way, a system controller to allocate resources is not required, reducing size, weight and power drain of the device. An independent reset of these resources is provided so that only the device requiring a reset is affected, and the remaining processing resources can continue to operate unaffected, improving the performance of the system as a whole.

An embodiment of the present invention can advantageously be applied to mobile communications devices using the common analogue or digital standards such as the second generation Global System Mobile (GSM) communications standard or the Digital American Mobile Phone System (DAMPS). Alternatively, the system can be applied to devices using the third generation Universal Mobile telecommunications standard (GETS). It may even be applied - 4 - to mobile communications devices of the dual band type that are able to communicate both on GSM and UMTS networks.

In accordance with the present invention there is provided a method and system for resetting one or more processors in a multi-processor system comprising the steps of issuing a request reset signal from an output of a first data processor, applying the reset request to an interrupt request input on at least one other processor to notify the lo other processor that a first processor has requested a reset, and applying a reset signal to a reset input of the first processor.

Preferably, the electronic device is a mobile communications device.

An embodiment of the invention will now be described in detail by way of reference to the accompanying drawing, in which: Figure 1 shows a block diagram of apparatus showing the reset architecture of a dual CPU electronic device embodying the invention.

Fig. 2 shows the circuitry for monitoring activity of the software and processor; and Fig. 3 shows the wave forms generated in operation of that circuitry.

Referring to figure l, there is shown a two-processor system comprising a camera l connected to an associated applications central processing unit (ACPU). There is also provided an antenna 5 which provides remote radio communication with a network using a modem 3. The modem 3 is in turn connected to a communications central processing unit (CCPU). The ACPU and CCPU are interconnected with reset circuitry which allows one of the processors to be reset while the remaining processor can continue to operate undisturbed. The reset output of the ACPU is connected to the interrupt request input of the CCPU. Similarly, the reset output of the CCPU is connected to the to the interrupt request input of the ACPU. Each of the reset lines is then connected to a logical OR gate and the output of the gate is connected to the reset input of each processor. A reset line is also provided from the power supply unit (PSU) 15 which provides the other input to both OR gates, so that both processors may be reset when the device is powered-up. In this example, the reset signals are active "high" to aid understanding, whereas they would normally be active "low" when the invention is implemented.

If, for example, the CCPU is not responding due to problems maintaining contact with the radio network the CCPU will request a reset via the CCPU reset line. The reset line is used both to notify the other processors via the interrupt request input (IRQ) that the CCPU has requested a reset, and to act as the reset input to the CCPU. Interrupt service routines are provided in the software to allow the recovery from a known good state.

A similar procedure occurs if the ACPU is not responding, perhaps due to the software running the camera facility being stuck in a loop.

Preferably, the data processing resources are those located in a mobile communications device.

In a further embodiment, a watchdog timer is provided to monitor any period of unresponsiveness of the processors. If the timer expires after a predetermined length of time, the timer prompts the unresponsive processor to send an interrupt request signal to all other processors and then to send a reset signal to the reset input of that processor.

The watchdog timer is a hardware block containing a count register and counter logical. The account register is regularly reloaded with a value that represents the watchdog timeout period. The clock signal is applied to the counter causing it to count down to zero. If it reaches zero then a re-set request is issued to the processor to indicate that a watchdog timeout has occurred.

In yet a further embodiment, an acknowledgment signal is also provided in addition to each reset line for each processor. As in the previous embodiment, if the software running on the CCPU takes longer to execute than expected, and the watchdog timer expires, a reset signal will be sent to the interrupt request (IRQ) of the other processor. The other processor then acknowledges the reset of the CCPU by sending a reset acknowledgment signal back to the CCPU.

Only on receipt of this signal will the CCPU actually be reset, which ensures data is not lost if the two processors are communicating with each other.

In a further embodiment, each CPU may be provided with its own dedicated memory structure such as RAM or ROM memory, so that if the CCPU has to be reset, the software running on the ACPU and its associated memory can continue to run without losing data stored on the storage structure.

Furthermore each memory structure can also store the current state and recent states of the processor, which will allow the processor to recover from a known good start-up state or the most recent state rather the start-up state, thereby avoiding further loss of data.

Then on page 6 at the end: A further embodiment, for monitoring correct operation of the software can be implemented using the circuitry shown in figure 2. In this, a capacitor 20 is connected between an input of a comparator 22 and ground.

The capacitor is charged by a resistor 24 connected between capacitor 20 and the supply voltage Vdd. When the capacitor voltage exceeds a threshold of e.g. 0.7 x Vdd after a time t, a reset request is generated. To stop the reset request occurring the software regularly instructs an open drain output port of 26 of the - 7 - processor to discharge the capacitor. The open drain port is connected to the capacitor.

With 1 Mega Ohm resister and 1 microfarad capacitor, the time taken for the capacitor to charge to 0.7 x Vdd is 1.2 seconds. Thus in normal operation the software would discharge the capacitor repeatedly at intervals within 1.2 seconds. If the software got stuck in a loop then the capacitor would carry on charging up to the reset threshold.

The wave forms generated by the circuitry of fig. 2 are shown in fig. 3.

Claims

1. A method for resetting one or more processors in a multi-processor system comprising: issuing a request reset signal from an output of a first data processor; applying the reset request to an interrupt request input on at least one other processor to notify the other processor that a first processor has requested a reset; and applying a reset signal to a reset input of the first processor.

2. A method for resetting one or more processors according to claim 1 in which each processor performs a set processing task or tasks.

3. A method for resetting one or more processors according to claims 1 or 2 in which the reset signal is issued after the expiry of a watchdog timer.

4. A method for resetting one or more processors according to claims 2 or 3 in which the other processor or processors acknowledge the request of the processor requesting the reset.

5. A method for resetting one or more processors according to claim 4 in which the processor requesting the reset is only reset once the other processors have acknowledged the request.

6. A method for resetting one or more processors resources according to claims 1 - 5 in which one or more of the processors is an applications processor. 9 -

7. A method for resetting one or more processors according to claims 1 - 6 in which one or more of the processors is a communications processor.

8. A method for resetting one or more processors according to any proceeding claim in which the processor requesting a reset re-establishes communication with the other processor or processors once the reset signal has been applied to the reset input of the processor.

9. A method for resetting one or more processors according to claims 1 - 8 in which each processor has its own memory.

10. A method for resetting one or more processors according to claim 9 in which both the processor and its associated memory are reset upon receipt of a reset signal to the reset input of the processor.

11. A method for resetting one or more processors according to any proceeding claims in which the processor is reset with the program counter at zero.

12. A method for resetting one or more processors according to claim 9 in which the state of the processors are periodically recorded in the memory.

13. A method for resetting one or more processors according to claim 12 in which the processor that has requested a reset is reset and the most recently recorded state is loaded from the memory unit.

14. A system for resetting one or more processors in a multi-processor system comprising: means for issuing a reset request signal from an output of a first data processor means for applying the reset request to an interrupt request input on at least one other processor to notify the other processor that the first processor has requested a reset; and means for applying a reset signal to a reset input of the first processor.

15. A system for resetting one or more processors according to claim 14 further comprising a watchdog timer.

16. A system for resetting one or more processors according to claim 15 further comprising means for the other processor or processors to acknowledge the request of the processor requesting the reset.

17. A system for resetting one or more processors according claims 14-16 in which the multi processor system is a multi processor mobile communications device.

18. A system for resetting one or more processors according to claim 17 in which the mobile communication devices uses one of the plurality of second-generation mobile communications standards.

19. A system for resetting one or more processors according to claim 18 in which the second-generation mobile communication standard is the Global System Mobile (GSM) communications standard.

20. A system for resetting one or more processors according to claim 17 in which the mobile communication device uses the third-generation Universal Mobile Telecommunications System (UMTS).

21. A system for resetting one or more processors resources according to claims 14 - 20 in which one of the processors is an applications processor.

22. A system for resetting one or more processors according to claims 14 21 in which one of the processors is a communications processor.

23. A system for resetting one or more processors according to claims 14 22 in which each processor has its own memory.

24. A system for resetting one or more processors according to any proceeding claim in which each timer is integrated into each processor.

25. A system for controlling the reset procedure of one or more processors substantially as herein described with reference to the drawing.

26. A method for controlling the reset procedure of one or more processors substantially as herein described with reference to the drawing.