GB2408899A - DAB receiver which looks up non-interfering digital processing clock frequencies from a table for each RF reception channel - Google Patents

Abstract

The digital broadcast receiver comprises an RF receiver 4. The RF reception frequency is selected using a selector 12. This selector also provides an input into a look up table of frequencies 14. Announcements from the look up table of frequencies 14 is used to control the speed of a clock 16 in a processor 6 for processing the digital signals, such that harmonics of the clock frequency do not interfere with the radio reception. The system may be applied to a DAB receiver, wherein three clock signals per reception frequency may be used. One for header processing, a lower one for body processing with equalisation, and a lowest one for body processing without equalisation.

Description

1 2408899

PROCESSOR CLOCK FREQUENCY SWITCHING IN DIGITAL

RECEIVERS

Field of the invention

This invention relates to processor clock frequency switching in digital receivers such as receivers of the type used in the digital audio broadcast (DAB) system.

Background of the Invention

DAB is based on a system originally known as the Eureka 147 Project. There are two broadcast bands in DAB known as Band III and L- Band. The band III frequency range is 174-240 MHz whilst that of the L-Band is 1452-1492 MHz.

Radio signals are transmitted within these bands using a system known as Coded Orthogonal Frequency Division Multiplexing (COFDM). In this, the bits of data to be transmitted are modulated onto carriers within the band using Quadrature Amplitude Modulation (QAM). The bits are thus multiplexed across a band of frequencies and are also multiplexed in time. A fast fourier transform of the QAM carriers is then taken for each set of modulated bits in turn to produce a DAB symbol. A number of time sequential symbols are then transmitted as a frame. This is typically of 24 milliseconds in duration and commences with a header containing identification information about the data in the frame and then the encoded data.

Receivers for DAB signals require high performance high speed digital processors to decode the received data.

Such processors are not required in known RF reception sets such as FM radio receivers. These high speed processors can cause interference with the RF components in a digital radio receiver. In larger digital radio products physical shielding of components can be included or the distance between the RF front end components and the digital processing can he made relatively large.

Shielding has cost and size limitations. In smaller digital radio receivers, especially small portable receivers the components will inevitably be in close proximity. Shielding is usually not practical both in terms of cost and size in such receivers and avoiding close proximity is not an option.

All systems which combine digital processing with the reception of RF are prone to interference between the digital electronics and the incoming RF signal. This is a result of RF emissions from the digital components. This is commonly referred to as digital noise. This interference can have a significant detrimental effect on RF sensitivity. For example, a DAB digital radio will contain an RF front end requiring a high level of sensitivity for adequate reception of broadcast data. A powerful digital processing chip is also required to decode the incoming DAB data. As discussed above, in larger receivers shielding can be provided and close proximity avoided. This is not possible in smaller receivers where the physical proximity of the digital components will mean that interference is more likely to be a problem.

The RF interference from digital components will be determined by their clock speed and harmonics thereof. It is therefore particularly relevant when data is being clocked from the memory bus between the processor and external RAM memory.

The range of RF frequencies which can be input to a digital radio are predetermined by the DAB standard being used with the broadcaster and the specific RF frequency then selected by the user. Therefore, it is not possible to change the RF frequency when there is interference from digital components.

Summary of the invention

In accordance with one embodiment of the invention there is provided a digital receiver with an RF reception unit and a digital processor with a dynamically adjustable clock frequency.

Preferably a different clock frequency or set of clock frequencies is selected for each radio reception frequency such that the selected frequency or set of clock frequencies have harmonics which do not interfere with the RF frequency.

Preferably the optimum clock frequency or set of clock frequencies are stored in internal memory and are selected in response to selection of an RF reception frequency to dynamically reset the processor system clock to the optimum clock frequency.

Preferably there is also stored data relating to the minimum processor speed required in different modes of operation and the clock speed is selected according to the selected mode thereby minimising power consumption.

The invention is defined with more precision in the appended claims to which reference should now be made.

Brief description of the drawings

A preferred embodiment of the invention will now be described by way of example with reference to the drawings in which: Fig. l shows a block diagram of a digital radio in which the invention may be embodied; Fig. 2 shows a flow diagram illustrating operation of an embodiment of the invention; and Fig. 3 shows a block diagram of the circuitry required to embody the invention.

Detailed description of preferred embodiment

Fig. 1 shows a digital receiver which may be a miniature digital receiver such as the PURE (RTM)Digital PocketDAB 1000 (RTM). This particular receiver uses the Diablo (RTM) FS2010 module with 8 mb of external SDRAM. This module contains an RF front end receiver component and the Chorus (RTM) FS1010 DAB processor chip.

In Fig. 1, an antenna 2 receives DAB frames which are demodulated from the carrier frequency and an RF receiver 4. The data is then passed to a DAB processor 6 which examines the header for each frame and using the information contained therein is able to reconstruct the received digital radio signal selected by the user. This is then passed through an audio processor 8 which provides a signal to a loudspeaker 10 for playback to the user.

The Chorus processor chip referred to above is provided with a dynamically programmable clock frequency. One purpose of this programmability is that in a battery powered portable device the clock speed is set to a relatively high level to process the header at the beginning of each frame of DAB data. It is then reduced to a lower level whilst the less intensive body of the DAB data frame is processed. This minimises power consumption and maximises battery life. The lower frequency is chosen to be the minimum possible depending on other processing which is occurring whilst the main body of the DAB frame is being processed. This other processing may be audio post-processing governed by equalizer (EQ)settings. For example, some radio products feature a number of predefined EQ settings so the user may select these at any time or switch EQ off.

Control of clock frequency in the chip is performed by a programmable control unit. This is loaded with software appropriate to cause it to perform the clock frequency selection. s

This programmability of the Chorus chip can be exploited to reduce or eliminate interference with the RF front end receiver. This is done by providing a look up table with optimal high and low clock frequencies for each RF multiplex frequency which the digital radio is capable of tuning into. In this particular implementation the look up table will contain a set of one high and two low processor clock frequencies for each possible digital radio multiplex frequency. These optimal clock frequencies are calculated by mathematically modelling the interaction of the clock harmonics and the radio multiplex frequency for each possible multiplex frequency. When doing this it is important to take into account the IS minimum clock frequency requirement to perform DAB processing and/or equalizer processing in each case. The modelling does generate a set of candidate clock frequencies which produce minimal interference with the multiplex radio frequency. From these model candidate clock frequencies, individual clock frequency values are chosen. Preferably the frequency values selected are the lowest possible frequencies. Making the selection on this basis will minimize power consumption.

A block diagram showing schematically how the apparatus of figure 1 is modified in an embodiment of the invention is shown in figure 2. In this, the antenna 2 and RF receiver 4 receive the signal in the same manner as figure 1. An RF frequency selection 12 is used to select the RF frequency. An output from this indicating the RF frequency is also supplied to as an input to a look up table of frequencies 14 which is stored in system memory.

This look up table has two outputs a high frequency and a low frequency which are supplied to a processor 6. This includes an internal clock 16 which is set using the high and low frequencies. The high frequency is selected to process the DAl3 frame header and the low frequency to process the DAB frame body.

The method of operation of this circuitry is illustrated better with reference to figure 3.

The first step in this is that a system tunes to a radio multiplex at 18 using the selection 12 of figure 2 and a high clock frequency value is retrieved from the look up table 14 and 20. This frequency is dependent on the selected multiplex frequency.

Next a determination is made as to whether audio equalization is active or not. If it is, then the minimum low clock frequency which can be used may be higher than that which would be possible if it were not active. Thus, if it is active an upper low clock frequency value is selected at 24 and if it is not then a lower low clock frequency value is obtained at 26.

The system then goes on to process the DAB data frames at 28. Firstly the clock frequency value is set to the high value at 30. The DAl3 frame header is then processed at 32. This contains information about the signals which are included in the DAB frame. The clock frequency low value is then selected at 34 and the main body of the DAB frame is processed at 36. This includes taking the inverse fast fourier transform of each DAB symbol and subsequently extracting from the thus determined frequency domain data the bits encoded onto the various characters using QAM.

These bits are then reconstructed into digital data in accordance with information included in the DAB frame header.

Thus, it can be seen that for each DAB frame the clock is set first to the high value to process the header and then to the low value to process the frame. This continues whilst the receiver is operational.

As an alternative to mathematically modelling the harmonics of the received frequencies, a lot more clock frequencies could be selected based on experimental measurement. However, this has generally been found not to give as good a performance as the modelling.

The invention has been described here in terms of a digital audio broadcast receiver. However, it can be embodied in any product which receives data from an RF transmission and includes digital processors. Any such system requires optimal sensitivity to maximise the RF reception performance and this can be adversely affected by interference with digital components. No significant modification is required to apply the invention to systems other than DAB digital radio which receive RF data and also include powerful digital processors. All that is required is that the processor is capable of dynamic clock frequency selection under software control, and a table of optimal values is provided within the system software, or some other method of calculating these values is provided.

Claims (8)

1. A receiver for digital broadcast signals comprising an RF receiver, and a digital processor coupled to the RF receiver to decode the digital signals, the digital processor including a clock to control the speed at which signals are processed, and means to control the clock frequency in dependence on the frequency at which the digital broadcasts are received whereby interference with the RF receiver is minimised.
2. 2. A receiver according to claim l in which the RF receiver operates on a selected one of a plurality of predetermined RF frequencies and the means to control the clock frequency includes a memory for storing clock frequencies which minimise interference with the RF frequencies, and means for applying a stored frequency to the clock in dependence on the selected RF frequency.
3. 3. A receiver according to claim 2 in which the memory means stores at least two clock frequencies for each of the predetermined RF frequencies.
4. 4. A receiver according to claim 3 in which a higher one of the at least two clock frequencies is applied to the clock to decode a high frequency portion of the received digital signal and a lower one of the two clock frequencies is applied to the clock to decode a lower frequency portion of the received digital signal.
5. 5. A receiver according to any preceding claim in which the receiver is a digital audio broadcast receiver.
6. 6. A method for receiving digital broadcast signals in a receiver having an RF receiver, and a digital processor to decode the signals, the digital processor including a clock to control the speed at which signals are processed, the method comprising the step of controlling the clock frequency in dependence in the frequency at which the digital broadcast signals are received, whereby interference with the RF receiver is received.
7. 7. A receiver for digital broadcast signals substantially as herein described with reference to the drawings.
8. 8. A method for receiving digital broadcast signals substantially as herein described.