GB2400725A

GB2400725A - Electrodeposited semiconductors

Info

Publication number: GB2400725A
Application number: GB0308826A
Authority: GB
Inventors: Imyhamy Mudiyansela Dharmadasa; N B Chaure; John Young; Anura Priyajith Samantilleke
Original assignee: Sheffield Hallam University
Current assignee: Sheffield Hallam University
Priority date: 2003-04-17
Filing date: 2003-04-17
Publication date: 2004-10-20
Anticipated expiration: 2023-04-17
Also published as: GB0308826D0; GB2400725B

Abstract

Consecutive layers of CuInGaSe2 are deposited from a single electrolyte by varying the deposition voltage of the electrolytic depostion bath. The level of the deposition voltage controls the conductivity type of the deposited layer, and sequential, pn or pin layers may be deposited without changing the electrolyte. Homojunction and heterojunction photovoltaic device configurations are described.

Description

À :: . :.

FABRICATION OF SEMICONDUCTOR DEVICES

Field of the Invention

The present invention relates to the field of fabrication of semiconductor devices and in particular, but not exclusively, the present invention relates to the fabrication of semiconductor devices comprising CulnGaSe2 and CuinGaTe2 based materials.

Background to the Invention

o The development of thin film solar cells for solar energy conversion requires two or more semiconducting layers to form the photovoltaic active junctions.

These devices can be pen type homo or heterojunctions, n-n-p, n-i-p, p-pn type two heterojunctions combined with ohmic or Schottky contacts for current collection. In the place of one or two junctions, it is possible to have multi junctions (eg: n±n---n-i-p---p-p+) in order to enhance the efficiency of solar energy conversion. In many situations, the growth of different semiconductor layers requires combination of many expensive techniques, making the final product expensive.

It is known to use electrodeposition to grow semiconductor layers and this method has the advantage that it is, as compared to other methods, relatively low in cost. US patent no. 4388483, Basol discloses use of electrodeposition to deposit cadmium telluride. US patent no. 4400244, Kroger is another reference that discloses use of electrodeposition of cadmium telluride.

International patent publication no. WO 98/48079, Davis is a further reference that discloses use of electrodeposition. This reference describes electrodeposition as applied to copper-indium-galliumdiselenide precursor films.

A problem with the teachings of the above identified references is that, in general, a different electrolytic bath has to be set up for deposition of each given À . À.

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layer. This results in considerable expense in fabrication of semiconductor devices. Furthermore obtaining layers of a predetermined electrical characteristic is therefore relatively complex and time consuming.

An improved method of electrodepositing copper-indium based photovoltaic compounds is disclosed in Canadian patent application no. CA 2056609, in the name of Shin and Qiu. This reference concerns deposition of a thin film of a chalcopyrite semiconductor compound on a conducting substrate. This reference discloses control over the stoichiometry of a given film being deposited by To applying a voltage between a cathode and an anode in contact with the electrolyte for circulating current with a certain density in the electrolyte. However this reference does not disclose a method or apparatus that provides pre- determined control over the electrical properties of actual layers being deposited.

None of the above identified references disclose a method or apparatus for enabling the doping level of semiconductor layers being deposited to be varied in a relatively straightforward manner and such that two or more layers of different electrical properties are deposited from the same electrodeposition bath.

In view of the above there is therefore a need to improve methods and apparatus associated with electrodeposition of semiconductor materials.

Summarv of the Invention An object of the present invention is to provide a low cost method of 2 fabricating semiconducting devices.

A further object of the present invention is to provide an improved electrodeposition based method for depositing at least a first semiconductor layer and a second semiconductor layer from the set of layer types comprising: [p+, p, i, 3 o n and n+].

À . . a À e À À À À À A further object of the present invention is to provide a method to establish the growth of a plurality of semiconductor layers from the same electrodeposition bath composition such that the deposited layers are doped to different and predetermined degrees by varying the deposition voltage.

According to a first aspect of the present invention there is provided a method of electrodepositing at least a first and a second layer of a semiconductor based material on to a substrate layer, said method comprising the steps: To selecting a required semiconductor based material to be deposited; in accordance with pre-determined conditions specific to said selected semiconductor based material, configuring an electrodeposition bath arrangement to effect successive deposition of each of said layers on to said substrate layer, said method characterized in that it further comprises the step of: in respect of a said layer to be deposited, selecting said pre-determined go conditions, including a pre-determined deposition voltage level, to ensure that deposition of said layer results in said layer having a pre-determined electrical characteristic.

Preferably, said pre-determined electrical characteristic corresponds to the degree of p-type or e-type doping.

Preferably, said pre-determined electrical characteristic corresponds to a doping level selected from the set comprising: 3 0 p±type, p-type, i-type, e-type and n±type.

i:: :: se.. ee46e::, Preferably, said semiconductor based material comprises a compound comprising group 1,111 and Vl elements.

Preferably, said group I element is copper (Cu) Preferably, said group 111 element is indium (In).

Preferably, but not exclusively, said method comprises the making of a photovoltaic device, said substrate layer and said other semiconductor layers o each having a different band gap energy value to an adjacent layer.

Preferably, said substrate layer comprises a wide band gap semiconductor window material layer that is deposited from a different electrodeposition bath composition to said at least first and said second semiconductor layers, said first and said second absorber layers being configured to function as photon absorber layers.

Preferably, said at least first and second semiconductor layers are deposited from the same electrodeposition bath composition.

Preferably, said step of selecting said predetermined conditions, including a predetermined deposition voltage level, comprises the following steps for a given electrolytic bath composition under consideration: 2 5 measuring the PEC signal of a series of samples of said material grown at different deposition voltages; plotting the PEC signal of each said sample verses the applied deposition voltage; identifying deposition voltage regions associated with particular electrical characteristics; and : A.: :: :: .e:' a: À À 1.

from said plotted and identified voltage deposition regions, selecting a given deposition voltage associated with a desired electrical conductivity.

Preferably, the first layer deposited is an e-type layer.

Preferably, the outer most layer deposited is thereafter configured with a metal contact.

To Preferably, said metal contact is deposited using the technique of vacuum evaporation.

Preferably, a first layer comprises a first compound deposited on said substrate layer, said first compound being deposited from the first electrolytic bath and said second layer and/or subsequent layers comprise a different compound to said first compound, said second compound being deposited from second electrolytic bath.

Preferably, said first compound comprises e-type InSe and said second compound comprises CIGS.

According to a second aspect of the present invention there is provided a semiconductor device fabricated according to the method of claim 1 appended hereto.

Suitably the resultant device may, for example, comprise a photovoltaic so solar cell, a pen junction, a p-i-n junction, a heterojunction or an optoelectronic device. However those skilled in the art will appreciate that a wide range of semiconductor devices can be fabricated using the methods of the invention.

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Brief Description of the Drawinas

For a better understanding of the invention and to show how the same may be carried into effect, there will now be described by way of example only, specific embodiments, methods and processes according to the present invention with reference to the accompanying drawings in which: Figures 1 (a) to 1 (e) respectively show x-ray diffraction (XRD), photoelectrochemical cell (PEC), optical absorption, band gap variation with growth voltage and x-ray fluorescence (XRF) results for GaSe layers; Figures 2(a) to 2(e) respectively show results obtained from XRD, PEC, band gap measurements and XRF for CuGaSe2 layers; Figures 3(a) to 3(e) respectively show XRD, PEC, band gap measurements s and XRF results for InSe layers; Figures 4(a) to 4(e) respectively show XRD, PEC, band gap measurements and XRF results observed for CuinSe2 layers.

go Figures 5(a) to 5(e) respectively show XRD, PEC, optical absorption, band gap variation and XRF results observed for CulnGaSe2 layers; Figure 6 details, in accordance with an aspect of the present invention, the steps involved in fabricating semiconductor devices of the type comprising CuinGaSe2 compounds as described under Example 5 of the detailed

description;

Figure 7 schematically illustrates a 12-layer graded band gap solar cell structure fabricated with an e-type window material, the semiconductor device 3 o having been fabricated in accordance with the methods of the present invention.

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a** .s À e The graded band gap multilayer devices having a greater number of layers (e.g. 36 layers) have also been grown using the methods of the present invention; Figure 8 schematically illustrates a 12-layer graded band gap solar cell structure fabricated with a p-type window material, the semiconductor device having been fabricated in accordance with the methods of the present invention.

The graded band gap multilayer devices having a greater number of layers (e.g. 36 layers) have also been grown using the methods of the present invention; Figure 9 details the dark l-V characteristics of a 2 mm diameter solar cell prepared using the methods of the present invention to construct a glass/FTO/n CdS/n-CIGS/p-CIGS/Au layered device structure. The following device parameters were observed for this solar cell device. Rectification factor at 1V = 104, diode quality factor, n = 1.90 and potential barrier height, fib =1. 10 eV; Figure 10 details (a) the capacitance (C), conductance (G) and (b) 1/C2 against the bias voltage for the same diode (a diode having the l-V curves shown in Figure 8). These results show expected Schottky-Mott behaviour and produce the following parameters for the device and the material; Potential barrier height, fib =(1.05 + A) 1.10 eV, doping concentration 1.8 x 1046 cm3; Figure 11 details the steps involved in fabricating a multi-layer (for example 1 2-layer) semiconductor device of the type identified in Figure 7; and ss Figure 12 details the steps involved in fabricating a 4-layer semiconductor device as identified in Example 6 of the detailed description.

Detailed Description of the Best Mode for Carrvinn Out the Invention 3 0 There will now be described by way of example the best mode contemplated by the inventors for carrying out the invention. In the following e;e À. e.e.:e:e description numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent however, to one skilled in the art, that the present invention may be practiced without limitation to these specific details. In other instances, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present invention.

According to a preferred embodiment of the present invention a wide band gap window material (first semiconductor layer) may be grown using a first electrolytic bath (or using other methods such as chemical bath deposition) and a To plurality of other semiconductor absorber layers (forming a combined second layer) may be grown from another electrodeposition bath thereby making it simple to fabricate a plurality of heterodunctions. In accordance with the present invention growth of a given layer as compared with a growth of a next required layer is achieved by varying the deposition voltage. The process permits large area thin film solar cells to be fabricated, and the method can be used to produce a wide variety of electronic devices based on various families of semiconductor materials.

Examples of layers that may be grown in accordance with the methods of 2 o the present invention include, for example: (i). Establishment of the growth of a p-type GaSe window material.

This layer is hard and adhesion is excellent. The band gap is 2.05 eV, and liquid/solid junction produces up to 730 mV open-circuit voltage indicating excellent properties for PV applications.

(ii). Establishment of the growth of p-type CuGaSe2 material for intermediate or window layers with a band gap of about 1.68 eV.

(iii). Establishment of the growth of InSe material with a band gap of 1.80 eV for window or intermediate layers. Growth of p, i, n and n±type InSe layers, is also possible.

::: ::: Àe.e À .e:e À (iv). Establishment of the CulnSe2 material with p, i, n and n±type semiconducting layers.

(v). Establishment of the CuinGaSe2 material with p+, p, i, n and n± type semiconducting layers.

(vi). Substantial multi-layer devices comprising photvoltaic 4-layer, 5layer, 12-layer and 36-layer device structures that exhibit PV activity can be fabricated using the methods of the present invention.

The methods of the present invention also apply to growth of CulnGaTe2 based materials and the methods also apply generally to growth of semiconductor based materials comprising group 1, lil and Vl elements.

Making use of an electrodeposition technique, new window materials of ptype conduction and CulnGaSeTe based absorber materials have been grown.

These are namely, GaSe (Eg=2.05 eV), CuGaSe2 (Eg=1.68 eV), InSe (Eg=1.80 eV), CulnSe2 (Eg=1.01 eV) and CulnGaSe2 (1.30-2.30 eV) suitable for thin film solar cell development. To reduce the cost of deposition, and to improve go processing steps, the growth of p+, p, i, n, or n±type material layers from the same electrolytic bath has been established for InSe, CulnSe2 and CulnGaSe2 materials. These layers are suitable for use as window, intermediate or absorber materials in multilayer graded band gap solar cells. Semiconductor devices comprising CuinGaTe2 based materials may also be fabricated in accordance with the present invention.

The methods of the present invention may be used to make semiconductor devices comprising binary, ternary, quarternary or other multinary compound semiconductor materials.

Examples of semiconductor layer deposition conducted in accordance with the methods of the present invention ::: ::: i eel.. i.e:.

e.e as- ln the following examples material depositions were carried out using three-electrode or a two-electrode electrodeposition technique. Both methods produce similar results, but the absolute values of voltages applied are different.

Example 1 (GaSe): The aqueous solutions of 0.008M Ga2(SO4)3 and 0.004M H2SeO3 were mixed in a vessel, and pH value was lowered to 2.05 until a clear solution is obtained. Using a three electrode or two- electrode system, the To material layers were deposited on to a glass/conducting glass cathode at a temperature of (2540) C without stirring the solution. The material layers deposited were identified as polycrystalline GaSe using X-ray diffraction as shown in Figure 1 (a). The electrical conductivity type of the layers were determined using a photoelectrochemical (PEC) cell arrangement. The polarity of the opencircuit voltage produced by illuminated solid/liquid junction provides the information on electrical conductivity type. Figure 1 (b) shows the conductivity type variation as a function of the growth voltage, indicating the p-type conductivity for all the values of growth voltages. Figure 1(c) shows the band gap of 2.04 eV for materials grown at-0.75 V with reference to Ag/AgCI electrode and Figure 1(d) so indicate the variation of the band gap as a function of growth voltage. At low negative voltages, the band gap is close to that of Se (1.5 eV), and the band gap increases to 2.05 eV corresponding to that of GaSe as the negative voltage increases. However, further increase of the cathode voltage causes the observed reduction of the band gap due to deposition of Ga-rich layers. Figure 1 (e) shows the variations of stoichiometry of the GaSe films as determined by XRF.

The most notable qualities of this material are that their excellent adhesion property and the production of a high open-circuit voltage of 730 mV for the solid/liquid junctions made out of GaSe/Ga2(SO4)3 aqueous solution.

Example 2 (CuGaSe2): The CuGaSe2 alloy was electrodeposited from an aqueous electrolyte containing 0.008M CUS04, 0.008M Ga2(SO4)3 and 0.004M A A. A ::: :: as. ee. ..e a:.

H2SeO3 solutions. The material layers were deposited on to glass/conducting glass substrates with pH1.9O, t(25-40) C and without stirring. The resultant layers were characterized by X-ray diffraction, PEC, optical absorption and XRF, and results are summarised in Figure 2. Polycrystalline material layers are p-type in electrical conduction and the band gap varies as shown by Figure 2(d). The band gap variation as a function of growth voltage show two anomalies and these changes correspond to visible peeling off of the layers at these two particular voltages. It is therefore important to avoid these voltages during the growth in order to keep the adhesion property of the semiconducting layers.

Example 3 (InSe): InSe compound was electrodeposited from an aqueous electrolyte containing In2(SO4)3 and H2SeO3 solutions. A typical set of parameters is given below.

0.004M In2(SO4)3, 0.004M H2SeO3, pH2.00, t(25-40) C and no-stirring during the growth.

The resulting layers were characterized using XRD, PEC, optical absorption and XRF. The results are summarised in Figures 3(a) to 3(e) and indicate the formation of polycrystalline InSe phases. These material layers show a full range of electrical conductivity types varying through p, i, n and n+. This is an excellent property of the compound and the electronic device structures could be fabricated while deposition by simply varying the applied voltage. At low negative values, selenium is preferentially deposited which is a p-type semiconductor with 2 band gap of 1.5 eV. As the negative voltage increases, indium deposition increases and therefore InSe compound formation takes place. As a result the material becomes e-type and the band gap saturates 1.8 eV, which is the reported band gap for InSe compound. The anomaly at 0.6V occurs due to visible peeling off of the layers during growth. XRF results shown in figure 3(e) so indicate the stoichiometry changes with growth voltages and these results are helpful in determining the optimum growth conditions.

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Example 4 (CulnSe2): CulnSe2 layers were also grown using 3-electrode or 2-electrode system from an aqueous electrolyte containing CuS04, In2(S04) 3, and H2SeO3. A typical set of parameters used is as follows.

0.002M CuS04, 0.004M In2(SO4)3 and 0.004M H2SeO3, pH2.00, t (25 40) C and no-stirring during growth.

The material layers were characterized using XRD, PEC, optical absorption and XRF. The results are summarised in Figures 4(a) to 4(e) and indicate the o possibility of achieving the full range of p, i, n and n+ electrical conductivities from the same bath, simply by varying the growth voltage. The band gap variation from 2.00 eV to 1.00 eV is observed with the indication of presence of two phases within the deposited layers. XRF results shown in figure 4(e) indicate the stoichiometry changes with growth voltages and these results are helpful in determining the optimum growth conditions.

Example 5 (CulnGaSe2): CulnGaSe2 compounds were electrodeposited using aqueous solutions. Typical growth parameters are: 0.002M CuS04, 0.004M In2(SO4)3, 0.004M Ga2 (S04)3 and 0.004M H2SeO3, pH2. 00, t(25-40) C and no-stirring during growth.

The material characterisation results arising from XRD, PEC, optical 2 5 absorption and XRF are shown in Figures 5(a) to 5(e). The resulting polycrystalline layers exhibit a full range of p+, p, i, n and n+ electrical conduction types. The band gap values vary from 2.2 eV to 1.6 eV. The XRF results are helpful in determining the growth voltage required for desired stoichiometry of the layers.

e:: c' :: :: :. :e: '.e:: a; Fig. 6 details, in accordance with the present invention, the steps involved in fabricating a CulnGaSe2 based series of semiconductor layers as described in this example. The process steps described for this example are similar for fabrication of semiconductor layers in accordance with the present invention using different materials in both this example and the other examples given herein.

At step 601 the required materials for fabrication of the series of semiconductor layers are obtained as are the required items of processing JO equipment and chemical/physical treatments to be applied. The electrolyte is configured for effecting deposition by selecting the appropriate chemicals and adjusting the parameters such as pH and temperature. Following step 601, at step 602 a selected clean glass/conducting glass substrate is washed in acetone followed by distilled water. Following step 602, at step 603 a small piece of the conducting glass substrate is inserted in the electrodeposition set up and used as the cathode. A layer of CIGS is then deposited on the small selected piece of substrate. Following step 603, the same process (as at step 603) is repeated for further pieces of the conducting glass substrate, but wherein semiconductor material, in each repetition, is grown at a different potential, but from the same 2 0 electrolyte. Following obtaining all the required samples at steps 603 and 604, at step 605 the PEC signal of each sample is obtained and the signal verses the deposition voltage plotted so as to identify p+, p, i, n and n+ deposition regions for the electrolyte being used. Following step 605, at step 606 the required deposition voltage determined for a layer having a required electrical characteristic is then selected using the graph obtained at step 605. In this way required semiconductor layers may be grown that have a desired electrical conductivity.

Step 606 comprises growing a series of semiconductor layers wherein the so layers each have a desired electrical conductivity. In other words each of the required layers has a desired amount or degree of doping. The important point is that the deposition voltage associated with a given layer to be deposited is known ::: ::e '.e., .. .:.

from the plotted graph of the PEC signal verses the growth voltage for a particular electrolytic bath of a particular semiconductor material to be grown. In this way the deposition voltage may therefore be subsequently varied, in accordance with values read from the graph, such that layers having the required electrical conductivity are deposited in a straightforward and predetermined manner as desired. Examples of use of such a graph of PEC signal verses growth voltage for a given electrolytic bath in growing semiconductor layers having desired electrical conductivity's are described in relation to Figs. 11 and 12 herein.

o Example 6: Demonstration of the possibility of fabrication of multilayer graded band gap device structures In order to harness the solar spectrum more efficiently, the front window material should have a wide band gap material like ZnSe (2.67 eV), CdS (2.42 s eV) or GaSe (2.05 eV), and the absorber material band gap should gradually reduce as move away from the window material. A publication by C H Henry of Bell Laboratories, New Jersey, USA in 1980 (J. Appl. Phys. 51 (8) August 1980, P4494) provided theoretical calculations for a 36-layer device and commented that such devices are impracticable (i.e. not possible to make). However, the o present invention enables the growth of any number of layers on both nand p type window materials. As a demonstration, 3- layer, 5-layer, 12-layer and 36 layer device structures showing PV activity have been fabricated. For example, Figures 7 and 8 show the energy band diagrams of 12-layer graded band gap solar cell structures fabricated on e-type and p-type window materials respectively. The l-V and C-V characteristics of a 3-layer device (glass/FTO/n CdS/n-CIGS/p- CIGS/Au) are shown in Figures 9 and 10 with corresponding parameters. These preliminary multilayer devices have a huge potential for development to achieve high solar energy conversion efficiencies in the future.

3 o Fig. 11 details, in accordance with the present invention, the steps involved in fabricating a semiconductor device of the type identified in Fig. 7. r i

At step 1101 a model of the device to be fabricated is constructed. In the example given the device to be fabricated is that schematically illustrated in Fig. 7. Following step 1101 at step 1102 a glass/FTO/n-type window layer is obtained. This layer is selected for use as the substrate layer for growth of a series of absorber layers of a photovoltaic device. Additionally the required processing equipment and treatments to be applied to the window layer are prepared ready for use. Following step 1102, at step 1103 the appropriate voltage for e-type InSe is selected by reviewing the PEC results of a set of samples (obtained in a similar manner as described in relation to Fig. 6). The To substrate layer is then placed in the InSe electrolytic bath and an e-type InSe layer is grown, at the selected voltage, on the substrate layer. Following step 1103, at step 1104 the substrate layer comprising the e-type InSe layer is transferred from the InSe electrolytic bath to a prepared CIGS electrolytic bath.

In respect of the CIGS electrolytic bath the appropriate voltage for growing an n type CIGS layer on the InSe layer is selected. The selected voltage for the CIGS electrolytic bath is obtained from the graph of the PEC signal verses growth voltage for CIGS. Following step 1104, further layers are grown at different voltage potentials, from the same CIGS electrolyte. The number and type of consecutive layers are selected as desired. Thus further deposited consecutive 2 o layers may comprise n, i and p-type layers respectively. Following step 1105, at step 1106 the substrate comprising the consecutive layers as prepared at step 1105 is transferred back to the InSe electrolytic bath wherein the appropriate voltage for p-lnSe is selected and applied for deposition of a p-type InSe layer on a p-type CIGS layer. Following step 1106, at step 1107 the resultant device :5 comprising the substrate and the subsequently deposited layers is withdrawn from the InSe electrolytic bath and is processed so as to make a metal contact on the p-lnSe layer. In the preferred embodiment of the present invention the metal contact is deposited at step 1107 using vacuum evaporation, following chemical and heat treatments. However those skilled in the art will realise that the p-lnSe o layer may be configured using other methods. Following step 1107, at step 1108 the resultant fabricated semiconductor device may be attached to a circuit to Àe Àe: .e es: À provide a useful function, such as, in the case of a photovoltaic cell (having a series of absorber layers as in this example), to provide electrical power.

Fig. 12 details the steps involved in fabricating a 4-layer semiconductor device.

At step 1201 a model of a semiconductor device to be fabricated is constructed. For example an n-n-i-p device may be desired to be fabricated.

Following step 1201, at step 1202 a glass/FTO/n-type window layer is obtained.

The selected window layer is configured for use as the substrate to grow a series of layers (e.g. absorber layers for a photovoltaic device) thereon. Also at step 1202, the required processing equipment and treatments to beapplied for fabrication of the semiconductor device are prepared for use in the subsequent steps. Following step 1202, at step 1203 an e-type CIGS layer is grown on the glass/FTO/n-type substrate layer. The e-type CIGS layer is grown at a pre- selected voltage for the given CIGS electrolytic bath, the selected voltage being obtained from the graph of the PEC signal verses the growth voltage for the particular electrolytic bath under consideration. Following step 1203, at step 1204 further voltages are selected from the PEC signal verses growth voltage go graph for the particular (CIGS) electrolytic bath under consideration. Each selected voltage corresponds to a particular CIGS based layer having a predetermined electrical characteristic, that is a predetermined doping level. The CIGS electrolytic bath under consideration is then run at the various appropriate voltages for predetermined lengths of time so as to successfully deposit a series :s of required layers each having the desired electrical characteristic. In this way the following layers are deposited in succession on the n- CIGS layer: An i-type CIGS layer; and A p-type CIGS layer.

Following deposition of all required layers at step 1204, the resultant semiconductor device is removed from the CIGS electrolytic bath. Following step À 3 À À À À À 3 À À À.e:.. À: Àe.e 1204, at step 1205 the resultant device is required to be completed by way of incorporation of a metal contact on the p-type CIGS layer. Various methods may be used to deposit such a layer, as is known to those skilled in the art, but in the preferred embodiment, the metal contact layer is deposited on the p-type CIGS layer using vacuum evaporation, this deposition step following appropriate chemical and heat treatments of the resultant device.

Following step 1205, at step 1206 the completed semiconductor device is attached to an electrical circuit so as to provide its required function. In the case To of a fabricated photovoltaic device, the device may be attached to such a circuit so as to provide useful electrical power.

Claims

À À À À À À . À . . . . ce. a À Claims: 1. A method of electrodepositing

at least a first and a second layer of a semiconductor based material on to a substrate layer, said method comprising the steps of: selecting a required semiconductor based material to be deposited; in accordance with pre-determined conditions specific to said selected semiconductor based material, configuring an electrodeposition bath arrangement to effect successive deposition of each of said layers on to said substrate layer, said method characterized in that it further comprises the step of: in respect of a said layer to be deposited, selecting said pre-determined conditions, including a pre- determined deposition voltage level, to ensure that deposition of said layer results in said layer having a pre-determined electrical characteristic.
2. The method according to claim 1, wherein said pre-determined electrical characteristic corresponds to the degree of p-type or e-type doping.

3. The method according to claim 1 or claim 2, wherein said pre determined electrical characteristic corresponds to a doping level selected from the set comprising: p±type, p-type, i-type, e-type and n± type.
3 o
4. The method according to any preceding claim, wherein said semiconductor based material comprises a compound comprising group 1, lil and Vl elements.

À À À À À . . . . À À À . À À À . . À À . . . À . À À À À À À
5. The method according to claim 4, wherein said group I element is copper (Cu)
6. The method according to claim 4, wherein said group lil element is indium (In).
7. The method according to any preceding claim, wherein said method comprises the making of a photovoltaic device, said substrate layer and said other semiconductor layers each having a different band gap energy value to an adjacent layer.
8. The method according to any preceding claim, wherein said substrate layer comprises a wide band gap semiconductor window material layer that is deposited from a different electrodeposition bath composition to said at least first and said second semiconductor layers, said first and said second absorber layers being configured to function as photon absorber layers.
9. The method according to any preceding claim, wherein said at least o first and second semiconductor layers are deposited from the same electrodeposition bath composition.
10. The method according to any preceding claim, wherein said step of selecting said predetermined conditions, including a predetermined deposition voltage level, comprises the following steps for a given electrolytic bath composition under consideration: measuring the PEC signal of a series of samples of said material grown at different deposition voltages; plotting the PEC signal of each said sample verses the applied deposition voltage; À À À c: À identifying deposition voltage regions associated with particular electrical characteristics; and from said plotted and identified voltage deposition regions, selecting a given deposition voltage associated with a desired electrical conductivity.
11. The method according to any preceding claim, wherein the first layer deposited is an e-type layer.
12. The method according to any preceding claim, wherein the outer- most layer deposited is thereafter configured with a metal contact.
13. The method according to claim 12, wherein said metal contact is s deposited using the technique of vacuum evaporation.
14. The method according to claim 1, wherein a first layer comprises a first compound deposited on said substrate layer, said first compound being deposited from a first electrolytic bath and wherein said at least said second layer o and/or subsequent layers comprises a different compound to said first compound, said second compound being deposited from a second electrolytic bath.
15. The method according to claim 14, wherein said first compound : comprises e-type InSe and said second compound comprises CIGS.
16. A semiconductor device fabricated according to the method of claim 1.
17. A semiconductor device as claimed in claim 16, wherein said device comprises a photovoltaic device.

À À À À . . . À
18. A semiconductor device as claimed in claim 16, wherein said device comprises at least one junction device from the set of devices comprising: a pen junction; a p-i-n junction; and a heterojunction.
19. A semiconductor device as claimed in claim 16, wherein said device comprises at least a first and a second junction device.
20. A semiconductor device as claimed in claim 16, wherein said o device comprises a solar cell.
21. A semiconductor device as claimed in claim 16, wherein said device comprises an optoelectronic device.