GB2395032A

GB2395032A - Parallel read and write access to a flash memory

Info

Publication number: GB2395032A
Application number: GB0320762A
Authority: GB
Inventors: Chun-Hung Lin; Chih-Hung Wang; Chun-Hao Kuo
Original assignee: Solid State System Co Ltd
Current assignee: Solid State System Co Ltd
Priority date: 2001-08-07
Filing date: 2002-08-07
Publication date: 2004-05-12
Anticipated expiration: 2022-08-07
Also published as: GB2395032B; GB0320762D0

Abstract

A method for accessing a flash memory, the flash memory including a plurality of storage sectors and a data-access operation to one sector of the storage sectors involving a plurality of stages handled by an access controller, in which a first data-access operation is performed and a subsequent data-access operation is begun while the first is not yet complete, as in a parallel pipeline.

Description

GB 2395032 A continuation (74) Agent and/or Address for Service: Edward

Evans Barker Clifford's Inn, Fetter Lane, LONDON, EC4A 1BZ, United Kingdom

WINDOW-BASED FLASH MEMORY STORAGE SYSTEM AND MANAGEMENT

AND ACCESS METlIOPS THEREOF This monition relates to the field of mass storage device, and more particularly, to

a windowbased flash memory storage system and a management method and an access method thereof.

A flash memory storage as stem is typically composed of two conponeats: a f lash memory unit and an. access controller; wherein the flash memory unit is used for data storage, while the access controller is used to control the access operation Mom the CPU to the flash memory as well as manage the data storage space ofthe flash memory. The access controller is typically composed of a microprocessor, a ROM unit, an SPAM unit, a flash memory interface, and a CPU interface; wherem the ROM unit is used to store the program code sunning on the microprocessor, the SWAM unit is used to store window-related in formation and also serves as a data buffer between the flash memory and the CPU; the CPU interface is used to allow the access controller to commuriicate with the CPU; and tile Bash memory interface is used to allow the access controller to gam access to the data stored the Dash memory.

The data storage space ofthe Dash memory is partitioned into a plurality of blocks, and most blocks are categorized into a number of subgroups, called vvindows. We use some specific blocks to record the related information of each madow (herein

( 2 referred to aswindow information). In order to reduce SRAM cost, a common practice is to store all the window information the flash memory and Only a part of the window inforon that is essential to window operation is loaded to the SRAM When it is desired to perform a readlwIite operation on a cerram window, it is re *urea to first load the associated window information. of this window into the SRAM In the event of a sudden power failure, however, some newlypdated window information con entry stored in the SRAM would be lost, and thus Me flash tory still stores the old version of the window informab.orl ConsequcD0y, in the next option of the same win-

dow when power is reshined to rorrnal, the older version ofthe wintov information will be loaded to the SRAM, resulting in the use of incorrect window information Furthernore, when a read/write operation is to be performed on a certain sector of the active window, it would involve r. nany stages of operations. If there are two sectors to be accessed, the apparently used method is to execute the readable operation on the first sector until all the stages are completed and. then proceed to tb.e recite operation on the nact sector. This scenic access method is undoubtedly low in efficiency. One con-

vendonal sorption to this problem i' to use two or more dash memory bang to perform ineang readJwrite operation to Rip increase the access One drawback to this solution, however, Is that it is limited in finctionality and would hare the penalty of an oiy large power consumption.

It is therefore an objective of this invention to provide a window-

based flash memory storage system and a management and an access method thereof which can provide a more reliable way of loading window information and can help enhance access

perlormancc throgl larallel pipelined operation on the reading/writing of a number of sectors. A windovi-hasetl flasl1 memory storage system according to the invention in cludes a window-based region and a redundant reserved region, wherein the window-

based region Ls used to store a number of widows, each window bum associated tenth a number of physical blocks. The redundant resented region includes a dc-link area, a notow-information area, a dc-liDlc informaii.on area, and a boot-information area; whem the dc-link area mchdes a plural.i of dynamic allocation. blocks, each bemg a31ocatable to any window. The window-infomaton area includes a plurality of dove information blocks, which are used to store a specific window-infomation set Mat is dedicated to a certain window. The dynamic 1inlc information area. is used to record the stat of the allocation of the dynamic allocation blocks to the windows Further the Mention proposes a management method for the window-based flash memory storage systemic. 1'1e window-based hash memory storage system includes a flash memory mat hang a plurality of window-informio.D block, each being used to store a praliU of wio.tow-isfomadon sets, eachdow-infomation setback associated with a window. My this m5U)8gemeDt method, at tb.e start of the wintow^baset for memory storage system, the first step to select a subgroup ofthe wintowPormation block'; ant fink Me selected window-info tion blocks, seLe one window-infotion set and loading the selected windowmion set into an SR unit n, the window-

infotion set associated with a user-ected window is put into an acvo-dow van-

able area of the SEAM; and when acotha window is swished to the active window, moving the current dow-information set stored the acvc window Table area to a resewed window in the i. In the event a user-selected window is Boat win

( any window-infornation sets stored in the SRAM, one of the windowinformation sets is selected and a taclup thereol'copicd to the flash memory, and the backup copy of the whdow-inf'ormation set is replaced with one of the window-information sets stored in the windo\v-informatio' hlock corresponding to the user-selected window to set the user selected window as tle active svhclow In one preferred embodiment of the invention, the checking of whether the win-

dow-information set loaded in the flash memory is correct is based on the writing block indictor and the spare block indicator.

Moreover, the foregoing step of c whether the cost of the window-

information set is based on the citeda (1) if30 that an error corrosion code in the Widow information is correct; (2) trek that a check sum code in the window mfiormabon correct (3) vet that the spare block is an erased block; (4) verif ring that the counts of a logic block lumber, a come counter, and the last accessed sector in Me wridug block are consistent Lath the contents of the wrung block indicator, and (5) verifying that the conterrt of a phaslock Bag in the wnt block is unequal to He value used to indicate the first blanlc sector in the nadow- infortion block.

If Me cone of the wm.towiDfomation is inccuTect, one prep embodi-

mnt of {he invention performs the step onlooking through the previous Vendor informa don gets stored the wdwinfomation bloclcg for the lam usable wdow-information set; within the n cable window-information set is the wintow-infotmation set that con trues the oorrecle error correction cotc the connect checl: sum code the wm dow-infarmatio \

( s Mother preferred embodiment ofthe mveoD. performs the step of finding all the blocks belonging to the window irk We Dash memory for rebuilding the window-

informadon set.

Still moreover. the invention proposes an access method for a windowbased flash memory storage systcn includes a flash memory unit having a window-based region and a redundant resewed region and iachlding a plurality of baffler areas. In the window infor-

mation area of the redundant reserved region, each window-informstion set is associated with a sped window having a "umber of physical blocks. By this access method accord-

ing to the invention, the first step is to load the window-infomation set of a user-sdectet Row into an SRAM; and then find a requested sector uestet by a tata re-

queshug component, and Fen loading the requested sector Tom the Hash memory into one ofthebu areas. Hem, the requested sector aptly loaded in one ofthe buffer areas Ls transferred to the data-access "ques'g come-on. The foregoing two steps of er-

riDg all the requested sectors to the deta-accens requesting component are performed a parallel pipelines manna.

Furthermore. to invention proposes another access method for a windowbased flash memory storage system including a flash memory unit having a window-based region and a redundant r eser\ied region and including a plurality of buffer areas. In the window-information area ot the redundant region, each window information set is associated with a specific window having a number of physical blocks. By this access method according to the invention. the first step is to transfer writing sector that is to be written into the flash memory to one of the buffer areas, and then computing for the address of the writings sector in the flash memory. Then, it is checked whether the previous read operation on the flasl1 memory is correct; and then issuing a write-enable signal to tile lllSll f11lory.1 title',

( sfe the wing sector to the flash memory. The foregoing two steps of bansf all the requested sectors to the data-access requesting corn'onent are performed in a par-

allel pipelines mariner.

In-conclusion. the invention is characterized by the use of the redundant reserved

region to store the related window information of each window as well as the use of Past Buildup Method Notma1 Buildup Method and Blockby-Block Search Buildup Method to 10 build the required window information to quidly inmate the windowased Dash memory storage svste',. Moreover. the invention also utilizes parallel pipelined operation to enhance the perform lance of read/write operations The Oregon can be more fi:lly Food by reading the follow detailed de-

scaption of the preferred embodiments web reference made to the accompany draw-

lags where FIG. 1 a echoic &am showing the dam structure ofthe flaw memory in He windaw-based flash memory storage system according to the iove2xtion; PIG. 2 is a schematic diagram thawing a preferred embodiment of the data strac-

ture of the.redundant Ma in data blew or wring block; PIG. 3 is a schematic diagram shod a preferred embody of the data sty tore of to iting block indicator or spare block indicator PIG. 4 is a Bow diagram saving a prepared embodi of the procedure per-

formed by each module the windowased flash memos storage system of the urvendon ding madtwrite operation;

( FIG. 5 is a schematic diagram showing a preferred embodiment of the architecture of the active window and the resewed window in the SRA1 PIG. 6 is a flow diagram showing a preferred embodiment of the procedure pa-

formed by the invention when loading vendor information into SRAM; FIG. 7 is a flow diagram showy a preferred embodiment of the procedure per-

formed by the Window Read/\iVnte Module dunog a write operation; FIG. 8 is a schematic diagram showing a conYentj.oDa1 method for reading data Bom sectors, FIG. 9 is a flow diagram showing a preferred embodiment of the procedure per-

formed by the i-veon for reading data from a number of sectors through a parallel pipe lined operation; PIG 10 a flow diagram showing a preferred embodiment office procedure per-

formed by the invention for reading data through a parallel pipelined operation; FIG. 11 is a flow diagram showing a preferred embodiment of ache procedure per-

formed by the invention for writing Late to flash memory through a parallel pipelined op-

eration; and FIG. 12 is a flow diagram shod a preferrer embodiment of the procedure per-

formed by the Swenson for wig data through a parallel pipelined operahom FIG. 1 is a schematic diagram showing the data snuchre ofthe storage space of the Dash memory unit in the windowbased flash memory storage system according to the invention As shown, the data storage space of the flash memory is partitioned into a

( mlmber of blocks, and these blocks are arranged into two groups, including a window-

based region 120 and a redundant resewed region 121.

The window-based region 120 includes a number of window areas, which are num-

bered Tom #O to #15, and each of which is partitioned into 512 blocks except the last window area $15 which may not include exactly 512 blocks. The redundant reserved re-

on 121 is partitioned into four areas: a dyc-link area 101, a windowinformation area 102, a dynamic-link information area 103, and a bootiDformation area 104. The dy-

nsmclink area 101 includes a number of block which are allocated for use by each wm-

cow. In the window-informacion area 102, two blocks are allocated for each window to record its window information. The dic-link information area 103 is used to record the status of the allocation of the blocks of the dynarraclink area 101. The boot-

infonntion Tea 104 is used to record the locations of the dy>link area 101, the wdow-iDfomation area 102, and the tynamic-link information area 103 as well as the total number of logic sectors in the =ndowbased Dash memory storage system, and so ok As shown TRIG. 1, the physical format 105 repres=ts the access scheme utilized by the access controller to gain access to the flash menoy, and the logic format 106 represents the access scheme utilized by the CPU to gain access to the window-based Desh memory storage system The data storage space of Me flash memory Ls partitioned into a total of 8,192 physical blocks, each physical block being composed of 32,,sectors. In the physical fort 105, tb.ese physical blocks 107 are rbered Tom O to 8191, and their relative blocks 108 are clustcredby 512 bloclmto apluralrof subgroups. ExceptWm-

dow #15, eaGt doWs associated blows Me fiery mom O to 511, "d the reline blocls Me redundant resewed region 121 are uNmbered Mom 512 to 103. The logic format 106 lacludes a number of logic blocks 110 (which are n. umberet Tom 0 to 7999) or

( a number of relative logic blocks 109 (which are clustered by 512 blocks into a plurality of subgroups). Except Window #15, each windows associated logic blocks are numbered Mom O to 51 1. Smcc each logic block is composed of 32 logic sectors, the logic sector& 1 12 are numbered Mom O to 255999 The relative logic sectors 111 arc clustered by 16384 sectors into a plurality of subgroups. Except Window #15, each windows associated logic blocks are numbered from O to 16383. It can be seen Mom FIG. 1 that the Cows logic addressing method would be incapable of gaining access to the redundant reserved region leach window includes three lids of blocks: data blocks, writing blocks, and spare blocks. When it is desired to perform a write operation on the previous data block, the write operation will be first directed to tb,e wing block and if Me meting block is All and another write operation is intended, then the wnt blocl: will replace the previous data block, and the previous data block will be erased into a spare block which can be thenused to serve as a writing block for another write operation As shown FIG. 1, Window O includes a total of 512 data blocks in Window #0 100 as well as one wiiimg block and one spare block allocated to the dynamic-link area 101. The window information of each window uchtes a tata-block-to-logicblock map ping table, the writing block indicator, and the spare block indicator. In the case of a win . dow having 512 da" blocks, one writing block, and one spare block, it requires the use of two sectors to record all the window information of this window. These two sectors are used to record the mapping relationships between the 512 data blocks and logic blocks in their userata area, and are further used to record the writing block indicators and Me spare blow indicators in their redundant area.

( PIG. 2 is a schematic diagram showing a prefened embodiment of the data struc-

tre of the redundant area in data block or Snug block.

As shove, the Relative Logic Blocl; Number 201 '3 used to register the relative logic block number that is mapped to tbia bloc). The Window Number 202 is used to indicate the window that is associated with this block. The Cycle Counter 203 is used to indicate whether data is old version or new updated version; and it operates in such a mncr that during each write operation, the content of the cycle counter of the writing block is set to be equal to the cycle courter of the data block increased by one. The Phase Lock Flag 204 is used to register the location of the sector that is used to backup the window information of the currently active window, arid whose value can. be used to indi-

cate whether Me previous backup action on the window information is successful The Check Sum Code 205 is used to register the check sum code of the foregoing data. The Data Error Flag 206 is used to indicate wb. ether the data stored in the user-data area in the sector is correct or not Tb.e Error Correction Code 208 is used to store the error correction code for the user-data area In the sector.

PIG. 3 is a schematic diagram shoving a preferred embot of the data struc-

Wre ofthe meting block indicator or spare block indicator.

As shown, the Relative Block Number 301 is used to register the relative 10giG block mambo is mapped to Ibis block. The Rcladve Logic Sector Number 302 I' used to indicate whether the block is a spare block (when its value is OtPFPF) or to indicate the location of the sector that is the law one written into the wnting block The Window Num-

ber 3 03 is used to indicate the window Mat is associated with this blow. The Writing-block Cycle Cotter 304 is used to register the cement value of the cycle counter of the writing block The Check Sum Code 305 is used to stow the check sum code excluding block error

( flag arid the error correction code. The Window Information Cycle Counter 306 can be used to indicate which window information block contains the newest data. The Block Error Flag 307 is used to indicate whether the block is invalid. The Error Correction Code 308 is used to store the error correction code for the user-data area.in the set tor.

The access operation to the flash memory is performed by three modules: Window Buildup Module, Window Read/Write Module, alla Flash Memory Access Module. The Window Buildup Module is responsible for loading the window information of uscr-

selected window into the GRAM The Window Read/Write Module is used to determine which. bloc); the Dash memor, is to be accessed in response to the (:PV's request. The FMory Access Module is capable of perform direct read, write, erase, and status check operations on the Bash memory m. response to request Tom other modules. This can help Simplify the operational complexity of the other modules. For example, the flow diagram of FIG. 4 shows a preferred embodiment of the procedure performed by each module m the dow-based flash memory storage system of the invention Turing read/wnte operation As shown, the But strep 401 is to en to the Window Buildup Module; the second step 402 is to excavate the Window Readlrite Module, and the third step 403 is to check whether althe requested sectors have been accessed;if N O,the pro-

cedure returns to the step 401; and if ARES, the procedureis ended. Durugttis procedure, The canto the Flash M cm ory Success M odule nncludedin the fkst substeg ofthe step 401 and the third subcp of the step 402.

In the ececohon of the Window Buildup Module, the pi concem is to eden tirade nnrge Filthy Waldo ws stored un the SO. To reduce the tEnc ofsvvitc be tvveen different wLndovvs in the pesh r3euJory and the SAW;, it is required to load at least two window-infomation sets asso;;i.ated with two windows being svitrhed. Although the

( loading of a larger number of window-information sets would reduce the sntcbiag time, it would undesirably increase SRAM cost. In one preferred embodiment of the invention three window-information sets are loafed, which should include thc window-informabon set associated with Window #0 since Window #0 is filactiox,.ally related to the DOS file system operation The window information loaded from the Dash memory to the SR includes the writing block indicator and spare block indicator (hereinafter referred to as window van-

ables). These window variables would be firequey accessed duno.g the operation of the nudor-based flash memory storage system; and therefore, order to reduce the com-

plety of software program and enhance the operational eBiaercy ofthe program code, it is a common practice to allocate these window Cables to fixed locations. For example, as shown in FIG. 5, the S1 addresses 40045, are defined as a reserved wdow-variable area 501 for the allocation of the window variables 503 of reserved window #0, the un-

dow variables 504 of resented window #1, and the window variables 505 of resewed window #Z.

When it is desired to switch to Window #O as the active one, since Shadow tfO is ally a resewed window, it is required to move the 20-Byte window variables horn the addresses 40019 to the addresses Z0-39, which are the locations in the actiYe-window variable area 502 where the window vanable 1 to window variable 20 are allocated. Tnis sotion makes Window #O become the active Widow. ADenaardls, if it is desired to switch to Window #2 as the active window, it its required to first move the Widow variables of Window #0 (which are currently stored in the active-window variable area 502) back to their original locanons, and then move the window variables ofthe resewed dow #2 to the active-window variable area 502, wh ch swindow t'2 become the activedow.

( In progranmi, the switchin, between Me Widows only requires the moved of the window variables 1-20, so that it In help reduce the complexity of the required program code and tam entice the overall operating efficiency of the window system.

When the user-selected window is not a resewed one, it is then reqliired to first move the active window back to the reserved-wndow area, and then choose a reserved window and make a backup copy of it to the flash memory, and finally load the window variables ofthe user-selected window to the acve-window Satiable area 502. Apparently, this backup scheme would not guarantee that the next use ofthe window information in the flash memory would be normal. There exists therefore a need for a solution that allows correct window information set to be loafed in SRAM the next use of the Window information in the flash memos.

The Artier provides three ways to solve the above-rnestioned problem (A) Fast Buildup Method; (B) Normal Buildup Method; and (C) Block-by-Block Search Buildup Method. (A) Past Buildup Method This method is capable of judging fast whence the current window information set stored inthe fly ah memory is correct based on the following cutena . (1) the error correction code the window iorrnation sector is correct; (I) the check sum code in the window information sector is correct; (3) the spare block indicated by the Spare Block Indicator is a block that was pre-

piously erased; (4) the writing block indicated by the Wnti Block Indicator contains logic block numbs, circle counter, and infoabon about the last wrinev. sector which are consistent with the data registered in Me Writing Block Indicator; and

( (I) the writing block indicated by the Writing Block Indicator contains a phase lock flag value that is unequal to the address ofthe first blank sector in the window-infomahon block related to the window.

In practice, since mom ofthe window information is normal, it is feasible to directly load the associated window-information set into the SRA and use this Fast Buildup Method to check whether the content of the loaded wD.dow-i.Dfomation set is normal. If not normal, either of the other two methods <:an be used to correctly load window infor-

ma;tion set into the SRAM.

Ill) Normal Buildup Method If the foregoing Fast Buildup Method is inapplicable, the Normal Buildup Method can be used if Rich looks through all the previously loaded windov-iormation sets to find the last usable P. dow-information set. Since Tic data-block-to-logic-block mapping table in the window-iormation set contains the information about the location of all the associated data blocks of the window, and the Writs Blocs; Indicator and the Spare Block Indicator contain the information about the locations of all the associated writing blocks and spare blocks of the widow, all the associated bloclss of this window can be found to help build up a correct vindow-information set for the window ant load this window-information set into the SRAM.

The usable window-infomation set mentioned above should meek the following criteria: (1) the data contained us the data-block-to-logiblock mapping table of the win-

dow-information set should contain no uncorrectable error correction code; and (2) the check sun code contained in the wntg block indicator and spare block in-

dica$or of the window-infomaion set is correct

( (C) Block-by-Block Search Buildup Method An alternative method to the Fast Buildup Method is the Blockby-Block Search Buildup Method, which searches through all the probable blocks to find back those blocks belonging to the window arid thus build up a new window-information set. Since the blocks of one window are unLrterchangeable with the blocks of another window, the search process can be conducted only through the window number area and all the blocks that have been dynamically allocated. If a spare bloclr is located within the dylink area, it would be difficult to dishing which window this spare block belongs to. TherG fore, it is only needed to first find all the data blocks and writing blocks that are associated with this widow, and then reallocate a new spare block. This allows the buildup of a normal set of Window information which is then loaded into the SRA1.

FIG. 6 is a flow diagram showing a preferred embodiment ofthe detailed proce dual steps performed by step 401, executing the U1-Lodow Buildup Module shown FIG. 4 for loading window information into SR -. La this procedure, the host step 601 is to check whether the user-selected window is the cly active window; if YES, the win-

dow operation is directed to the auTently active window; whereas if NO, the procedure goes to the next step 602 in which the currently active window is moved back to tle ret served window location The procedure then goes to the step 603, which it is checked whether ache user-selected wrndow is one of the reserved windows; if YES, the procedure goes to the step 609 in which Me user-sclccted window is swtch.ed to the active widow; whereas if NO, the procedure goes to the step 604, which one of the reserved mudows is selected and a backup thereof is copied to the Dash memory. The procure then goes to the step 005, which the Fast Buildup Method is used to load the dow-information set of the user-sdected window into the S1 If the loading is suc;cessfil, the procedure

( lumps to the end, whereas if filed, the procedure goes the new step 606, us which the Normal Buildup Method is used instead If the use of the Normal Buildup Method is sum cessfilL the procedure jumps to the end; and whereas if failed the procedure goes to the next step 607, in which the Blocky-Blodr Search Buildup Method is used to build up the required window information and copy a backup thereof to the Cash memory. In the final step 609, the window information is loaded into the active window area of SRAM to cause the user-.elected nador to be switched as the active window FIG. 7 is a flow diagram showing a preferred embodiment of the detailed proce-

aural steps performed by the step 402 shown FIG. 4 for exealting the Wndov Write Module. The first step 701 its to judge whether the write operation is directed to the opal writing block; if YES, the procedure goes to the step 702; whereas, if NO, the procedure goes to the step 705. In ache step 702, it Is judged whether the overwritten operation happens; if YES, the procedure goes to the step 703; whereas if NO, the proce-

dure goes to the step 707. In the step 707, it is checked whether to perform a pre-write opetior In the step ?03, the original fining block is donned up; and them the procedure goes to the step 704, in which the spare bloclc is allocated to the original writing block, and the procedure then retune to the step 701. In the step 701, if the result is NO, Me procedure goes to the step 705,

in which the original Hinting blocl; is cleaned up; and then the procedure goes to the step 706, m which the spare block is allocated to the currently accessed vr Mock; and the procedure then goes to the step 707, m. Rich it is checked whether to perform a pre-wnte operation; if N0, the procedure goes to Me step 709; vbereas if YES, the procedure goes to the step 70S, which a predate operation is performed; and the procedure then goes to the step 109.

( 17 In the step 709, a write operation is performed to write data into the writing blocks.

This wite operation will proceed until Me current writing block ll or the written data is completed The procedure Men goes to the step 710, inwhichit is checlred whether all the data ofthe user-selected window have been. Mitten; if NO, the procedure goes back to the step 701; otherwise, the procedure is ended.

The Scan ng up of the original writing block performed In step 703 and step 705 includes the following substeps (1) filling each blank sector in the writing block win the data in the data block (2) c the venting block to data blodr (i.e., updating the content of the datablock-to-logiclocl: mapping table in the window information); and (3) erasing the original data block to turn. it into a spare block.

The prevents operation porrned in step 707 its used to move the sector data the data blocks that will not be written by the CPU to the wring blows.

The step 402 shown FIG. 4 for eecuhng the Wutow Read/Write Module in rolves a relative simple read operation, which first checks whether the requested data are stored in the writing blows; if YES, a read operation is performed on the wndog blow to read the wasted data; Verses if NO, it indicates that the requested data are Cored the ! data blocks.

A parallel pipelined operation is used to perform the readwrite operation so as to enhance the access speed. The implementation of this parallel pipelined operation should meet the following system requirements; (1) at least two independent buyers in hardware configuration, ema when one buffer is used for communication With the CPO, Me other buffer is capable of performing access operation to the gash memory ooncurrl.y, and

(2) at least two consecutive sectors in the user-selected window that are accessed by the CPU.

The Cups operation of reading data from a sector in the Dab memory indudes three stages. Ic the first stage, the microprocessor computes where the address of the sector in the flash memory storing the Cups requested data is located. In the second stage, the microprocessor Issues a read request to the flash memory, then waits until the flash memory is ready, arid then fetches the requested data from the flash memory and puts them the buffer. During this stage, error correction is also performed to make any necessary corrections to the data. In the third stage, a ready signal is issued to the CPIJ to notify the CP13 that the buffer is ready to transfer data, alloqmg the CPU to fetch the requested data Bom the sector in the buffer.

Assume the first stage of operation needs 25 ms (microseconds) to complete, the second stage of operation needs 65 ms to complete, and the third stage of operation needs 100 ms to complete. Then, the reed operation on each sector requires a total of 190 me. As shown FIG. 8, for the read operation 801 on Me first sector, it requires 190 ms to com-

plete; and for the subsequent rear operation 802 on the second sector, it alto requires 190 ms to complete. Therefore, if there are a tom of n sectors to be read, the overall read oration on these n sectors will require 1 90*n ms to complete.

FIG. 9 is a flow diagram showing a preferred embodimeD: of the procedure per-

fomed by the inveion for reading data Rom a rancher of sectors Trough a parallel pipe-

linet operatiorr The read openLtion901 on. the first sector requires three stages and 190 ma to complete. tile preferred embodiment, the stage 1 is to Snot a requested sector requested by data-access requesting component, and the stage 2 is to load the requested sector Tom the flash memos into one of the buff areas, and the stage 3 is to transfer the

requested sector loafed in the buffer area to the da-access requesting component. After the read operation 901 proceeds to the second stage 902, the hrst stage 903 of the read operation on the second sector As shed; and aver the read operation 901 proceeds to the third stage 904, the second Wage 905 and Bird stage 906 of the read operation on the second sector are started one after one. As a result, the overall read operation 907 on the second sector takes just 100 ma (i.e., tl;e complete time of the third stage). Further, after the read operation 907 on the second sector proceeds to the third stage 908, the second stage 909 ofthe read operation. OD. Sector 3 and the first stage 910 ofthe read operation on Sector 4 are started one after one. As a result, the overall read operation on Sector 3 also takes just lOO ms. Therefore, it can be concluded that for n sectors, the overall read operation on those n sectors will take 190 + 100*(n-l) ms to complete.

FIG. 10 IS a flow diagram stomag a preferred embodiment of the procedure per-

forrned by tile inveIltion for performing read operation through parallel pipelired opera-

tion As shown, the first step lOOl is to proceed the first stage to compute for the address of the sector that Ls to be accessed. the next step lOO2, Me second stage is started, but only the first half of procedure is camed out; and the hem step 1003 is to compute for the address ofthe neat sector that is to be accessed. In the next step 1004, the second half of the procedure ofthe second stageiscnned out to complete the second stage of operation.

ID The next step 1005 The CPU checked to see if it As received ad The data Mom the previous sector in the buffer (d the carrel secoris the first secor,then this step ig nored),aud then the CPU isnodfiedto rovethedaafrorntbissectorunthebufEer.Inthe next step 1006,it checked to see K there are stilrennairung datsto beread;ifYlES,the procedure goes beck to the step 1002; whereas N O,the procedure goes to the nexttcp

( 1007, the CPU proceeds to receive data from the buffer unto all data are received. The procedure is then eroded.

The CPI's operation of writing data from a sector into the flash memory storage system also includes three stages. In the first stage, the microprocessor issue' a request to the CPU for data transfer, causing the CPU to transfer a sector of data to the buffer. In the second stage, the microprocessor computes for the address ofthe sector where the data are to be wnKen into. In the third stage, the previous mite operation is checked to see if all data are correctly written, and then. a write request is issued to write data into the flash memory. PIG. 11 is a Dow diagram showing a preferred embodiment of the procedure per-

formed by the invention for writing data to flash memory Trough a parallel pipelined op-

eratio In the preferred embodiment, the i.tng operation is divided into three stages.

The stage 1 is to transfer a writing sector that is to be written into the Dash memory to one of the buffer areas. The stage 2 is to compute for the address of the writing sector in the Dash memory. The stage 3 is to check. whether the previous write operation on the fl -

me,ory is correct and then transfer the writing sector in the buyer area to the Bash mem-

ory Moreover, in the preferIet embodiment, the write operation on stage 1 of sector 1 (llOl)protothestage20fsector 1 (1102)beforetheage 1 (llOl) iseded, alla the stage 2 (1102) is ceded before the stage 1 (1101) is ended, too. Ming the Ante op-

eration on stage 1 of sector 2(1103),the stage 3 of sector 1(1104) and the stage 2 of sector 2(1105) are started one after one. Ihe stage 2 of sector 2(1105) is ended first and then the stages ofsector 1(1104) end the stage 1 ofsector 2(1 1 03) are ended one after one.lillthe other stages to finish the write operation are starlet and then ended one after one like that.

FiDally, the stage 3 of the last sector(1 log) is shed and then ended mvidually.

( FIG. 12 is a flow diagram shoving a preferred embodiment of the procedure per-

fortned by the invention for writing data through parallel pipelirled operation which shows the detailed 3ubsteps in the step 109 ofthe flow diagram of FIG. 7. At the start of the Bow diagram of FIG. 7, the data in. the first sector is transferred to the buffer. In the flow dia-

grarn of FIG. 12, the first step 1201 is to compute for the address of the sector to be ac-

cessed in the flash mernoly. The new step 1202 is to wait until the CPU fills up one buffer, and then it is checked whether there are remaining data that haven't been put into the buyer, if YES, the CPU continues to transfer the data of next sector to the buffer. In the I next step 1203, it is checked whether the precious Wake operation is correctly cccuted (if the current sector is the first sector, then this step is ignored), and then a sequential scput signal and an address signal are issued to cause the data blithe buffer to be transferred to the dash menory. Then7 the next step 1204 is to compute for the address of new sector in the flash memory that is to be accessed in succession to the previous sector. Em, the next step 1205 is to wait until the completion of the data transfer Mom the buffer to the flash memory, and then a write enable signal is issued to the flash memory. In the next step 1206, it is eheclrod Nether the writing block Ls Fill; if YES, the procedure jumps to the step 1208, whereas if N0, the procedure goes to the next sup 1207, In the step 1201, it is clucked whether all data have been transferred; if NO, the procedure remans to the step 1202; whereas if YES, the procedure goes to the step 1208. the step 1208, it is checked whether the previous write operation is correctly executed; and then, the procedure is ended. During the parallel pipeline operation, if the write operation fails to execute cor rectly, the following substeps are executed: (1) stopping the parallel pipette operation;

(2) finding usable spare block; (3) moving the usefi1 sectors in the failed block to the spare block; (4) setting the block error Gag of the failed block, arid replacing the failed block with the spare block obtained in step (2); and (5) resum ng the parallel pipeline operation.

In conclusion, the invention has ':he fol.lowg advantages. The invention utilizes

three methods, i c., Fast Buildup Method, Normal Buildup Method, and Blockby-Block Search Buildup Method to load window infold don into SRAM, and then utilizes parallel pipclined operation to enhance the performance of ready operations, in such a manner that the access operation on the Act for is started when the access operation on the cement sector is halfcompleted.

The invention has been tescabed using exemplary preferred embodiments. 11ow-

erer, it is to be understood that the scope of the invent.ion not limited to the disclosed embodiments. On the contrary, it is intended to corer various modifications and Pinier arrangements. The scope of the cloth, therefore, should be accorded the broadest inter-

pretation so as to cocompass all such modifications and similar arrangements.

Claims

CLAI5IS:

1 A reading method to a Hash memory from a data-access requesting component, wherein the flash memory includes a plurality of storage sectors, and a read operation to one sector ot'the storage sectors needs a plurality ot' stages handled by an access controller, the reading method comprising: I performing a t'irst read operation to read a current sector of the storage sectors, and starting to perform a second read operation to a next sector of the storage sectors when the first read operation is not completed yet, wherein the second read operation starts before the first read operation ends thereby decreasing the time required to perform read operations and increasing overall system performance.

2 The reading method according to claim 1, further comprising: starthig to perform a third read operation to read a further next sector of the storage sectors when the first read operation and the second read operation are not completed yet 3 'I'he reading method according to claim I or claim 2, wherein the stages include a first stage for finding a sector of the storage sectors to be read, a second stage for transmitting an information to be read fiom the Hash memory hito the access controller, and a third stage for transmitting an information to be read in the access controller hito the data-access requesting component.

! 4. The reading method according to any of claims 2 or 3, further comprising recurrently performing the foregoing steps if another sector is still to be read.

5. l he reading method according to any preceding claim, wherein the second stage for the first read operation is overlapping with the first stage tor the second read operation' 6. 'l he reading method according to any of claims 3 to 5, wherein the third stage for the first read operation is overlapping with the second stage for the second read operation. 7. The reading method according to any of claims 3 to 6, further comprising: starting to perform a first stage of a third read operation to find out a further next sector of the storage sectors to be read when the first read operation and the second read operation are not completed yet.

8. l he reading method of claim 7, wherein the third stage of the first read operation, the second stage for the second read operation, and the first stage for the third read operation are overlapping.

9. A writing method to a flash memory fiom a data-access requesting component, wherein the flash memory includes a plurality of storage sectors, and a writing operation to one sector of the storage sectors needs a plurality of stages handled by an access controller, the writing method comprising: performing a first writing operation to write a current sector of the storage sectors, and

( starting to perform a second writing operation to a next sector of the storage sectors when the first writing operation is not completed yet wherein the second writhing operation starts before the first writing operation ends thereby decreasing the time required to perform writing operations and hicreasing the overall system pert'ornance.

10. 'I'he writing method according to claim 9 further comprising: starting to perform a third writing operation to write a further next sector of the storage sectors when the second writing operation is not completed yet.

11. 'I'he writing method according to claim 9 or claim 10 wherein the stages includes a first stage for transmitting an information to be written into the access I controller a second stage for finding a sector of the storage sectors in the flash memory to be written and a third stage for transmitting an information in the caccess controller into the flash memory.

12. The writing method according to claims 9 10 or 11 further comprising recurrently performing the foregoing steps if another sector is still to be written.

13. The writing method according to claim I I or 12 wherein the third stage for the first writing operation is overlapping with the first stage of the second writing operation. 14. The writing method according to claims 11 12 or 13 wherein the first stage and the second stage for the same writing operation are overlapping IS. The writing method according to claims 11 12 13 or 14 wherein the third stage of the first writing operation the first stage for the second writing operation and the second stage for the second writing operation are overlapphg.

16. A mmagPn' method for window-based Dash memory storage system having a flash memory unit including a window-information area partitioned into a number of wm-

dow-infotmation blocks, each window-information block bum used to store a number of wdow-formation sets, each wdow-infomacion set being associated with a window; the management method comprising the steps of; (1) at the start of the window-based flush memory storage system, selecting a subgroup of the madow-inform.a.tion Mocks; and Mom the selected wmdowinfolma40n blocks, sdeciing onf window-information get and Loading ache selected window iDformadon set into an SRA]vI unit; (2) puking a portion ofthewindow-infoabon set associated with suscr-selected Widow into an acve-window vocable area of the STEAM; (3) when the user-selected window is not the active window, mown" the portion of the wdow-inforrntion set stored in the active-window variable area to a reserved win-

dow ranablc area in the SRAM; and (4) in the event of the user-selected window is Tmssoasted tenth any wdow-

information sets stores in the SRAM, select one of tb.e previous windowinfomation acts and copying a backup thereofto the flash mernoy, and replace the backup copy ofthe window-information set with a selected one of Me wdow-information scat stored irr the window-information block corresponding to the user-selected window to set the user-

selected wmHow as the active window 17 À A management method for windowbased flash memory storage system according to claim 16, wherein the vvindow-infonnation sets loaded into the SRAM include one windowinformation set corresponding to Window #0.

( 8. A management method for window-based flash memory storage system according to claim 1, or I 7. wherein each window-information set includes: a data-block-to-logic-bIock mapping table, which store' the mapping relations between a plurality of physical data blocks and a plurality of logic data blocks; a writing block indicator, whose con is used to indicate the status of the Mating block Mat is currently berg used by Me window associated with the wintov-infomation set; and a spare blocl: indicator, whose content is used to indicate the status of a spare block that currently being used by the Widow associated with Me windowinformation set.

19. A management method for window-based flash memory storage system according to claim 18. wherein the loading of the window-information sets into the SRAM includes the substeps of: am the windov-information sets have been loaded, checking whether Me corre-

sponding wdow-information set is correct based on the contents of the writing block indicator and the spare block indicator, and if the windowinformatior sot is incorrect, then cog Me content of the -

dow-infomation set based or the data stored in ache Bash memory; and then, loading the corrected window information set into the SRAM.

20. A management method for window-based flash memory storage system according to claim I 9. wherein checking whether the window-inforrnatiori set is correct includes the substeps of: verifying that an error correction code in the window information is correct verifying that a check sum code in the window informatior is correct; velibing that the spare block is an erased block;

( verifying that the contents of a logic block number, a cycle counter, end a last accessed sector are consistent with the contests of the wrong block indicator, and "verify - that the content of a phase-locc f ag is unequal to a value used to indicate the first blanl; sector in the windowinformation block zi. A management method for window-based flash memory storage system according to claim I') or claim 20. \vherein the step of correcting the content of the window-information set based on the data stored in the flash memory includes the following substep: tooling for ad the blocks belong to the window to rebuild the window infold tion get through last usable window-infooo. set; Rein the usable wdow-

information set is the dow-information set that contains correctable error correction code of the datablock-to-logic-bloclc mapping table and contains a correct check mm code in the writing block indicator and the spare block indicator.

22. A management method for window-based flash memory storage system according to any of claims 19 to 71. wherein the step of correcting the content of the window information set based on the data stored in the flash memory includes the following substep: ending all the blocks belonged to the window in the flash memos ant rebuilding the wiDdowiormon set.

23. A wintow-based Dash memory storage system, comnsing: a wintow-based region which is partitioned into a Amber olwindow areas, each window area Earring a plurality of physical blocks; and a redundart resewed region, which includes: a dc-link area having a pluralizer of dynamic allocation blocks each berg used to allocate to one of the widows;

( a window-infomation area, which is associated web one of the windows and is used to store the window-iDfomaiion set of the associated window; a tynamic-link information area7 which is used to record the allocation status of the dynamic allocation blocks of the dyna>li area; and an bootinformation area.

24, A window-based flash memory storage system according to claim 23, wherein the boot-information area is used to record the addresses of the dynamic-link area, the window-information area, and the dynamic-link information area.

25. A window-based flash memory storage system according to claim 23, wherein the boot-information area is used to record the total number of logic sectors of the window-based flash memory storage system.

26 À An access method for window-based flash memory storage system including a Dash memos umt having a nndow-oased region and a redundant reserved region containing a window information area and mclud a pluralizer of buff areas, the window-information area being associated avid a pluralizer of mudows, each window had a number of physical blocks and associated with a specific window-infonPtion set; wherein each ofthe pbyncal blocks contains a number of sectors; the access method for windowbased flaw memory storage system comprising Me steps of: (1) load the ndow-information set of a user-selected window into an SRAM, (2) finding a requested sector requested by a daa-acce,s requesting component, and than loading the requested sector from Me flash memor, into one of the bump areas; (3) trfunug the requested sector loaded Me buffer area to the data-access requiem component; and

! (4) perfog said step (2) through said step (3) of all ache requested sectors by parallel pipeline operation.

27.An access method for window-based flash memory storage system according to claim 26, wherein while any one of the buffer areas is currently transferring data to the data-

access requesting component, another one of the buffer areas is capable of concurrently gaining access to the flash memory.

28.An access method for window-based flash memory storage system according to claim 26 or claim 27 further comprising when the requested sector has been loaded in the buffer area the step of: Performing a checking and error-correcting procedure on the requested sector by means of error correction code.

29 Man access method for window-based flash memory storage system according to claim 26, wherein, said step (2) further comprises the substep of: computing for the address of We requested sector.

30 An access methodior wtowased memory storage systemc}ud a Dam memory mat braving a vrindow-based region and a redundant reserved region containing a Now iformion area Id including a plurality of buffer areas, We dow-mfomaton area berg associated win a plurality of windows, each window had a Her of physical blocks and assocd with a specific window- infodon sat; wharcm each of the physical blocks coyotes a 'oar of sectors; the Hess method for windowased flash memory storage system comprising the steps of:

(1) transfer a writinO" sector that is to be whiten into the Dash memory to one of the buffer areas, and ther1 computing for the address of the wnt.ing sector in the flash mern ory; (2) checking whether the previous write operation on the flash memory is correct, and then hansfe the writing sector to the flash memory; and (3) performing said step (1) through said step (2) by parallel pipeline operation 31. An access method for window-based flash memory storage system according to claim 30, wherein while any one of the buffer areas is currently receiving the writing sector, another one of the buffer areas is capable of concurrently gains access to the flash mem ory. 32. An access method for wdovbased flash memory storage systeminabting aDasb memory unit havug a window-based region and a redundant reserved region cout;g a window Formation area and including a plurality of buffer areas, the window- information area being associated with a plurals of windows, each window having a number of physical blocks and associated with a specific mudow- information set; wherein each of the physical blocks cousins a Anchor of sectors, the access method for window-based Dash storage system including tbree stages stage 1: firming a requested sector requested by a data- access requesting compo nem; *sage 2: loading the requested sector from the Ash memory into one office buffer areas; and stage 3: transferring the requested sector loaded in the buffer area to the data access requesting component;

( wherein the three stages of all the requested sectors being performed by parallel pipeline operation; wherein between duration of operating, the stage 2 of a first recucsted sector, the stage I of a second requested sector being performed, whetem between duration of operating Me stage 3 of a first requested sector, the stage 2 of a second requested sector bc performed, and between duration of operating the stage 2 of the second requested sector, the stage I of a third rcs nested sector being performed. 33. An access method for window-based flash memory storage system including a flash memory unit having a wdow-based region and a redundant reserved region containing a window information area and including, a phral of buffer areas, the wtow-infDrmation area being associated with a plurally of windows, each window hi, a number of physical blocks and associated with a specific wiD.dow-infoma$ion set; wherein each ofthe physical blocks contains a umber of sectors, the access method for wdow-based fi&sh memory storage system including three stages: stage 1: transferring a writing sensor that to be written mto the flash memory to one of the buffer areas; stage 2; computing for the address of the writing sector the flash memory; and she 3: chewing whether the previous write operation on the Bash memory is correct, ant then transferring the wng sector the buffer area to the hash memory; warm the 6dh-ee of 1 the wrung sectors being performed by parallel pipe We operation; wherein the stage 2 of the first writing sector being performed during duration of the stage 1 ofthe first witmg sector, the stage 3 ofthe first wrding sector being performed

( dunag dmtian of the stage 1 of the second mung sector, the stage 2 of the second mnt mg sector being performed during duration of the stage 3 of the first wrmug sector;;md the Me 3 of the last wIiti sector is started and then ended individually.

34. A management method for window-based memory storage system, substantially as hereinbefore described with reference to the accompanying drawings.

35. A window-based flash memory storage system, substantially as hereinbefore described with r eference to the accompanying drawings. I 36. An access method for window-based flash memory storage system, substantially as hereinbefore described with reference to the accompanying drawings.

37. An access method for window-based flash memory system, substantially as hereinbefore described with-reference to the accompanying drawings.