GB2391780A

GB2391780A - DLL for maintaining synchronization between a received spreading code and a combined code generated by weighting and phase shifting a local spreading code

Info

Publication number: GB2391780A
Application number: GB0326184A
Authority: GB
Inventors: Yasuyuki Oishi; Kazuo Nagatani; Hajime Hamada; Yoshihiko Asano
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1998-07-17
Filing date: 1999-06-07
Publication date: 2004-02-11
Anticipated expiration: 2019-06-07
Also published as: GB0326184D0; GB2391779A; GB2391780B; GB2391779B; GB0326126D0

Abstract

A delay locked loop circuit for maintaining phase synchronization between a received spreading code included in a spread-spectrum signal and a reference spreading code in a mobile communications system. A reference spreading code generator 51 generates the reference spreading code, and a combined code generator 52 generates a combined spreading code from the reference spreading code by applying weights to a plurality of phase shifted occurrences of the reference spreading code and then combining the weighted occurrences. An arithmetic circuit 53, 54 detects a phase difference between the received spread code B and the reference spreading code using the combined spreading code A, and a voltage controlled oscillator 55 controls a phase of the reference spreading code on the basis of the phase difference. The combined code generator makes positive, and successively reduces in magnitude, the weights of a number n of reference spreading codes of small phase shift constituting a first half of a number 2n (where n is a positive integer) of reference spreading codes that have been successively shifted in phase, and makes negative, and successively increases in magnitude, the weights of n constituting a second half of the reference spreading codes that have been successively shifted in phase.

Description

DELAY LOCK LOOP CIRCUIT

This is a divisional of GB2340()07 and relates to a DLL circuit disclosed therein.

9.,-,2611 0

5 GB2340002 as well as another co-pending divisionalrelate to correlator circuits.

More particularly, the present invention relates to a delay locked loop (DLL) circuit for maintaining the synchronization bctwcn the received spreading code and a reference spreading code.

Direct-sequence code division multiple-access based upon dircct-sequencc 10 spread-spectrum (DS-SS) modulation has been considered as a wireless access scheme for next-generation digital mobile communications systems. In order to receive a spread-spectrum signal, a code phase of a spreading code on the transmitting side must be detected on a receiving side and a spreading code for despreading purposes must be generated so as to achieve phase synchronization with the spreading code on the 15 transmitting side.

Digital cellular wireless communication systems using DS-CDMA (Direct Sequence Code Division hlultiple-Access) technology have been developed as next generation mobile communication systems for implementing wireless multimedia communications. In a COMA digital cellular wireless communications system of this 20 kind, a base station transmits control inforrr.ation and user information after multiplying

this inronr.atic.^ s.ith a spreading code Individual m,obt.le stations spread and transmit information using a spreading code specified by the base station. In order for a mobile station to correctly reck He ir, fo:Tatio such As contra! information from. the base station in a CDMA digital cellular wireless communications system of this kind, it is necessary 5 to identify the timing at which the spread-spectrum modulation starts at the base station, i.e., the phase of the spreading code.

Fig. 19 shows a receiver of a mobile station for a CDMA digital cellular wireless communication system. The receiver includes an antenna 1, a receiver circuit 2 for performing amplification and fiequency conversion from RF (radio frequency) to IF 10 (intermediate frequency), a QPSK detector 3 for performing QPSK detection and outputting I, Q signals and an A/D converter 4 for converting baseband analog I, Q signals output from detector 3 to digital I, Q dater a despreading circuit 5 for applying despread processing to the I, Q data output by the A/D converter 4, a data demodulator 6 for performing synchronous detection, data discrimination and error correction, a 15 correlator 7 for performing a correlation operation in order to identify spread start timing (the phase of the received spreading code) and a timing decision unit 8 for identifying spread start timing (phase) from correlation value.

The correlator 7 pervious a correlation operation between a received spread-

spectrum data sequence and a reference spreading code sequence (a spreading code SO sequence identical with that on the side of the base station).

As shown in Fig. 20, a spreader 9 on a transmitting side executes spread processing and transmits a signal indicated by: X(t) = a(t) c(t)

Where a(t) represents trans=.i.A din and cat) a pit =udordom, number) sequence. The PN sequence cots is a spreading wde sequence of Ales and "O"s. The same code sequence (a code sequence of N chips) is repeated on a per-symbol basis, wherein 5 one symbol corresponds to one-bit of data.

The signal x(t) is received on the receiving side, where the correlator 7 calculates the correlation between the signal x(t) and a reference spreading code c(t-) and outputs a correlation value it(t) indicated by the following equation: it(t) -X(t) c(t-T) 10 =Ta(t) c(t) c(t-l),t=Tc,2Tc, N-Tc where T represents a code shin (phase difference) between the spreading code on the transmitting side and the reference spreading code of the correlator on the receiving side.

The integration interval is the duration of one symbol (the time period of N chips, which is equal to N Tc).

15 If "a(t) -- 1" holds in the above equation, the correlation value it(t) will indicate the auto correlation value of the PN sequence. If the PN sequence is an M sequence, it(t) - N (1 when normalized) is obtained as a maximum at = 0 and it(t) - 1/N holds at 0. In actuality, a(t) is unknown and may be " l " or Roll, However, by assuming for example that " 1 n = 1 and 0" l, and integrating the absolute value of a(t) c(t) chute), it(t) 20 - 1 is obtained at T = 0 and it(t) = l/ at 0.

Thus, by calculating correlation values while changing the phase of the reference spreading code c(t-T) one chip width Tc at a time and detecting the timing at which the correlation value exceeds a set level, it is possible to identify the spread start timing on

the trnslli++,ing side (die phase of the spreading code on the Transmitting side).

Accordingly, the timing decision unit 8 of Fig. 19 acquires the spread start timing (phase) based Up&O the timing at which the correlation value output by the coelto! 7 exceeds the set level and inputs this timing to the Respreader circuit 5.

5 A matched filter and a sliding correlator are available as the principal correlation detection techniques applied to l:)S-SS signals.

Fig. 21 shows a matched filter 71. The matched filter includes an N-chip shift register (sit -SN) 71a for successively shining the received spreadspectrum data sequence of the baseband (the output of the A/D converter in Fig. 19) at the chip frequency. Also 10 included is an N-chip shin register (cat -CN) 71b for storing the reference spreading code sequence, N-number of multiplying corresponding bits of the baseband spreadspectrum data sequence and reference spreading code sequence. An adder circuit 71d is farther included for adding the outputs of the multipliers and a PN generator 71 e for generating the PN sequence (the reference spreading code sequence).

15 The reference spreading code sequence is composed of N chips. The matched filter 71 outputs one correlation value it(t) per chip period Tc and then successively outputs a correlation value every time the phase of the baseband spread-spectrum data sequence changes by one chip width Tc. The matched filter thus outputs correlation values of N-number of different phases over the period of one symbol.

20 The timing decision unit 8 monitors the correlation value it(t) output by the matched filter 71, determines whether the correlation value has exceeded the set level and identifies the start of the spreading code sequence on the transmitting side (spread start timing) when the correlation value exceeds the set level.

Fig. 22 shows a sliding correlator 72, which i.,cludes a PN generator 79a for generating a PN sequence (reference spreading code sequence) The reference spreading code sequence is composed of N chips and is generated cyclically at the symbo! period T (= N X Tc). Further, multiplier 72b multiples the baseband spread-spe<;trum data 5 sequence (the received signal) by the reference spreading code sequence chip by chip and outputs the result.

An integrator 72c integrates N chips of the output of multiplier 72b and outputs the correlation value it(t) The integrator 72c includes an adder 73 for adding the output of the multiplier 72b and the current integrated value, and a delay circuit 74 for 10 outputting the integrated value from adder 73 upon delaying the value by one chip period.

The sliding correlator 72 outputs one correlation value it(t) in one symbol period (the period of N chips) and shifts the phase of the reference spreading code by one chip every symbol, thereby outputting correlation values of N-number of different phases over the period of N symbols (= N2.Tc).

15 The timing decision unit 8 monitors the correlation value it(t) output by the sliding correlator 72 to determine whether the correlation value has exceeded the set level. Further, the timing decision unit ships the phase of the reference spreading code if the correlation value is less than the set level and identifies the start of the spreading code sequence on the transmitting side when the correlation value exceeds the set level.

2C Thus, the phase of the spreading code on the transmitting side can be detected at a precision of within one chip by the matched filter or sliding correlator. (This is referred to as "synchronization acquisition". ) This is followed by perforating Respreading by

generating the spreading code sequence in sync with the detected phase to despri-d or.

the receiving side.

However, if no farther action is taken once synchrortion has been acquired, the synchronizing position will be lost owing to the effects of modulation and noise. I his 5 makes it necessary to exercise control in such a manner that the spreading code sequence on the receiving side will not develop a time shift with respect to a received signal for which synchronization has been acquired (This is referred to as Synchronization tracking".) A DLL (Delay Locked Loop) is known as such a synchronization tracking circuit. 10 Fig. 23 shows a DLL circuit, which includes a PN generator 9a that generates a first PN sequence (the reference spreading code) The PN generator 9a has nine delay circuits D 1 - D9 and an Ex-OR gate provided at the input of the fourth delay circuit. This configuration outputs a PN sequence of an M sequence in accordance with X9 + X4 + 1.

The first PN sequence A' is composed of N chips (- 29 = 512) and is generated cyclically lS at the symbol period T (= N X Tc).

delay circuit 9b delays the first PN sequence (reference spreading code) Al by one chip and outputs a second PUT sequence A2 A multiplier 9c multiplies, chip by chip, the first PA sequence Al output by the PN generator 9a and a received spread-spectrum data sequence B. A multiplier 9d multiplies, chip by chip, the second PN sequence A2 90 delayed by one chip and the received spread-spectrum data sequence B. Further, an adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the code output by the multiplier 9d. The output of the adder 9e is input to a low-pass filter 9f, the output whereof is applied to a voltage-controlled oscillator (VCO)

( 9s, which caries the clod frequency (chip frequency) based upon the output of the low-

pass filter.

The multiplier 9c and low-pass filter 9f Unction to calculate the correlation, between the first PN sequertce A and the received spreadspectrum data sequence B. If 5 the phase of the first PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained.

As shown in (a) of Fig. 24, a correlation value R() = I having the width of one chip is output every symbol. If the phase shiRs by the width of one chip or more, the correlation value R(T) becomes l/N.

10 The multiplier 9d and low-pass filter 9f Unction to calculate the correlation between the second PN sequence A: delayed by one chip width and the received spread spectrum data sequence B. If the phase of the second PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained and a correlation value Ret) is output' as shown in (b) of Fig. 24. If the phase shifts by the 15 width of one chip or more, the correlation value R() becomes 1/N. The adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the output of the multiplier 9d. As a result a signal having an S-curve characteristic shown in (c) of Fig. 24 with respect to a phase difference is output via the low-pass filter 9 On the basis of the output of the low-pass filter, the voltage-controlled oscillator 20 9g controls the clock frequency in such a manner that the phase difference becomes zero. For example, if the phase of the PN sequence (reference spreading code) leads that of the received spreading code, control is performed so as to make the phase difference zero by lowering the clock Frequency. If the phase of the PA sequence (reference

spreading coded lags be}lirld that ofthe r dived spreading code, cont,n! is pe,Ponned so as to make the phase difference zero by raising the clock frequency.

Thus, the phase of the spreading code sequence o., the rar.sm.t+.ing side is detected (synchronization acquisition) at a precision of within one chip by the correlator 5 (the matched filter of Fig. 21 or sliding correlator of Fig. 22), and then synchronization tracking is carried out by the DLL circuit.

Fig. 25 shows another example of a DLL circuit. In particular, Fig. 25a shows a DLL circuit having a configuration similar to Fig. 23. Fig. 25(b) shows a configuration of another DLL circuit obtained by modifying the DLL circuit of Fig. 25(a). Since 10 multiplication by the PN code and adding the results of multiplication are linear operations, the operations can be interchanged in terms of their order. Accordingly, the DLL circuit of Fig. 25a provides an equivalent function even if the adjacent first and second PN code sequences are multiplied by +l and -I by multipliers 9h, 9I, respectively.

Further, the products are added by an adder 9j and the received signal is multiplied by the 15 value of the surn, as shown in Fig. 2(b).

The time needed to detect a code phase, the scale of the circuitry and the power consumption associated with the matched filter are compared with those associated with the sliding correlator, the following results are obtained: (1) If the code length for obtaining correlation is N chips, the code phase 20 detection time required for initial synchronization, of reception will be N chips (=N Tc) in case of the matched filter and N chips (=N2 Tc) in case of the sliding correlator. In other words, the matched filter requires less time to detect the code phase, namely l./N of the time required in case of the sliding correlator.

( (2) The scale of the cf. cuing in a case where the correlc or is implemented by digital processing is understood from Figs. 21 and 22. Specifically, the matched filter requires two Shift registers each having a length equivalent to the number of taps (=), multipliers equivalent to the number of taps and one cumulative adder. The sliding 5 correlator, on the other hand, requires only one multiplier and one cumulative adder.

Therefore, the scale of the hardware of the matched filter is much greater than that of the sliding correlator.

(3) The power consumption of the circuitry is considered to be proportional to the product of the number of gates used and the operating frequency based on the assumption I O that CMOS LSI circuitry is used The operating frequency is the chip frequency or the over-sampling frequency of the chip in the case of both the matched filter and sliding correlator. Power consumption, therefore, is considered to be proportional to the scale of the circuitry. Accordingly, the power consumed by the matched filter is much greater than that by the sliding correlator.

Although the matched filter is advantageous in that code phase detection time is short, the scale of the circuitry is very large A problem that arises, therefore, is that a matched filter cannot be used in a mobile station, which requires low power consumption. The sliding correlator, on the other hand, has the advantage of small-scale circuitry. However, since code phase detection time is long, achieving initial 20 synchronization in the demodulation operation takes time which causes degradation of the system characteristics.

Further, with the conventional DLL circuit, the phase synchronization acquisition range (i.e. the lock range) is small, namely the width of one chip or -Tc/2 to Tc/2, as is

( evident from Fig. 24( c). However, a problem that arises is that synchronization tracking can no longer be performed if a phase shift in excess of one chip occurs.

SUMMARY OF THE INVENTION

5 Another embodiment of the present invention may provide a DLL circuit that makes it possible to enlarge the phase synchronization acquisition range.

According to the present invention, there is provided a delay locked loop circuit for maintaining phase synchronization between a received spreading code included in a spread-spectrum signal and a reference spreading code, comprising: 10 a reference spreading code generator for generating the reference spreading code; a combined code generator for generating a combined spreading code from the reference spreading code by weighting each of a plurality of phase-shifted occurrences of the reference spreading code with first weights, and combining the weighted phase shifted occurrences; 15 an arithmetic circuit for detecting a phase difference between the received spread code and the reference spread code using the combined spreading code; and a voltage controlled oscillator for controlling a phase of the reference spreading code on the basis of the phase difference; wherein the combined code generator makes positive, and successively reduces in 20 magnitude, the weights of a number n of reference spreading codes of small phase shift constituting a first half of a number 2n (where n is a positive integer) of reference spreading codes that have been successively shifted in phase, and makes negative, and successively increases in magnitude, the weights of n constituting a second half of the reference spreading codes that have been successively shifted in phase.

\ In a delay locked loop car cult that maintains phase synchroruzation between a received spreading code contained in a received spread-spectnm signal and a reference spreading code in -.. irnticn, a EN Hi rr> bet received spreading code and the reference spread code is detected using a combined 5 spreading cocle. The combined spreading code is obtained by weighting and combining a plurality of phase-chided reference spreading codes. Further, the phase of the reference spreading code is controlled based upon the phase difference.

Among 2n (where n is a positive integer) sequentially phase-shiRed reference spreading codes, the weight of the n reference spreading codes of the first half 10 in which the amount of phase shin is small is taken as being positive and the amount of weighting is successively reduced. The weight of the n reference spreading codes of the second half in which the amount of phase shin is large is taken as being negative and the amount of weighting is successively enlarged. Thereby generating a combined spreading code, where the phase difference is detected using this combined spreading code, and the 15 phase of the reference spreading code is controlled based upon the phase difference. By performing phase difference detection using the combined spreading code and controlling the phase of the reference spreading code based upon the phase difference, the phase synchronization acquisition range of the DLL is enlarged to a code length of N chips.

This enables initial synchroruzation to be achieved in a shorter period of time.

20 Further, a plurality of weights in which n is different are prepared. A combined spreading code is output initially using weights for which n is large and a combined spreading code is subsequently output using weights for which n is small whenever the phase difference between the first-mentioned combined spreading code and received _

spreading code fa!!s below a set value. rf Is rrmngenlePt is adopted, the loop gain of the DLL circuit with respect to the phase difference is raised while narrowing the lock r=,gc, thereby malting it possible to improve the characteristic of the DLL.

A desniticn Will now bgivEn ty way c candle with refenre ' the axnFn rang dredge.. in Which: Fig. 1 is a diagram showing a first correlator useful for understanding the present invention; Fig. 2 is a diagram illustrating the operation of the correlator of Fig. 1; Fig. 3 is a diagram showing a generalized configuration ofthe correlator of Fig. 1; 10 Fig. 4 is a diagram showing a second correlator useful for understanding the present invention; Fig. 5 is a diagram showing the operation of the correlator of Fig. 4; Fig. 6 is the output of a correlation detector; Fig. 7 is a diagram illustrating a third correlator useful for 15 understanding the present invention; Fig. 8 is a diagram showing the correlator of Fig. 8; Fig. 9 is a diagram illustrating the principle of a fourth correlator useful for understanding the present invention; 20 Fig. 10 is a diagram shoving the Much correlation; Fig. 1 1 is a diagram showing a ALL c ircuit useful for understanding the present invention; 1 2

Fig. 12 is an output waveform. for the DLL c:" cu;.t of Fig 1 1; Fig 13 isa filter output characteristic for the DLL circuit of Fig 11; rig 14 is a diagram shoving a generalized configuration clothe I:)LL c:r"it of Fig. 11; 5 Fig 15 is a diagram showing the S curve of the DLL circuit ot big 14; Fig 16 is a diagram showing a table look-up DLL circuit; Fig 17 is a diagram illustrating the operation of the DLL circuit according to the yet invention, Fig 18 is a dagran showing an emooamen OI LilO 1 11 quit v. ding to the present invention; Fig 19 is a diagram showin, Fig 20 is a diagram illustrating decision of spread start timid D, _ _ _, Fig 21 is a diagram showing a matched filter; Fig 22 is a diagram showing a sliding correlator, 15 Fig 23 is a diagram showing a conventional DLL circuit; Fig 24 is a diagram illustrating the S-curve of a DLL circ_, _ _ Fig 25 is a diagram showing another conventional DLL circuit Before describing an embodiment of the present invention, various correlator circuits and related DLL circuit will first b? described as background.

20 (A) Correlator (a) First correlator 1 3

f; Fig.lshowsafir.correlator, useful for understanding the invention.

The correlator of Fig. 1 calculates the correlation between a received spreading code contained in a received spread-spectrum signal and a ererence spreading code.

Reference numeral 21 designates a PN sequence generator for cyclically generating a PN sequence (a reference spreading code) as an M sequence. The PN sequence has a code length of N chips, where the chip width is Tc. The code period (N Tc) of the PA sequence is equal to one symbol period (one bit interval) T. A combined code generator 22 weights and combines a plurality of (two in the illustration) of phase-shiRed reference spreading code sequences, namely first and second reference 10 spreading code sequences Al and A:. An arithmetic circuit 23 calculates the correlation between a combined spreading code A and a received spre ding code B. A phase detection circuit 24 detects the phase difference between the received spreading code and the reference spreading code (namely the phase of the received spreading code) on the basis of the output level of the arithmetic circuit 15 The combined code generator 22 includes a phase shift circuit 22a for outputting the first reference spreading code Al C(t), C:(t)7 -, CN(t) and the second spreading code A' C(t+n-Tc), Cz(t+n Tc),, CN(t+n Tc. The first reference spreading code Al has not been delayed, while the second reference spreading code A2 has been delayed by a time equivalent to n chips (A Tc). The combined code generator includes a weighting 20 circuit 22b for weighting the first and second reference spreading codes Al, A2 by weights We, W2 (WOW:), respectively, and a combining circuit 22c for combining the weighted first and second reference spreading codes to output the combined spreading code. It should be noted that n = N/2.

The arithmetic circuit 23 has a r,ultiplicatioTi -arctic Ma that multiplies the received spreading code B by the combined spreading code A, one chip at a time at the chip period. Further, an integrator 23b adds the results of multiplication N fumes and then outputs the result. The integrator 23b has an adder SUM that adds the output of the 5 multiplication circuit 23a and the currently prevailing integrated value. A delay line DEL then outputs the integrated value, which is the output of the adder, upon delaying the integrated value by one chip width Tc.

The correlator of Fig. 1 is obtained by providing the conventional sliding integrator described in regard to Fig. 22 with the phase shifter 22a, weighting unit 10 22b and combiner 22c. If the second reference spreading code A2 is assumed to be O. then the correlator becomes a sliding correlator similar to that of the prior art.

If the phases of the first reference spreading code Al and received spreading code B match, the arithmetic circuit 23 outputs the signal shown in (a) of Fig. 2. After integration has been perforT.ned N times, the arithmetic circuit 23 outputs a correlation 15 value of level We (= N We). Similarly, if the first reference spreading code A, is assumed to be O and, the phases of the second reference spreading code As and received spreading code B match, the arithmetic circuit 23 outputs the signal shown in (b) of Fig. 2. Aver integration has been performed times, the arithmetic circuit 23 outputs a correlation value of level W2 (= N-W2).

20 In actuality, the first and second reference spreading codes Al, A2 are not 0.; However, the phases of the first and second references spreading codes Al, Az do not coincide with the phase of the received spreading code B simultaneously. Accordingly, the phase detection circuit 24 monitors the correlation level (the correlation value of one 1 5

f pen of-the reference spreading code) that prevails after N additions and (1) decides that the phase of the received spreading code matches the phase of the first reference spreading code Al if the correlation level is We: Further, the phase detec;tior. cf. cult 24 (2) decides that the phase of the received spreading code matches the phase of the second reference spreading code A2 if the correlation level is W2 and (3) decides that the phase of the received spreading code does not match We phases of the first and second reference spreading codes if the correlation level is zero.

In case of (3) described above, the phase detection circuit 24 delays, by one chip, the phase of the next period of the PN sequence output by the PN sequence generator 21.

10 The phase detection circuit 24 then repeats the operation described above. If the correlation level becomes We while the PN sequence generator 21 is outputting a reference spreading code having a phase delayed by m chips, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code in m-Tc. If the correlation level becomes W2, then the phase 15 detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is (mn)-Tc.

If the correlation is calculated between the received spreading code B and the combined spreading code A, which is obtained by combining two reference spreading codes Al, A: delayed in phase as set forth above, the time needed for phase detection is 20 N2/2 chips (= N2 Tc/2). Therefore, the time required for detection is shortened to half that of the conventional sliding correlator.

1 6

1' ' ')

(D) Generality cr^guration The arrangement shown in Fig. 1 relates to a case where two reference spreading codes Al, A2 delayed in phase are combined upon being weighted by weights we, we, respectively. Thus, the correlation between the combined spreading code and reference spreading code is calculated. If an arrangement is adopted in which this approach is expanded to combine M-number of phaseelayed reference spreading codes Al AM weighted by weight we -WM, respectively, to calculate the correlation between the combined spreading code and the received spreading code, then the time needed to detect phase can be shortened to N2 TclM.

10 IN view of the above, Fig. 3 shows a generalized configuration of the correlator of Fig. 1, in which components identical with those of Fig. I are designated by like reference characters. Shovrn here are the PN sequence generator 21, the combined code generator 22, the arithmetic circuit 23, the phase detection circuit 24 and an oscillator 25 for outputting a clock having the chip frequency.

15 The combined code generator 22 includes the phase shin circuit 22a, the weighting circuit 22b and the combining circuit 22c. The phase shiftcircuit 22a has delay elements Do - DM each of which successively delays the PN sequence, which is the reference spreading code, by (N Tc/). The weighting circuit 22b includes multiplication circuits MP -}V{PM for weighting the 1 through Mth reference spreading 20 codes Al - Act, which are output by the phase shirt circuit, by weights we - WM (Wt:> W2 > À-- > WM), respectively. The combining circuit 22c combines the weighted 1 - Mth reference codes and outputs the combined spreading code A 1 7

( The &iuhl.etic c:ucuit 23 includes Me multiplication circuit 23a for multiplying the received spreading code B and the combined spreading code A at the chip period.

Further, the integrator 23b adds the results of multiplica6orl N tines and outputs the result. 5 Lyle phase detection circuit 24 monitors the correlation level (the correlation value of one period of the reference spreading code) that prevails after N additions. Further, the phase detection circuit 24 (1) decides that the phase ofthe received spreading code matches the phase of the first reference spreading code Al if the correlation level is We, (2) decides that the phase of the received spreading code matches the phase of the second 10 reference spreading code As if the correlation level is W2; ---, (3) decides that the phase of the received spreading code matches the phase of the Mth reference spreading code AM if the correlation level is WM and (4) decides that the phase of the received spreading code does not match the phases of the 1 through Mth reference code sequences if the correlation level is zero.

15 En case of (4) above, the phase detection circuit 24 delays, by one chip width Tc, the phase of the next period of the reference spreading code (PN sequence) output by the PN sequence generator 21. The phase detection circuit 24 then repeats the operation described above. If the correlation level becomes Wit while the PN sequence generator 21 is outputting a reference spreading code (PN sequence) having a phase delayed by m 20 chips, the phase detection circuit 24 judges that the phase dillerence between the received spreading code and the reference spreading code is m Tc If the correlation level becomes W2, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is [m+(NlM)] Tc. Further, if 1 8

the correlation level becomes W3, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is [m+(2N'M)] Tc; If the correlation level becomes WM, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is [m+(M-l)] À N/M1 Tc.

If the correlation is calculated between the received spreading code B and the combined spreading code A, which is obtained by combining M- number of phase-

delayed reference spreading codes Al - AM as set forth above, the time needed for phase detection is N2 Tc/hI. Thus, the time recluired for detection is shortened to 1/M that of 10 the conventional sliding correlator.

If C represents the spreading code, N the code length and M the number of codes combined, then a linear combined code S will be given by the following equation: S=Z Ci+) i= 1-N (1) 15 where rej represents the weighting coefficient of a jth code to be added and iG represents the amount of phase shift of the josh code to be added. Ln a case where correlation detection is performed using Si in Equation (i) as the combined spreading code, a correlation output value proportional to toj is obtained with respect to the code phase of i(j). As a result, a correlation output with regard to M-number of code phases 20 Awn be obtained by a single correlation detection operation (c) Second correlator Fig. 4 shows a second correlator useful for understanding the invention, in which components identical with those of Fig. 3 1 9

are designated by Like reference chara - Hers. TO this arrangement, two correlators in accordance with Fig. 3 are provided and a phase difference 6 between the received spreading code and reference spreading code (the phase of the received spreading code) is detected using the output of each correlator.

5 Reference numerals 21, 21' designate identical first and second PN sequence generators for cyclically generating PN sequences (reference spreading codes) as M sequences Each PN sequence has a code length of N chips, where the chip width is Tc.

The code period (N Tc) of each PN sequence is equal to one symbol period T. Combined code generators 22, 22' each weight and combine a plurality 1 in the illustration) of 10 phase-chided reference spreading code sequences Al - AM.

Further, first and second arithmetic circuits 23, 23' calculate the correlations between combined spreading code A, A', respectively, and the received spreading code B. Oscillators 25, 25' output clocks having the chip frequency. A third arithmetic circuit 26 calculates the phase difference using correlation values output by the first and second 15 arithmetic circuits 23, 23'. The first and second combined code generators 22, 22' include phase shin circuits 22a7 29a', weighting circuits 22b, 22b' and combining circuits 22c, 22c', respectively.

The phase shift circuit 22a of the first combined code generator 22 has delay elements Do - DO each of which successively delays the PN sequence by (N TclM). The 2Q weighting circuit 22b includes multiplication circuits MA - MPM for weighting the 1 Mth reference spreading codes as Al - AM, which are output by the phase shit circuit, by the weights wit - WE, respectively. The combining circuit 22c combines the weighted 1 Mth reference codes and outputs the combined spreading code A The weights we WM

ó ' are obtained by successively sampling one r_r; - (= N TO of a cosi.n. e-waV. e Sims! at the units (N-Tc/M) at which the phase of the reference spreading code is shifted. Fig, 5(a) illustrates the weights in a case where sampling is carried out at the period of N T c/M, ex., at the chip period Tc, where M = N holds.

5 The phase shift circuit 22a' of the second combined code generator 22' has delay elements DI - DM each of which successively delays the PN sequence by (N.Tc/M). The weighting circuit 22b' has the multiplication circuits MA - MPMfor weighting the 1 through Mth reference spreading codes Al - AM, which are output by the phase shift circuit, by weights we' we', respectively. The combining circuit 22c' combines the 10 weighted lo through Mth reference codes and outputs the combined spreading code A'.

The weights we' - WM' are obtained by successively sampling one period (= N Tc) of a sine-wave signal at the units (N-Tc/M) at which the reference spreading code is shifted.

Fig. 5(b) illustrates the weights in a case where sampling is carried out at the period of N Tc/M, ex., the sampling is carried out at the chip period Tc' where M = N holds.

15 In a case where M = N holds, the first combined code generator 22 outputs a combined spreading code U(i) indicated by the following equation: o(i) = EPN(i+j) x cos (2?j/N) (2) where j = -N/2 - N/2 holds.

The second combined code generator 22' outputs a combined spreading code 20 Q(i) indicated by the following equation: Q (i) = I;PN(i+j) x sin (77rj/N) where j = -N/2 - N/2 holds.

i The first arithmetic circuit 23 multiplies the combined spreading code v: (i) by the received spreading code. Further, the first arithmetic circuit 23 cumulatively adds (integrates) the results of multiplication over one period (= N Tc) of the reference spreading code. Similarly, the second arithmetic circuit 23' multiplies the combined 5 spreading code Phi) by the received spreading code, and cumulatively adds (integrates) the results of multiplication over one period of the reference spreading code.

Fig. 6 illustrates the output characteristics of the first and second arithmetic circuits 23, 23' in a case where the received spreading code B is multiplied by the combined spreading codes A, A', where the results are cumulatively added (integrated) 10 over one period of the reference spreading code. From this cos, -sin characteristics are obtained with respect to all phases (N = -256 to 256) of the code. As a result, a third arithmetic circuit 26 uniquely decides and outputs the phase difference (the phase of the reference spreading code) between the received spreading code and reference spreading code from the results vie, Do of integration, where is given by the following equation: 15 0=-tan-ivp/v' (4) In other words, the code phase is obtained by integrating over one period (=N Tc) of the reference spreading code. Thus, the amount of time needed is significantly shortened in comparison with the conventional sliding correlator, which requires a length of time equivalent to N2 Tc.

20 In addition, the scale of the circuitry is much smaller than that of a matched filter It should be noted that if delayed waves are present, it may be necessary to adopt an arrangement in which the vicinity of the obtained phase difference is searched using a sliding corTelator IN this case, however, the time needed for synchronization can be

I' 1 shortened in comparison with the conventions! sliding correltor, which sequentially scans all code phases. I The PA sequence generators 91, 21' of Fig. 4 can,be combined into a single common PN generator. The same is true for the phase shift circuits 22a, 22a' and 5 oscillators 25, 25'.

(d) Third correlator In mobile communications, multiple paths exist. As shown in (a) of Fig. 7,] transmitted signals from a base station BS arrive at a mobile station MS successively via multipaths MPO, MP1, MP2 with delay times Ti, 12, as illustrated in O of Fig. 7. These 10 multipath signals constitute noise in phase detection and are obstacles to accurate i detection of code phase in the second cca. Multipath signals, however, can be dispersed within a certain range of phases.

Accordingly, in a third c, the phase difference is detected roughly in units of (7/2) using 4, for example, as M of the second rar. This enables 15 phase areas R1- R4 [Fig. 7( c)] in which the true phase difference resides are discriminated, and the interiors ofthe phase areas are searched sequentially by a sliding correlator to obtain the phase difference for which the maximum correlation is obtained.

It this arrangement is adopted, phase difference can be detected accurately even if multipaths exist.

20 Fig. shows the third correlator useful for understanding the invention, in which components identical with those of the second c=x are designated by like reference characters. The third Wren differs from of Fig. 4 in that (1! a sliding correlator 31 is provided on the output side of the third

j a.+hnetic circuit 25; (2) a phase detection circuit 32 is provided for detecting the phase for which the correlation value output by the sliding correlator is maximized; and (3) :=4 is used for the correlator.

The phase shift circuit 22a of the first combined code generator 22 has delay 5 elements Do - D3 each of which successively delays the PN sequence by (N Tc/4). The weighting circuit 22b has multiplication circuits MA MP4 for weighting the first through fourth reference spreading codes al for weighting the first through fourth reference spreading codes Al - Ad, which are output by the phase shift circuits by the weights we - W4, respectively. The combining circuit 22c combines the weighted first 10 through fourth reference codes and outputs the combined spreading code A. The weights WE - W4 are obtained by successively sampling one period (- N Tc) of a cosine-wave signal at the units (N Tc/4) at which the phase of the reference spreading code is shifted.

Here we = cosO, we, - cost), W3 - cos(2/2), W4 - cos(3/2) holds.

The phase shift circuit 22a' of the first combined code generator 22' has delay 15 elements Do - D3 each of which successively delays the PN sequence by (N Tc/4). The weighting circuit 22b' has multiplication circuits MP - MP4 for weighting the first through fourth reference spreading codes Al - A4, which are output by the phase shift circuit, by the weights we'' - W4', respectively. The combining circuit 22c' combines the weighted first through fourth reference codes and outputs the combined spreading code 20 A'. The weights we' - W4' are obtained by successively sampling one period (=N Tc) of a sine-wave signal at the units (N Tc/4) at which the phase of the reference spreading code is shifted. Here wit' = sine, w2' = sink), W3' = sin(212), W4' = sin(3/2) holds.

i ne firm. combined code generator 22 outputs a combined sprqdir.g code phi) indicated by the following equation: SKI) = Phiti+(N/);) x cosj (12) (S) where j = 0 - 3.

5 oQ(I) = TPN(i+lN/4)j) x sinj(7c/Z) (6) where j = 0 - 3.

The first arithmetic circuit 23 multiplies the combined spreading code (i) by the received spreading code and cumulatively adds (integrates) the results of multiplication 10 over one period (=N Tc) of the reference spreading code. The second arithmetic circuit 23' multiplies the combined spreading code (i) and the received spreading code and cumulatively adds (integrates) the results of multiplication over one period of the reference spreading code.

The third arithmetic circuit 26 obtains the phase difference (code phase) from 15 lo, vQ in accordance with Equation (4). As a result, in which of the M-number of areas a response resides is specified, where the IvInumber of areas are obtained by dividing all N code phases into M (= 4) areas.

The sliding correlator 31 determines that the true code phase exists in an area Ri in which there is a response. The sliding correlator 31 then performs a search 20 sequentially with respect to the phase of N/M-number of chips of the area Ri in a manner similar to that of the prior art. More specifically, the sliding correlator 31 generates the

reference spreading code at the initial phase of the area Ri, calculates the correlation between this reference spreading code and the receiving spreading code, outputs one

correlation value it(t) following one symbo; period (--N Tc) and shifts the phase of the reference spreading code by chip width. The sliding correlator 31 then outputs correlation values of N/M-number of different phases and, the phase detection circuit 32 finds the code phase for which the correlation value it(t) output by the sliding correlator 5 31 is maximized.

By virtue of the operation described above the scanning of all code phases of N chips of one symbol can be completed in a time of (N2/M+N) Tc in accordance with the third ar. Thus, the amount of time needed is shortened greatly in comparison with the conventional sliding correlator, which requires a length of time equivalent to 10 N2Tc (e) Fourth correlator In the first air cry Fig. 3, the arithmetic circuit 23 (1) outputs a correlation value of level We if the phase of the received spreading code B matches the phase of the first reference spreading code An Further, the arithmetic unit 23 (2) outputs i 15 a correlation value of level W2 if the phase of the received spreading code B matches the phase of the second reference spreading code A2 and (3) outputs a correlation value of level WM if the phase of the received spreading code B matches the phase of an Mth reference spreading code AM.

Accordingly, when a phase area is divided into two portions, all weights we - WM 20 of reference spreading codes Al - AM for which the amounts of phase shift reside in the first phase area are made w (where w is an integer). Thus, all the weights we,+ - WM of the reference spreading codes A' -: - AM for which the amounts of phase shift reside in the second phase area are made -w (Fig. 9(a)). When this arrangement is adopted, the

( ari-L,.mec C:l1 "i. 23 o,u+.p Us a -^rrelqti^- value of weight W if tale phase of the received spreading code B matches the phase of any one of the reference spreading codes Al - AM d outputs a cot I elation Sue o+ weight -W if the phase of the received spreading code B matches the phase of any one of the reference spreading codes A, - -

5 AM. As a result, the phase detection circuit 24 is capable of recognizing the phase area to which the code phase belongs depending upon whether the correlation value is +W or -W. The phase area to which the code phase belongs is then divided further into two portions, and similar weighting [Fig 9(b)] and discrimination are camed out to narrow 10 down the phase area. If these weighting and discrimination operations are repeated (Figs.

9(c), (d)), the phase difference between the received spreading code and reference spreading code (namely the phase of the received spreading code) can eventually be detected. For example, as indicated by the hatched portions in Figs 9(a) through (d), the area in which the code phase actually resides in narrowed successively and matching of 15 the phase of the received spreading code with the phase of the second reference spreading code can eventually be recognized If the relation M = N holds, the method described above makes it possible to complete the scanning of all code phases of N chips by performing correlation detection logon times.

Fig. 10 shows a fourth air useful far inseam in 20 which components identical with those of the first Errs shown in Fig. 3 are designated by like reference characters. This circuit includes the PN sequence generator 21, the combined code generator 22, the arithmetic circuit 23, the phase detection circuit 24 and the oscillator 25 for outputting a clock having the chip frequency.

The combined code generator 22 includes the phase shin circuit 22a, the weighting circuit 22b, the combining circuit 29c and a weight selector 22d. The phase sniff circuit cza has delay elements Do - DM for successively delaying the PN sequence, which is the reference spreading code, (N Tc/M) at a time. The weighting circuit 22b has 5 multiplication circuits MA - ARM for weighting the 1 - Mth reference spreading codes A! AM, which are output by the phase shift circuit, by weights we - WM, respectively.

The combining circuit 22c combines the weighted 1 - Mth reference spreading codes and outputs the combined spreading code A. The weight selector 22d is provided with the following K sets of weight patterns 10 in advance: WII, W2I, W31'... WMI'

W12, W2z, W32,... WM2, W1K, W2'W3K, -- W,

15 and changes weight patterns successively whenever identification of which of the two divided phase areas a code phase belongs to is completed, thereby eventually identifying the code phase. If N= 512 and M = N holds, then K= 9 and nine sets of weight patterns are provided. As shown in Fig. 9(a), the first weight pattern is one in which the weights we - wm of m (=M12) reference spreading codes are made positive and 20 constitute the first half of the successively phase-shifted M (= N) reference spreading codes. The weights we+ - WM of M/2 reference spreading codes are made negative and constitute the second half of the successively phase-shifted M (= N) reference spreading codes. The second and third weight patterns are the patterns shown in Figs. 9O and

9tc), respectively, and the last or ninth weight pattern is one in which + w and -w alternate. The arithmetic circuit 23 includes the multiplication circuit 23a for ruru'tiplying the received spreading code B. by the combined spreading code A and the integrator 23b 5 for adding the results of multiplication N times and outputting the resulting correlation value. The phase detection circuit 24 monitors the correlation value (the correlation: value of one period of the reference spreading code) that prevails after N additions, discriminates the area to which the code phase belongs depending upon whether the correlation value is +W or -W. and causes the weight selector 22d to select the weights of 10 the next group.

Initially selectors SELF - SEIZE ofthe weight selector 22d select the weight pattern of Fig. 9(a) and input the pattern to the multipliers laps - MPM, respectively. The arithmetic circuit 23 outputs a correlation value of +W if the code phase is present in the initial phase area Rr, [Fig. 9(a)] and outputs a correlation value of -W if the code phase is 15 present in the other phase area Rib. The phase detection circuit 24 identifies the phase area by the sign of the correlation value and then instructs the weight selector 22d to select the next weight pattern.

The weight selector 22d responds by selecting the weight pattern of Fig. 9(b) and i inputs the pattern to the multipliers MA - MPM of the weighting circuit 22b. The 20 arithmetic circuit 23 outputs the correlation value of +W if the phase difference resides in: phase area Rat or phase area R23, and outputs the correlation value of -W if the phase difference resides in phase are Ret or phase area Rae. When the phase detection circuit 24 identifies the phase area by sign of the correlation value, it instructs the weight selector;

i. Ad to select the nest, weight pane.... T.."s oration is pe;fo reputedly to fi"Aa!!y specify the area to which the code phase belongs.

(B) DLL circuit I (a) Fig. 11 shows a red chit useful for using 5 invention. Reference numeral 51 designates a PN sequence generator for cyclically generating a PN sequence (a reference spreading code) as an M sequence. The PN: sequence has a code length of N chips, where the chip width is Tc. The code period (N Tc) of the PN sequence is equal to one symbol period T. A combined code generator 57 weights and combines a plurality (four) of phase 10 shined reference spreading code sequences Al - A4. A multiplier 53 multiplies the combined spreading code A and the received spreading code B. chip by chip. A filter 54 subjects the output of the multiplier to filtering processing. A voltage-controlled oscillator (VCO) 55 is capable of varying the clock frequency (chip frequency) based upon the output of the filter to synchronize the reference spreading code with the received 15 spreading code.

The combined code generator 52 includes a phase shier circuit 52a, a weighting circuit 52b and a combiner 52c. The phase shin circuit 52a has delay elements Do - D each of which successively delays the PN sequence that is the reference spreading code i by one chip width Tc. The weighting circuit 52b includes multiplication circuits MP 20 MP4 tor weighting the first - fourth reference spreading codes Al - A4, which we output: by the phase shim circuit, by weights we - W4 (w: = 1.0, w2=0.5, W3 = -0 5, W4 = -1.0), respectively.

Al I he combiner 52c collarbones the weighted first-fourth reference spreading codes and outputs the combined spreading code A The multiplier 53 and filter 54 calculate simultaneously the correlations between the reference spreading codes Al - A4 End the received spreading code B. The results of these calculations are then combined and 5 output.

More specifically, the multiplier 53 and filter 54 calculate (1) the correlation between the first reference spreading code Al and the received spreading code, (2) the correlation between the second reference spreading code A2 and the received spreading code, (3) the correlation between the third reference spreading code As and the received 10 spreading code, and (4) the correlation between the fourth reference spreading code A4 and the received spreading code. These calculations are then combined and output.

Accordingly, if the phase of the received spreading code B matches the phases of each of the first - fourth reference spreading codes A, - A4, the filter 54 outputs the correlation values Cab - C4 at the phase illustrated in Fig. 12 and therefore outputs a signal 15 having the overall S-curve characteristic shown in Fig. 13. The phase synchronization acquisition range (lock range) is enlarged to the width of three chips, namely from -3Tc12 to 3Tc/2, as evident from the S-curve The voltage-controlled oscillator 55 controls the clock frequency based upon the i output of the low-pass filter in such a manner that the phase difference T will become 20 zero. For example, if the phase of the reference spreading code leads that of the received spreading code, control is performed so as to make the phase difference T zero by lowering the clock frequency. If the phase of the reference spreading code lags behind

l that of the received spreading ode, control is PerfCeJ PC to make the phase difference zero by raising the clocl: frequency In accordance with She DLL cu-c-ui of Fig. 1 l, Me IGCI- range can be enlarged threefold in comparison with the conventional DLL circuit.

5 (b) Generalized configuration The DLL circuit described above relates to a case where four reference spreading codes Al - At delayed in phase are combined upon being weighted by weights wit - we, respectively, and the correlation between the connbined spreading code and the received spreading code is calculated. If an arrangement is 10 adopted in which this approach is expanded to combine M-number of phase-delayed reference spreading codes Al - AM upon weighting them by weights wit - WM, respectively, and to calculate the correlation between the combined spreading code and the received spreading code, then the lock range can be enlarged by a factor of (M-1.

Fig 14 is a diagram showing the generalized configuration of the DLL circuit 15 c'E Eig. 11, in which components identical with those ofthe chit of Fig. 11 are designated by like reference characters. The generalized configuration includes the PN sequence generator 51, the combined code generator 52, the multiplier 53, the low-pass filter 54 and the oscillator 55 for outputting i the chip-equency clock.

20 The combined code generator 52 includes the phase ship. circuit 52a, the weighting circuit 52b and the combiner 52c. The phase shin circuit 52a includes M number of delay elements Do - DO each of which successively delays the PN sequence (the reference spreading code) by the chip width Tc. The weighting circuit 52b includes;

multiplication circuits MA - MA for weighting the I - Mth reference spreading codes AI - AM. which are output by the phase shin circuit, by weights we - WM, respectively.

The combining circuit 52c then combines the weighted 1 - Mth reference codes and outputs the combined spreading code A. The weights we - WM are determined in the following manner. The weights of M/2-number of reference spreading codes constituting the first half of the M-number of reference spreading codes successively shined in phase are made positive and successively smaller. The weights of M/2-number of reference spreading codes constituting the second half of the M-number of reference spreading codes are made 10 negative and successively larger. For example, when M = N holds, the following weights are adopted. we = N/2, w2 =(112)- l, W3 = (N/2)-2,... won = 1, warm = -1, wound = -2, WN = -(N/2)

If weighting is performed in this manner, the combined code generator 52 will output a combined reference code Fiji), which is indicated by the following equation, at a 15 code phase of i Tc: Fiji) - I::j x PN(ij). (7) where j = -N/2 to N/2.

The multiplier 53 multiplies the combined reference code Fiji) and the received spreading code B. chip by chip. The filter 54 subjects the output of the multiplier to a 20 filtering process. The voltage- controlled oscillator 55 then controls the clock frequency based upon the output of the low-pass filter in such a manner that the phase difference becomes zero. If the reference spreading code has nine PN phases (where N = 512), an S-curve characteristic shown in Fig. 15 is obtained in the DLL circuit. The input code

if. phase (phase d Inference) is plotted along The honzoriLal axis in Fig. 15, and the normalized output level is plotted along the vertical axis. In accordance with the DLL circuit of Fig. id, an qutput characteristic having a linear slope can be obtained for all phases of the code and thus initial synchronization acquisition is unnecessary.

5 Fig. 16 shows a table look-up DLL circuit. Reference numeral 56 designates a combined code generator, which has a counter and a ROM tablethat outputs the combined reference code Hi) indicated by Equation (7) The multiplier 53 multiplies the combined reference code A = fti) and the received spreading code B. chip by chip.

Reference numeral 54 designates the filter and 55 the voltage-controlled oscillator 10 (VCO).

The combined code generator 56 has a ROM table 56a for storing the combined spreading code of Equation (7), and a counter 56b for generating a table address. The phase of the received spreading code and the phase of the reference spreading code are made to coincide by controlling the clock of the counter 56b by the voltage-controlled 15 oscillator 55. The content of the ROM table S6a can be configured in various forms depending upon the weighting method. The S-curve characteristic in a case where a table in accordance with Equation (7) is used is as shown in Fig. 15, as described above.

(c) of DLL circuit An advantage of the DLL circuit according to the art in Fig. 2G 14 is that the lock range is enlarged if M is large. However, if the slope of the S-curve becomes more gentle, loop gain declines and achieving coincidence between the phases of the received spreading code and reference spreading code takes more time. Moreover, phase tends to fluctuate in response to external disturbances On the other hand, if it is

1 ' i made smaller, then the lock range is recluced. However, 'he 510pe Or the S-curve becomes extremely steep, loop gain can be enlarged and fluctuation of the phase in response to external disturbances diminishes.

In the invention (see Fig.17(a)) M is enlarged initially and a 5 synchronizing operation is perforr,ned. Thus, when a certain degree of synchronization has been achieved, the output level of the correlator declines. The output level is discriminated, M is reduced and a changeover is made to a linear combined code set including narrower range of phases, as shown in (b) of Fig. 17. If control is performed in similar fashion so as to gradually reduce M (Fig. 17(c))7 synchronization can be achieved i 10 earlier and the slope of the S-curve with respect to phase is made much steeper. This makes it possible to raise the loop gain and to improve the characteristic of the DLL circuit. Fig. 18 shows an embodiment of the DLL circuit according to the present invention in which components identical with those shown in Fig. 14 are designated by: 15 like reference characters. Reference numeral51 designates the PN generator. Combined code generators 52 - 52N generate combined spreading codes in a case where M = 2, M -

4,..., M = N hold, respectively. The multiplier 53 multiplies the combined reference code A and the received spreading code B chip by chip.

Reference numeral 54 denotes the filter and 55 the voltage-controlled oscillator.

20 Reference numeral 61 designates a state detector for detecting a state in which the output of the low-pass filter falls below a set level when a certain degree of synchronization has been achieved. Further, reference numeral 62 designates a selector for selecting and outputting the next combined spreading code having a small M.

(, l The configuration of the combined code generator 52N is obtained when M in Fig 14 is made equal to N. The weights w: - WN are decided in a manner similar to that of Fig. 4 T 1 part wular' the weights of N./2number of reference spreading codes of a small phase difference constituting the first half of the N-number of reference spreading codes successively shined in phase are made positive and successively smaller. The weights of N/2-number of reference spreading codes of large phase difference constituting the second half of the N-number of reference spreading codes are made negative and successively larger.

The combined code generator 52z has a configuration identical with that of the 10 combined code generator of the [ALL circuit shown in Fig. 11, and the combined code generator 52, has a configuration identical with that of the conventional combined code generator, shown in Fig. 25(b), for which the lock range is one chip width Tc.

Initially, the selector 62 outputs a combined reference code, which is produced by the combined code generator 52? for which M = N holds, and performs a synchronizing 15 operation. The multiplier 53 multiplies the combined spreading code and the received spreading code B. chip by chip. The filter 54 subjects the output of the correlator to a filtering process and outputs the result. The voltage-controlled oscillator 55 controls the clock frequency based upon the output of the low-pass filter in such a manner that the phase difference becomes zero.

20 As a result, when a certain degree of synchronization is achieved and the filter output decreases, the state detector 61 instructs the selector 62 to select the next combined spreading code. In response, the selector 62 outputs a combined spreading code for which M = NI2 holds and performs a synchronizing operation. If control is

subsequently performed in similar fashion in such a manner that M becomes gradually smaller, synchronization to within one chip will eventually be obtained.

Though the present invention has been described referring to an embodiment thereof, the present invention can be modified in various ways in accordance with the 5 gist thereof set forth in the claims and covers these modifications.

In accordance with the present invention, phase is detected using a combined spreading code. The combined spreading code is obtained by weighting and combining a plurality of reference spreading codes that have been shifted in phase. Further, the phase of the reference spreading code is controlled using the results of phase detection.

10 As a result, the phase synchronization acquisition range of a DLL can be enlarged to a code length of N chips and initial synchronization is achieved more quickly.

Further, in accordance with the present invention, the output level of the correlator declines when the DLL has achieved a certain degree of synchronization.

This is discriminated and a changeover is made to the combined spreading set to a 15 narrower range of phases. As a result, the slope of the Scurve with respect to phase is made much steeper. This makes it possible to raise the loop gain of the DLL and to improve the phase control characteristic.

Claims

1. A delay locked loop circuit for maintaining phase synchronization between a received spreading code included in a spread-spectrum signal and a reference 5 spreading code, comprising: a reference spreading code generator for generating the reference spreading code; a combined code generator for generating a combined spreading code from the reference spreading code by weighting each of a plurality of phase-shifted occurrences 10 of the reference spreading code with first weights, and combining the weighted phase shifted occurrences; an arithmetic circuit for detecting a phase difference between the received spread code and the reference spread cotle using the combined spreading code; and a voltage controlled oscillator for controlling a phase of the reference spreading 15 code on the basis of the phase difference; wherein the combined code generator makes positive, and successively reduces in magnitude, the weights of a number n of reference spreading codes of small phase shift constituting a first half of a number 2n (where n is a positive integer) of reference spreading codes that have been successively shifted in phase, and makes negative, and 20 successively increases in magnitude, the weights of n constituting a second half of the reference spreading codes that have been successively shifted in phase.

2. The delay locked loop circuit of claim 1, wherein the arithmetic means includes a multiplier for multiplying the received spreading code by the combined 25 spreading code, and a filter for filtering an output of the multiplier.

3. The delay locked loop circuit of claim 2, responsive to a plurality of sets of weights, each set of weights com.pr.sing a different number n of 'eights, wherein the delay locked loop circuit outputs the combined spreading code using a set of weights for 30 which n is large initially, and subsequently outputs a combined spreading code using a set of weights for which n is smaller when the phase difference obtained using the larger set of weights falls below a predetermined value.