GB2391779A

GB2391779A - A correlator uses two combined spreading codes, each based on a local PN code, to determine the phase difference between a received PN code and the local code

Info

Publication number: GB2391779A
Application number: GB0326126A
Authority: GB
Inventors: Yasuyuki Oishi; Kazuo Nagatani; Hajime Hamada; Yoshihiko Asano
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 1998-07-17
Filing date: 1999-06-07
Publication date: 2004-02-11
Anticipated expiration: 2019-06-07
Also published as: GB2391780B; GB0326184D0; GB0326126D0; GB2391779B; GB2391780A

Abstract

A correlator for determining a phase difference between a received spreading code included in a spread-spectrum signal and a reference spreading code, in a mobile communication system. The correlator has a reference spreading code generator for generating the reference spreading code 21, 21'. A first combined code generator 22 generates a first combined code from the reference spreading code; and a first arithmetic circuit 23 calculates a first correlation between the received spreading code and the first combined code. Meanwhile, a second combined code generator 22' generates a second combined code from the reference spreading code; and a second arithmetic circuit 23' calculates a second correlation between the received spreading code and the second combined code. A further arithmetic circuit 26 determines the phase difference r based on the first and second correlations.

Description

2391 779

CORRE ATOR

This application is a divisional of GB 2 340 002 and relates to a particular form ? 2;. i- / 5 of a correlator disclosed in that application. further co-penling divisional relates to a DLL circuit disclosed in GB 2 340 002.

The present invention is directed to a correlator for detecting the code phase of a spreading code on a transmitting side (i.e., a code phase of a received spreading code) in a case where a direct-sequence spreadspectrum signal is received, for example in a 10 mobile communications system.

Direct-sequence code division multiple-access based upon direct-sequence spread-spectrum (DS-SS) modulation has been considered as a wireless access scheme for next-generation digital mobile communications systems. In order to receive a spread-spectrum signal, a code phase of a spreading code on the transmitting side must 15 be detected on a receiving side and a spreading code for Respreading purposes must be generated so as to achieve phase synchronization with the spreading code on the transmitting side.

Digital cellular wireless communication systems using DS-CDMA (Dircct-

Sequence Code Division Multiple-Acccss) technology have been developed as next 20 generation mobile communication systems for implementing wireless multimedia communications. In a CDMA digital cellular wireless communications system of this kind, a base station transmits control information and user information after multiplyin,

this information w.., a spread -,, code. T^dir,dual mobile stations spread and transmit information using a spreading code specified by the base station. In order for a mobile station to correctly recei he information. s ch as control irforr..ion from the home station in a CDhIA digital cellular wireless communications system of this kind, it is necessary 5 to identify the timing at which the spread-spectrum modulation starts at the base station, i. e, the phase of the spreading code.

Fig. 19 shows a receiver of a mobile station for a CDMA digital cellular wireless communication system The receiver includes an antenna 1, a receiver circuit 2 for performing amplification and frequency conversion from RF (radio frequency) to IF 10 (intermediate frequency) a QPSK detector 3 for performing QPSK detection and outputting I, Q signals and an AID converter 4 for converting, baseband analog I, Q signals output from detector 3 to digital I, Q data, a despreading circuit 5 for applying despread processing to the I, Q data output by the N converter 4, a data demodulator 6 for performing synchronous detection, data discrimination and error correction, a 15 correlator 7 for performing a correlation operation in order to identify spread start timing (the phase of the received spreading code) and a timing decision unit 8 for identifying spread start timing (phase) from correlation value.

The correlator 7 performs a correlation operation between a received spread-

spectrum data sequence and a reference spreading code sequence (a spreading code 20 sequence identical with that on the side of the base station).

As shown in Fig. 20, a spreader 9 on a transmitting side executes spread processing and transmits a signal indicated by: X(t) = a(t) c(t)

Where a(,J lep,eser.ts ans...;,t+ed and Art) apes (pseudsóandom num.her3 sequence. The PN sequence cats is a,spreading wde sequence of "lies and ''O"s. The C=me code sequence (a code sequence of N chips) is repeated on a per-symbol basis, wherein 5 one s;yrnbol corresponds to one-bit of data.

The signal x(t) is received on the receiving side, where the correlator 7 calculates the correlation between the signal x(t) and a reference spreading code c(t-) and outputs a correlation value it(t) indicated by the following equation: it(t) = Ex(t) c(t-) 10 -Za(t) c(t) c(t-),t=Tc,2Tc, - NTc where represents a code shin (phase difference) between the spreading code on the transmitting side and the reference spreading code of the correlator on the receiving side.

The integration interval is the duration of one symbol (the time period of N chips, which is equal to N Tc).

15 If A(t) = 1" holds in the above equation the correlation value it(t) will indicate the auto correlation value of the PN sequence. If the PN sequence is an M sequence, R(+.) = N (1 when normalized) is obtained as a maximum at = 0 and it(t) = 1/N holds at 0. In actuality, a(t) is urnown and may be " 1'' or "0". However, by assuming for example that alp = -I and 0" 1, and integrating the absolute value of a(t) c(t) -c(t-), it(t) 20 = 1 is obtained at = 0 and it(t) = 1/N at 0.

Thus, by calculating correlation values while changing the phase of the reference spreading code c(t-) one chip width Tc at a time and detecting the tirrung at which the correlation value exceeds a set level, it is possible to identify the spread start timing on

the transmi++.:lug side lithe phase of the spreading code on the transmitting sided.

Accordingly, the timing decision unit 8 of Fig. 19 acquires the spread start timing (phase) based UpOIl the +;ning at which the correlation value output by the correlator 7 exceeds the set level and inputs this timing to the Respreader circuit 5.

5 A matched filter and a sliding correlator are available as the principal correlation detection techniques applied to DS-SS signals.

Fig. 21 shows a matched filter 71. The matched filter includes an N-chip shift register (si -so) 71a for successively shining the received spreadspectrum data sequence of the baseband (the output of the AID converter in Fig. 19) at the chip frequency. Also 10 included is an N-chip shift register (cat -CN) 71b for storing the reference spreading code sequence, N-number of multiplying corresponding bits of the baseband spreadspectrum data sequence and reference spreading code sequence. An adder circuit 71d is further included for adding the outputs of the multipliers and a PA generator 71e for generating the PA sequence (the reference spreading code sequence).

15 The reference spreading code sequence is composed of N chips. The matched filter 71 outputs one correlation value it(t) per chip period To and then successively outputs a correlation value every time the phase of the baseband spread-spectrum data sequence changes by one chip width Tc. The matched filter thus outputs correlation values of N-number of different phases over the period of one symbol.

20 The timing decision unit 8 monitors the correlation value it(t) output by the matched filter 71, determines whether the correlation value has exceeded the set level and identifies the stars. of the spreading code sequence on the transmitting side (spread start timing) when the correlation value exceeds the set level.

Fig. 22 shows a sliding correlator 72, which includes a PN generator Ma for generating a PN sequence (reference spreading code sequence). The reference spreading code sequence is composed of NT chips and is generate cyclically at the symbol period T (= N X Tc). Further, multiplier 72b multiples the baseband spread-spe<;trum data 5 sequence (the received signal) by the reference spreading code sequence chip by chip and outputs the result.

An integrator 72c integrates N chips of the output of multiplier 72b and outputs the correlation value it(t) The integrator 72c includes an adder 73 for adding the output of the multiplier 72b and the current integrated value, and a delay circuit 74 for 10 outputting the integrated value from adder 73 upon delaying the value by one chip period.

The sliding correlator 72 outputs one correlation value it(t) in one symbol period (the period of N chips) and shifts the phase of the reference spreading code by one chip every symbol, thereby outputting correlation values of N-number of different phases over the period of N symbols (- N2.Tc).

15 The timing decision unit 8 monitors the correlation value it(t) output by the sliding correlator 72 to determine whether the correlation value has exceeded the set level. Further, the timing decision unit shiRs the phase of the reference spreading code if the correlation value is less than the set level and identifies the start of the spreading code sequence on the transmitting side when the correlation value exceeds the set level.

20 Thus, the phase of the spreading code on the transmitting side can be detected at a precision of within one chip by the matched filter or sliding correlator. (This is referred to as "synchronization acquisition". ) This is followed by perlForm.ing Respreading by

generating the spreading code sequence ire sync With the detected phase to despr-d on the receiving side.

However, if no farther action is taken once synchrortion has been acqu; sed, the synchronizing position will be lost owing to the effects of modulation and noise. I-his makes it necessary to exercise control in such a manner that the spreading code sequence on the receiving side will not develop a time shift with respect to a received signal for which synchronization has been acquired. (This is referred to as "synchronization tracking".) A DI,L (Delay Locked Loop) is known as such a synchronization tracking circuit. 10 Fig. Z3 shows a DLL circuit, which includes a PN generator 9a that generates a first PN sequence (the reference spreading code). The PN generator 9a has nine delay circuits D 1 - D9 and an Ex-OR gate provided at the input of the fourth delay circuit. This configuration outputs a PN sequence of an M sequence in accordance with X9 + X4 + 1.

The first PN sequence Al is composed of N chips (= 29 = 512) and is generated cyclically 15 at the symbol period T (= N X Tc).

A delay circuit 9b delays the first PN sequence (reference spreading code) Al by one chip and outputs a second PN sequence A2. A multiplier 9c multiplies, chip by chip, the first PN sequence A output by the PA generator 9a and a received spread-spectnam data sequence B. A multiplier 9d multiplies, chip by chip, the second PN sequence A: 20 delayed by one chip and the received spread-specuum data sequence B. Further, an adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the code output by the multiplier 9d. The output of the adder he is input to a low-pass filter 9f, the output whereof is applied to a voltage-controlled oscillator (VCO)

9g, which varies the clock frequency rcL'p frequency) based upon the output of the low-

pass filter.

The multiplier 9c and low-pass filter 9f Unction to calc!ate the ccrelaton between the first PN sequence Al and the received spread- spectrum data sequence}3. If 5 the phase of the first PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained.

As shown in (a) of Fig. 24, a correlation value R() = 1 having the width of one chip is output every symbol. If the phase shifts by the width of one chip or more, the correlation value R() becomes TIN.

10 The multiplier 9d and low-pass filter of Unction to calculate the correlation between the second PN sequence A2 delayed by one chip width and the received spread spectrum data sequence B. If the phase of the second PN sequence and the phase of the received spread-spectrum data sequence match, the maximum output is obtained and a correlation value R() is output, as shown in (b) of Fig. 24. If the phase shifts by the 15 width of one chip or more, the correlation value R() becomes TIN. The adder 9e adds the output of the multiplier 9c and a signal obtained by inverting the output of the multiplier 9d. As a result, a signal having an S-curve characteristic shown in (c) of Fig 24 with respect to a phase difference r is output via the low-pass filter 9f.

On the basis of the output of the low-pass filter, the voltage-controlled oscillator 20 9g controls the clock frequency in such a manner that the phase difference becomes zero. For example, if the phase of the PN sequence (reference spreading code) leads that of the received spreading code, control is performed so as to make the phase difference zero by lowering the clock frequency. If the phase of the PN sequence (reference

t spreading code) lags bemired that of the riled spreading code, contra! is peffonned so as to make the phase difference zero by raising the clock frequency.

T bus, the phase of the spreading code sequence on the transmitting side is detected (synchronization acquisition) at a precision of within one chip by the correlator S (the matched filter of Fig. 21 or sliding correlator of Fig. 22), and then synchronization tracking is carried out by the DLL circuit.

Fig. 25 shows another example of a DLL circuit. In particular, Fig. 2'a shows a DLL circuit having a configuration similar to Fig. 23. Fig. 25(b) shows a configuration of another DLL circuit obtained by modifying the DLL circuit of Fig. 25(a). Since 10 multiplication by the PN code and adding the results of multiplication are linear operations, the operations can be interchanged in terms of their order. Accordingly, the DLL circuit of Fig. 93a provides an equivalent function even if the adjacent first and second PN code sequences are multiplied by +1 and -1 by multipliers 9h, 9I, respectively.

Further, the products are added by an adder 9j and the received signal is multiplied by the 15 value of the sum, as shown in Fig. 25(b).

The time needed to detect a code phase, the scale of the circuitry and the power consumption associated with the matched filter are compared with those associated with the sliding correlator, the following results are obtained: (1) If the code length for obtaining correlation is N chips, the code phase 20 detection time required for initial synchronization of reception will be N chips (--N Tc) in case of the matched filter and N2 chips (--N2 Tc) in case of the sliding correlator. In other words, the matched filter requires less tinge to detect the code phase, namely 1 of the time required in case of the sliding correlator.

al \ (2) The wale of Be circuitry in a -=se where the relator is implemerted by digital processing is understood from Figs. 21 and 22. Specifically, the matched filter requires two s=lll., egisters each hasting a length equivalent to the number of taps (=N), multipliers equivalent to the number of taps and one cumulative adder. The sliding 5 correlator, on the other hand, requires only one multiplier and one cumulative adder.

Therefore, the scale of the hardware of the matched filter is much greater than that of the sliding correlator.

(3) The power consumption of the circuitry is considered to be proportional to the product of the number of gates used and the operating frequency based on the assumption 10 that CMOS I,SI circuitry is used. The operating frequency is the chip frequency or the over-sampling frequency of the chip in the case of'ooth the matched filter and sliding correlator. Power consumption, therefore, is considered to be proportional to the scale of the circuitry. Accordingly, the power consumed by the matched filter is much greater than that by the sliding correlator.

15 Although the matched filter is advantageous in that code phase detection time is short, the scale of the circuitry is very large. A problem that arises, therefore, is that a matched filter cannot be used in a mobile station, which requires low power consumption The sliding correlator, on the other hand, has the advantage of small-scale circuitry. However, since code phase detection time is long, achieving initial 20 synchronization in the demodulation operation takes time which causes degradation of the system characteristics.; Further, with Me conventional DLL circuit, the phase synchronization acquisition range (i.e., the lock range) is small, namely the width of one chip or -Tc/2 to Tc/2, as is

( evident from Fig. 24( c). However, a problem that arises is that synchronization tracking can no longer be performed if a phase shin in excess of one chip occurs.

SUMMARY OF THE INVENTION

5 An embodiment of the invention may provide a correlator having circuitry of a smaller scale, which also makes it possible to shorten code phase detection time required for initial synchronization.

According to the present invention, there is provided a correlator for determining a phase difference between a received spreading code included in a spread 10 spectrum signal and a reference spreading code' comprising: a reference spreading code generator for generating the reference spreading code; a first combined code generator for generating a first combined code from the reference spreading code; 15 a first arithmetic circuit for calculating a first correlation between the received spreading code and the first combined code; a second combined code generator for generating a second combined code from the reference spreading code; a second arithmetic circuit for calculating a second correlation between the 20 received spreading code and the second combined code; and a third arithmetic circuit for determining the phase difference based on the first and second correlations.; The correlation detection using combined spreading codes provides a response of a linear sum of correlation outputs with respect to the plurality (M-number) of code 1 0

phases in the spreading code phase space in a single correlation operation. The response can be designed based upon the weighting function of the combined spreading code.

A correlator that discriminates an area in which a code phase resides and a correlator that uniquely decides code phase can be realized by employing the above 1 1

property. Phase detection +.ime of the correlator according to the present irNrention is 1../M that of a sliding correlator. Moreover, the scale of the circuitry is determined by adding a code combining circuit and phase d,s;minaton circuit onto a sliding corrlator7 Which is much smaller in scale than that of a matched filter.

5 The animator of tin Exeunt irt:im; a cnia between a received spreading code contained in a received spread-spectrum signal and a reference spreading code. This enables the phase of the received spreading code to be detected using first and second combined spreading codes obtained by applying first and second weighting to each of a plurality of phaseshifted reference spreading codes and 10 then combining the weighted codes.

For example, the first c sr is carafe by mi=:i cry the phase-shifted reference spreading codes by values obtained by sampling one period of a sine-wave signal in phase-shift units and - g: Whir 3ir is generated by weighting each of the phase-shiRed reference spreading codes bar values l 5 obtained by sampling one period of a cosine-wave signal in phase-shiR units. Thus, a phase difference between the received spreading code and reference spreading code (namely the phase of the received spreading code) is detected using the first and second combined spreading codes. If this arrangement is adopted, the phase of the received spreading code can be detected correctly even if the reception level changes.

20 Further, a code phase is detected accurately by enlarging the uruts in which the phase shift is made, obtaining the phase of the received spreading code at these phase shift units and then sequentially searching the phase area in the phase-shiD units obtained

using a sliding correlator, for example. If this arrangement is adopted, the code pose can be detected by a small number of correlation operations.

T.r [at_ in, a Eh arm in vamp a EN dif 5 t received spreading code and reference spreading code (namely the phase of the received spreading code) belongs i s Awing Biro ci codes. The combined spreading -us are cattail itir cabining a plurality of EN shined reference spreading codes. Further, the weighting is changed and a smaller phase 10 area to which a code phase belongs is discriminated, and the phase area is narrowed down by repeating these discrimination operations.

For example, the phase area is divided into first and second areas. The phase area in which a code phase belongs is identified by discriminating the sign of a correlation value The correlation value is obtained by the weight of a reference spreading code for 15 which the amount of phase shin resides in the first phase area is +w (where w is an integer) and the weight of a reference spreading code for which the amount of phase shiR resides in the second phase area is made -w. The identified phase area is then divided further into two area and similar weighting and discrimination operations are performed to narrow down the phase area. 1 bus, the phase of the received spreading code is 20 detected by subsequently repeating weighting and discrimination. If this arrangement is i adopted, the scanning of all code phases of N chips is completed by performing log2N number of correlation operations.

1 3

\ A description will now be given by way of example with reference to the

accompanying drawings, in which: Fig. 1 is a diagram showing a correlator which is not in accordance with the present invention, but useful for understanding the same; 5 Fig. 2 is a diagram illustrating the operation of the correlator of Fig. 1; Fig. 3 is a diagram showing a generalized configuration of the correlator of Fig. 1; Fig. 4 is a diagram showing a first embodiment of the correlator according to the present invention; 10 Fig. 5 is a diagram showing the operation of the correlator of Fig. 4; Fig. 6 is a diagram the output of a correlation detector; Fig. 7 illustrates a second embodiment of the correlator according to the present invention; Fig. 8 is a diagram of the second embodiment of the correlator according to the 15 present invention; Fig. 9 is a diagram for explaining weights used in a correlator; Fig. 10 is a diagram showing another correlator which is not in accordance with the present invention; Fig. 11 is a diagram showing a first DLL circuit; 1 4

Fig. 12 is air output waveform. for the DLL circuit of Fig. 11; Fig. 13 is a filter output characteristic for the DLL circuit of Fig. 11; Fig. 14 is a diagram showing a generalized configuratiori of the DLL circuit of Fig. 11; Fig. 15 is a diagram showing the S curve ofthe ALL circuit of Fig. 14; Fig. 16 is a diagram showing a table look-up DLL circuit; Fig. 17 is a diagram illustrating the operation of the ALL circuit of Fig. 14; Fig. 18 is adiagrarn showing second Did circuit; Fig. 19 is a diagram showing a receiver of a mobile station; Fig. 20 is a diagram illustrating decision of spread start timing by a correlator; Fig. 21 is a diagram showing a matched filter; Fig. 22 is a diagram showing a sliding correlator; 15 Fig. 23 is a diagrar.n showing a conventional DLL circuit; Fig. 24 is a diagram illustrating the S-curve of a DLL circuit; and Fig. 25 is a diagram showing another conventional DLL circuit.

20 (A) Correlator (a) Background Explanation

1 5

(' Before describing a correlator or the present invention, a correlator employing a single combined code generator will first be described as' background explanation.

in Fig. 1, 21 designates a PA sequence generator for cyclically generating a PA sequence (a reference spreading code) as an M sequence. The PA sequence has a code length of N chips, where the chip width is Tc. The code period (N Tc) of the PA sequence is equal to one symbol period (one bit interval) T. A combined code generator 22 weights arid combines a plurality of (two in the illustration) of phase-chided reference spreading code sequences, namely first and second reference to spreading code sequences Al and Az. An arithmetic circuit 23 calculates the correlation between a combined spreading code A arid a received spreading code B. A phase detection circuit 24 detects the phase difference between the received spreading code and the reference spreading code (namely the phase of the received spreading code) on the basis of the output level of the arithmetic circuit.

15 The combined code generator 22 includes a phase shift circuit 22a for outputting the first reference spreading code Al: C(t), C2(t),, C?(t) and the second spreading code A2: C(t+n Tc), Cz(t+n Tc), -, CN(t+n Tc The first reference spreading code Al has not been delayed, while the second reference spreading code 2 has been delayed by a time equivalent to n chips (=n Tc). The combined code generator includes a weighting 20 circuit 22b for weighting the first and second reference spreading codes Al, A2 by weights Wit, W: (W>W2), respectively, and a combining circuit 22c for combining the weighted first and second reference spreading codes to output the combined spreading code. It should be noted that n = N/2 1 6

I, 1 The arithmetic circuit 23 has a multiplication circuit 23a that multiplies the received spreading code B by the combined spreading code A, one chip at a time at the Chip period. Further, an integrator 23b adds the results of multiplication N times and then Outputs the result. The integrator 23b has an adder SUM that adds the output of the 5 multiplication circuit 23a and the currently prevailing integrated value. A delay line DEL then outputs the integrated vague, which is the output of the adder, upon delaying the integrated value by one chip width Tc.

The correlatorof Fig. 1 is obtained by providing the conventional sliding integrator described in regard to Fig 22 with the phase shifter 22a, weighting unit 10 22b and combiner 22c. If the second reference spreading code is assumed to be O. then the correlator becomes a sliding correlator similar to that of the prior art.

If the phases of the first reference spreading code Al and received spreading code B match, the arithmetic circuit 23 outputs the signal shown in (a) of Fig. 2 After integration has been performed N tines, the arithmetic circuit 23 outputs a correlation 15 value of level WE (- NEWS). Similarly, if the first reference spreading code Al is assumed to be O and, the phases of the second reference spreading code A: and received spreading code B match, the arithmetic circuit 23 outputs the signal shown in (b) of Fig. 2. After integration has been performed N times, the arithmetic circuit 23 outputs a correlation value of level Wz (= N W2).

20 In actuality, the first and second reference spreading codes Al, As are not 0.

However, the phases of the first and second references spreading codes Al, A2 do not coincide with the phase of the received spreading code B simultaneously. Accordingly, the phase detection circuit 24 monitors the correlation level (the correlation value of one

It ? period of the referent spradir.g coded that p, avails after N additions and (1) decides that the phase of the received spreading code matches the phase of the first reference spreading code Al if the correlativil leve! is WE Farmer, the phase detection circuit 24 (2) decides that the phase of the received spreading code matches the phase of the second 5 reference spreading code A2 if the correlation level is WE and (3) decides that the phase of the received spreading code does not match the phases of the first and second reference spreading codes if the correlation level is zero.

In case of (3) described above, the phase detection circuit 24 delays, by one chip, the phase of the next period of the PA sequence output by the PN sequence generator 21.

10 The phase detection circuit 24 then repeats the operation described above. If the correlation level becomes WE while the PN sequence generator 21 is outputting a reference spreading code having a phase delayed by m chips, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code in m.Tc. If the correlation level becomes We, then the phase 15 detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is (m+n) Tc.

If the correlation is calculated between the received spreading code B and the combined spreading code A, which is obtained by combining two reference spreading codes Al, A2 delayed in phase as set forth above, the time needed for phase detection is 20 N2/2 chips (= N2 Tc/2). Therefore, the time required for detection is shortened to half that of the conventional sliding correlator. !) (b) Ge;erali7ed cor.Sration In Fig. 1, the correlator is arranged such

that i reference sp. ending codes Al, A: delayed in phase ate contained upon being weighted by weights we, we, respectively. Thus, the correlation between the 5 combined spreading code and reference spreading code is calculated. If an arrangement is adopted in which this approach is expanded to combine M-number of phase-delayed reference spreading codes Al - AM weighted by weight we -WM, respectively, to calculate the correlation between the combined spreading code and the received spreading code, then the time needed to detect phase can be shortened to N2 Tc/Nl.

10 In view of the above, Fig. 3 shows a generalized configuration of the correlator according to Fig. 1, in which components identical with those of Fig. I are designated by like reference characters. Shown here are the PA sequence generator 21, the combined code generator 22, the arithmetic circuit 23, the phase detection circuit 24 and an oscillator 25 for outputting a clock having the chip frequency.

15 The combined code generator 22 includes the phase shift circuit 22a, the weighting circuit 22b and the combining circuit 22c. The phase shin circuit 22a has delay elements Do - DM each of which successively delays the PA sequence, which is the! reference spreading code, by (N TclM). The weighting circuit 22b includes multiplication circuits NIPS -MPM for weighting the 1 through Mth reference spreading 20 codes A! - AM, which are output by the phase shift circuit, by weights W! - WM (Wit > W2 > À > WM)' respectively. The combining circuit 22c combines the weighted 1 - Mth reference codes and outputs the combined spreading code A. 1 9

) 1lle =4hmetic circuit 23 includes the multiplication circuit 23a for multiplying the received spreading code B and the combined spreading code A at the chip period.

Further, the integrator 23b adds rule,-exults of miltiplica+on N noes and outputs the result. 5 The phase detection circuit 24 monitors the correlation level (the correlation value of one period of the reference spreading code) that prevails after N additions. Further, the phase detection circuit 24 (I) decides that the phase of the received spreading code matches the phase of the first reference spreading code Al if the correlation level is Wit, (2) decides that the phase of the received spreading code matches the phase of the second 10 reference spreading code Al if the correlation level is W:; --, (3) decides that the phase of the received spreading code matches the phase of the Mth reference spreading code AM if the correlation level is W7M and (4) decides that the phase of the received spreading code does not match the phases of the 1 through Mth reference code sequences if the correlation level is zero.

15 In case of (4) above, the phase detection circuit 24 delays, by one chip width Tc, the phase of the next period of the reference spreading code (PN sequence) output by the PN sequence generator 21. The phase detection circuit 24 then repeats the operation described above. If the correlation level becomes Wit while the PN sequence generator 21 is outputting a reference spreading code (PN sequence) having a phase delayed by m 20 chips, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is m Tc. If the correlation level becomes W:, the phase detection circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is [m+(NlM)] Tc. Further, if

the correlation level becomes NY3, the phase d - reckon circuit 24 judges that the phase difference between the received spreading code and the reference spreading code is Lm+(Nl)j Tc; -a. If the correlation level becomes WM, the phase detection c;'cn;.t 24 judges that the phase difference between the received spreading code and the reference spreading code is [m+(M-l)] N/1 Tc.

If the correlation is calculated between the received spreading code B and the combined spreading code A, which is obtained by combining M- number of phase delayed reference spreading codes Al - AM as set forth above, the time needed for phase detection is N2 Tc/2vI. Thus, the time required for detection is shortened to ItM that of 10 the conventional sliding correlator.

If C represents the spreading code, N the code length and IvI the number of codes E combined, then a linear combined code S will be Even by the following equation:: S=E wjCi - ' i= l ON (I) 1 where Hi represents the weighting coefficient of a jth code to be added and ó(j) I represents the amount of phase shin of the jth code to be added. In a case where correlation detection is performed using Si in Equation (i) as the combined spreading] code, a correlation output value proportional to Hi is obtained with respect to the code phase of ó(j). As a result, a correlation output with regard to M-number of code phases 20 can be obtained by a single correlation detection operation.

( c) First embodiment of correlator l Fig. 4 shows a f first embodiment of the correlator according to the present Invention, in which components identical with those of the correlator sham in

Fig. 3 &-e designated by like reference c^ur.ers. In this invention, two correlators (ccxbined code generators), are provided and a phase differences between the received spreading code and reference spreading code (the phase of the received spreading code) is detected using the output of each correlator.

5 Reference numerals 21, 21' designate identical first and second PN sequence generators for cyclically generating PN sequences (reference spreading codes) as M sequences. Each PN sequence has a code length of N chips, where the chip width is Tc.

The code period (N-Tc) of each PM sequence is equal to one symbol period T. Combined code generators 22, 22' each weight arid combine a plurality (M in the illustration) of 10 phase-shifted reference spreading code sequences Al - AM.

Further, first and second arithmetic circuits 23, 23' calculate the correlations between combined spreading code A, A', respectively, and the received spreading code B. Oscillators 25, 25' output clocks having the chip frequency. A third arithmetic circuit 26 calculates the phase difference using correlation values output by the first and second 15 arithmetic circuits 23, 23'. The first and second combined code generators 22, 22' include phase shin circuits 22a, 22a', weighting circuits 22b, 22b' and combining circuits 22c, 22c', respectively.

The phase shift circuit 22a of the first combined code generator 22 has delay elements Do - DM each of which successively delays the PN sequence by (N Tc/M). The 20 weighting circuit 22b includes multiplication circuits MA - MPM for weighting the 1 Mth reference spreading codes as A; - An, which are output by the phase shift circuit, by the weights wit - WM, respectively. The combining circuit 22c combines the weighted 1 IvIth reference codes and outputs the combined spreading code A. The weights we - WM

! ( are obtained by successively sampling one period (= N Tc) of a cosinewave signal at the units (N TclM) at which the phase of the reference spreading code is shined. Fig. 5(a) illustrates the weights in a case where sampling is camed out at the period of N Tc/M, en., at the chip period Tc, where M = N holds.

5 The phase shiR circuit 22a' of the second combined code generator 22' has delay elements D, - DM each of which successively delays the PA sequence by (N Tc/M). The weighting circuit Z2b' has the multiplication circuits MA - IVIPM for weighting the 1 through Mth reference spreading codes A! - AM, which are output by the phase shift circuit, by weights we' - we', respectively. The combining circuit 22c' combines the 10 weighted 1 through pith reference codes and outputs the combined spreading code A'.

The weights we' - we' are obtained by successively sampling one period (= N Tc) of a sine-wave signal at the units (N TclM) at which the reference spreading code is shined.

Fig 5(b) illustrates the weights in a case where sampling is carried out at the period of N Tc/^ ex., the sampling is carried out at the chip period Tc, where M = N holds.

15 In a case where M = N holds, the first combined code generator 22 outputs a combined spreading code U(i) indicated by the following equation: ul(i) = EPN(i+j) x cos (2/N) (2) where j = -N/2 - N/2 holds.

The second combined code generator 22' outputs a combined spreading code 20 uQ(i) indicated by the following equation: OQ (i) = PN(+j) x sin (2j/N) (3) where j = -N/2 - N/2 holds.

i The *rst arithmetic circuit 23 multiplies the combined spreading code vet 0) by the received spreading code. Further, the first arithmetic circuit 23 cumulatively adds (integrates) the results of multiplication over one period (= Tc) of the reference spreading code. Similarly, the second arithmetic circuit 23' multiplies the combined spreading code Phi) by the received spreading code, and cumulatively adds (integrates) the results of multiplication over one period of the reference spreading code.

Fig. 6 illustrates the output characteristics of the first and second arithmetic circuits 23, 23' in a case where the received spreading code B is multiplied by the combined spreading codes A, A', where the results are cumulatively added (integrated) 10 over one period of the reference spreading code. From this cos, -sin characteristics are obtained with respect to all phases (19 = -256 to 256) of the code. As a result, a third arithmetic circuit 26 uniquely decides and outputs the phase difference (the phase of the reference spreading code) between the received spreading code and reference spreadin code Tom the results or, t> Q of integration, where is given by the following equation: 15 O=- tanloQ/ur (4) In other words, the code phase is obtained by integrating over one period (=N Tc) of the reference spreading code Thus, the amount of time needed is significantly shortened in comparison with the conventional sliding correlator, which requires a length of time equivalent to N2 Tc.

20 In addition, the scale of the circuitry is much smaller than that of a matched filter.

It should be noted that if delayed waves are present, it may be necessary to adopt an arrangement in which the vicinity of the obtained phase difference 3 is searched using a sliding correlator. In this case, however, the time needed for synchroruzation can be

shorter,ed in comparison with the conventional sliding correlator, which sequentially scans all code phases.

The PM sequence generators 21, 21' of Fig. 4 can be combined into a single common PN generator. The same is true for the phase shift circuits 22a, 22a' and 5 oscillators 25, 25'.

(d) Second embodiment of correlator In mobile communications, multiple paths exist. As shown in (a) of Fig. 7, transmitted signals from a base station BS arrive at a mobile station MS successively via multipaths MPO, MP 1, MP2 with delay times i, lo, as illustrated in (b) of Fig. 7. These 10 multipath signals constitute noise in phase detection and are obstacles to accurate detection of code phase a in the first embodiment. Multipath signals, however, can be dispersed within a certain range of phases.

I n a 1 mine -,: - doff is <d Archly in units of (em) using 4' for example, as M of the first embodiment. This enables 15 phase areas Rl- R4 [Fig. 7( c)] in which the true phase difference resides, to be discriminated, and the interiors of the phase areas are searched sequentially by a sliding correlator to obtain the phase difference for which the maximum correlation is obtained.

It this arrangement is adopted, phase difference can be detected accurately even if multipaths exist.

20 Fig. 8 shows the 1 er9ink cf Or w, F invention, in which components identical with those of the first embodiment are designated by like reference characters. Did fir differs fran fc embodiment in that (1) a sliding correlator 31 is provided on the output side of the third

) 1" arithmetic circuit 26; (2) a phase detection circuit 32 is provided for detecting the phase for which the correlation value output by the sliding correlator is maximized; and (3) Ivl=4 is used for the chelator of Me second embodirrnt.

The phase shin circuit 22a of the first combined code generator 22 has delay 5 elements Do - D3 each of which successively delays the PN sequence by (N.Tc/4). The weighting circuit 22b has multiplication circuits MA - MP for weighting the first through fourth reference spreading codes al for weighting the first through fourth reference spreading codes A - A4, which are output by the phase shin circuit, by the weights we - W4, respeGtively. The combining circuit 22c combines the weighted first 10 through fourth reference codes and outputs the combined spreading code A. The weights wit - W4 are obtained by successively sampling one period (= N.Tc) of a cosine-wave signal at the units (N Tc/4) at which the phase of the reference spreading code is shifted.

Here we = COST, W2, - cosmos), W3 - cost), W4 = cos(32) holds.

The phase shift circuit 22a' of the first combined code generator 22' has delay 15 elements Di - D3 each of which successively delays the PN sequence by (N Tc/4). The weighting circuit 22b' has multiplication circuits MP i - MP4 for weighting the first through fourth reference spreading codes Al - A4, which are output by the phase shin circuit, by the weights we'. - we.', respectively. The combining circuit 22c' combines the weighted first through fourth reference codes and outputs the combined spreading code 20 A'. The weights we' - we,' are obtained by successively sampling one period (=N Tc) of a sine-wave signal at the units (N Tc/4) at which the phase of the reference spreading code is shined. Here w:' = sine, we' = sin(xl2), W3' = sin(2:rJ2), we' = sin(3/2) holds.

) lithe first combined code generator 22 outputs a combine spreading code oI(i) indicated by the following equation: )(l) = TPN(i+(N/4)j) x cosj (3v'2) t5) where j = 0 - 3.

5 t>Q(I) - N(i+(N/4)j) x sinj(7t/2) (6) where j = 0 - 3.

The first arithmetic circuit 23 multiplies the combined spreading code Phi) by the received spreading code and cumulatively adds (integrates) the results of multiplication 10 over one period (--N Tc) of the reference spreading code. The second arithmetic circuit 23' multiplies the combined spreading code Q(i) and the received spreading code and; cumulatively adds (integrates) the results of multiplication over one period of the reference spreading code.

The third arithmetic circuit 26 obtains the phase difference (code phase) (3 from 15 lo, Do in accordance with Equation (4). As a result, in which of the M-number of areas a response resides is specified, where the Mnumber of areas are obtained by dividing all N code phases into M (= 4) areas The sliding correlator 31 determines that the true code phase exists in an area Ri in which there is a response. The sliding correlator 31 then performs a search 20 sequentially with respect to the phase of N/M-number of chips of the area Ri in a marmer similar to that of the prior art. More specifically, the sliding correlator 31 generates the

reference spreading code at the initial phase of the area Ri, calculates the correlation between this reference spreading code and the receiving spreading code, outputs one Z

I ( correlation value it(t) following one symbol period (=N Tc) and shins the phase of the reference spreading code by chip width. The sliding correlator 31 then outputs correlation values of N/M-number of different phases and, the phase detection circuit 32 finds the code phase for which the correlation value it(t) output by the sliding correlator 5 31 is maximized.

By virtue of the operation described above, the scanning of ail code phases of N chips of one symbol can be completed in a time of (N2/M+N) Tc in accordance with the so errLDdLTT=c. Thus, the amount of time needed is shortened greatly in comparison with the conventional sliding chelator, which requires a length of time equivalent to 10 N2TC,

(e) Another corrugator; In the correlator of Fig. 3, the arithmetic circuit 23 (1) outputs a correlation value of level We if the phase of the received spreading code B matches the phase of the first reference spreading code Al. Further, the arithmetic unit 23 (2) outputs 1 S a correlation value of level W2 if the phase of the received spreading code B matches the phase of the second reference spreading code A: and (3) outputs a correlation value of level WM if the phase of the received spreading code B matches the phase of an Mth reference spreading code AM.

Accordingly, when a phase area is divided into No portions, all weights we - WE 20 of reference spreading codes Al - AM for which Me amounts of phase shift reside in the first phase area are made w (where w is an integer). Thus, all the weights we+ - WE Of the reference spreading codes A. - AM for which the amounts of phase ship reside in the second phase area are made -w (Fig. 9(a)). When this arrangement is adopted, the

) ( arithmetic cu-c-mt 23 outputs 8 correlation value of weight W if the phase of the received spreading code B matches the phase of any one of the reference spreading codes Al - JAM and outputs a correlation sue o'weight -W if the phase of the received spreading code B matches the phase of any one of the reference spreading codes A'n+ -

5 AM. As a result, the phase detection circuit 24 is capable of recognizing the phase area to which the code phase belongs depending upon whether the correlation value is +W or -W. The phase area to which the code phase belongs is then divided further into two portions and similar weighting [Fig. 9(b)] and discrimination are carried out to narrow 10 down the phase area. If these weighting and discrimination operations are repeated (Figs 9(c), (d)), the phase difference between the received spreading code and reference spreading code (namely the phase of the received spreading code) can eventually be detected. For example, as indicated by the hatched portions in Figs. 9(a) through (d), the area in which the code phase actually resides in narrowed successively and matching of 15 the phase of the received spreading code with the phase of the second reference spreading code can eventually be recombed. If the relation M = N holds, the method described above makes it possible to complete the scanning of all code phases of N chips by perforTrung correlation detection log:N times.

Fig. lOshows another correlator (not part of the invention), in 20 which components identiod with those of the correlator of Fig.3 are designated by like reference characters This circuit includes the PN sequence generator 21, the combined code generator 22, the arithmetic circuit 23, the phase detection circuit 24 and Me oscillator 23 for outputting a clock having the chip frequency.

I-he combined code generator 22 includes the phase shin, circuit 22a, the weighting circuit 22b, the combining circuit 2c and a weight selector 22d. The phase sniff circuit 22a has delay elements Do - DO for successively delaying the PA sequence, which is the reference spreading code, (N-TcIM) at a time. The weighting circuit 22b has S multiplication circuits MP NfPM for weighting the 1 - Mth reference spreading codes A} - AM, which are output by the phase shift circuit, by weights we - WM, respectively.

The combining circuit 22c combines the weighted 1 - Mth reference spreading codes and outputs the combined spreading code A. The weight selector 22d is provided with the following K sets of weight patterns 10 in advance: WII, W2I, W31,... WMI'

Wt2, W22, W32,... WM2, WiK, W2K7W3K, -- We, 15 and changes weight patterns successively whenever identification of which of the two divided phase areas a code phase belongs to is completed, thereby eventually identifying the code phase. If N= S12 and M = N holds, then K= 9 and nine sets of weight patterns are provided. As shown in Fig. 9(a), the first weight pattern is one in which the weights Eve - wm of m (=M/2) reference spreading codes are made positive and 20 constitute the first half of the successively phase-shifted M (- N) reference spreading codes. The weights wand - WM of M/2 reference spreading codes are made negative and constitute the second half of the successively phase-shifted M (= N) reference spreading codes. The second and third weight patterns are the patterns shown in Figs. 9(b) and

9tc), respectively, and the last or ninth weight pattern is one in which low and -w alternate. The arithmetic circuit 2 includes Me multiplication circuit Ma for multiplying the received spreading code B. by the combined spreading code A and the integrator 23b 5 for adding the results of multiplication N times and outputting the resulting correlation value. The phase detection circuit 24 monitors the correlation value (the correlation value of one period of the reference spreading code) that prevails after additions, discriminates the area to which the code phase belongs depending upon whether the correlation value is +W or -W. and causes the weight selector 22d to select the weights of 10 the next group.

Lnitially selectors SELF - SELM of the weight selector 22d select the weight pattern of Fig 9(a) and input the pattern to the multipliers ME Who, respectively. The arithmetic circuit 23 outputs a correlation value of +W if the code phase is present in the initial phase area Rid [Fig. 9(a)] and outputs a correlation value of -W if the code phase is 15 present in the other phase area Ritz. The phase detection circuit 24 identifies the phase area by the sign of the correlation value and then instructs the weight selector 22d to; select the next weight pattern.

The weight selector 22d responds by selecting the weight pattern of Fig. 9(b) and inputs the pattern to the multipliers MPr - MPM of the weighting circuit 22b. The 20 arithmetic circuit 23 outputs the correlation value of +W if the phase difference resides in phase area R2 or phase area Rae, and outputs the correlation value of -W if the phase difference resides in phase are Rz2 or phase area 124. When the phase detection circuit 24 identifies the phase area by sign of the correlation value, it instructs the weight selector;

) 22d to select the next weight pattern. Ibis operation is performed repeatedly to finally specify the area to which the code phase belongs.

(B) DLL circuit (a) Fig. 11 shows a first DLL circuit (not part of the invention).

5 Reference numeral 51 desigrrates a PN sequence generator for cyclically generating a PN sequence (a reference spreading code) as an M sequence. The PN sequence has a code length of N chips, where the chip width is Tc. The code period (A Tc) of the PA sequence is equal to one symbol period T. A combined code generator 52 weights and combines a plurality (four) of phase 10 shifted reference spreading code sequences Al - A4. A multiplier 53 multiplies the combined spreading code A and the received spreading code B. chip by chip. A filter 54 subj ects the output of the multiplier to filtering processing. A voltage-controlled oscillator (VCO) 55 is capable of varying the clock frequency (chip frequency) based upon the output of the filter to syrlchronze the reference spreading code with the received 15 spreading code.

The combined code generator 52 includes a phase shift circuit 52a, a weighting circuit 52b and a combiner 52c. The phase shin circuit 52a has delay elements Do - Do each of which successively delays the PM sequence that is the reference spreading code by one chip width Tc. The weighting circuit 52b includes multiplication circuits IvfP 20 P4 for weighting the first - fourth reference spreading codes Al - A., which are output by the phase shin circuit, by weights we - W4 (W; = 1.O, W2=.5, W3 =.5, W4 =-1.0) , respectively.

! The combiner 52c combs We weighted first-ourth reference spreading codes and outputs the combined spreading code A The multiplier 53 and filter 54 calculate simultaneously the correlations between the reference spreading codes Al - A. mId the received spreading code B. The results of these calculations are then combined and 5 output. More specifically, the multiplier 53 and filter 54 calculate (1) the correlation between the first reference spreading code Al and the received spreading code, (2) the correlation between the second reference spreading code A: and the received spreading code, (3) the correlation between the third reference spreading code ^3 and the received 10 spreading code, and (4) the correlation between the fourth reference spreading code A4 and the received spreading code. These calculations are then combined and output.

Accordingly, if the phase of the received spreading code B matches the phases of each of the first - fourth reference spreading codes A, - A4, the filter 54 outputs the correlation values Cat - C4 at the phase illustrated in Fig. 12 and therefore outputs a signal 15 having the overall S-curve characteristic shown in Fig. 13. The phase synchronization acquisition range (lock range) is enlarged to the width of three chips, namely from -3Tc/2 to 3TcJ2, as evident Mom the S-curve.

The voltage-controlled oscillator 55 controls the clock frequency based upon the output of the low-pass filter in such a manner that the phase difference will become 20 zero. For example, if the phase of the reference spreading code leads that of the received spreading code, control is performed so as to make the phase difference zero by lowering the clock frequency. If the phase of the reference spreading code lags behind

to= of the received spreading code, cortro! is performed so as to make the phase difference zero by raising the clock frequency.

In accordance with the DIAL ci,-cu.e of Fig. 1 l, the lock range call be enlarged threefold in comparison with the conventional DLL circuit.

5 (b) Generalized configuration The DLL circuit described above relates to a case where four reference spreading codes Al -A delayed in phase are combined upon being weighted by weights we - win respectively, and the correlation between the combined spreading code and the received spreading code is calculated. If an arrangement is 10 adopted in which this approach is expanded to combine M-number of phase-delayed reference spreading codes Al - AM upon weighting them by weights we - WM7 respectively and to calculate the correlation between the combined spreading code and the received spreading code, then the lock range can be enlarged by a factor of (M-).

Fig. 14 is a diagram showing the generalized configuration of the DLL circuit 15 of Fig. 1 1, in which components identical with those of the DLL circuit of Fig. 11 are designated by like reference characters. The generalized configuration includes the PN sequence generator 51, the combined code generator 52, the multiplier 53, the low-pass filter 54 and the oscillator 55 for outputting the chip-Dequency clock 20 The combined code generator 52 includes the phase shirt circuit 52a, the weighting circuit 52b and the combiner 52c. Lyle phase shin circuit 52a includes M number of delay elements Do - Do each of which successively delays the PN sequence (the reference spreading code) by the chip width Tc. The weighting circuit 52b includes

! multiplication circuits MA - MA for weighting the 1 - Mth reference spreading codes Al - AM, which are output by the phase shift circuit, by weights we - was, respectively.

The combining circuit 52c then combines the weighted 1 - Mth reference codes and outputs the combined spreading code A. 5 The weights wit - WM are determined in the following manner. The weights of M12-number of reference spreading codes constituting the first half of the M-number of reference spreading codes successively shifted in phase are made positive and successively smaller. The weights of M12-number of reference spreading codes constituting the second half of the M-number of reference spreading codes are made 10 negative and successively larger. For example, when M = N holds, the following weights are adopted: we = N/2, we =(N/)- 1, W3 = (/2)-2,... we = 1, W(Nn = -1, w(NR2 = -2, WN = -(N/2) If weighting is performed in this manner, the combined code generator 52

will output a combined reference code fti), which is indicated by the following equation, at a 15 code phase of i Tc: Hi) = Ej x PN(i+j) (7) where j = -N/2 to N/2.

The multiplier 53 multiplies the combined reference code Hi) and the received spreading code B. chip by chip. The filter 54 subjects the output of the multiplier to a 20 filtering process. The voltage- controlled oscillator 55 then controls the clock frequency based UpOD the output of the low-pass filter in such a manner that the phase difference T becomes zero. If the reference spreading code has nine PA phases (where N = 512), an S-curve characteristic shown in Fig. 1: is obtained in the DLL circuit. The input code

phase (phase deference) is plotted along the horizontal axis in Fig. 15, sand the normalized output level is plotted along Me vertical axis. In accordance with the DLL circuit of Fig 14, an output characteristic having a linear slope can be obtained for all phases of the code and thus initial synchroruzation acquisition is unnecessary.

5 Fig. 16 shows a table look-up DLL circuit. Reference numeral 56 designates a combined code generator, which has a counter and a ROM table that outputs the combined reference code fti) indicated by Equation (7). The multiplier 53 multiplies the combined reference code A = Fiji) and the received spreading code B. chip by chip.

Reference numeral 54 designates the filter and 55 the voltage-controlled oscillator lo CO). The combined code generator 56 has a ROM table 56a for storing the comD'nu spreading code of Equation (7), and a counter 56b for generating a table address. The phase of the received spreading code and the phase of the reference spreading code are made to coincide by controlling the clock of the counter 56b by the voltage-controlled 15 oscillator 55 The content of the ROM table 56a can be configured in various forms depending upon the weighting method. The S-curve characteristic in a case where a table in accordance with Equation (7) is used is Al, shown in Fig. 15, as described above.

(c) Second DLL circuit An advantage of the DLL circuit according to the arrangement shown in Fig. 20 14 is that thelock range isenlargedifMislar, e. However, if the slope ofthe S-curve becomes more gentle, loop gain declines and achieving coincidence between the phases of the received spreading code and reference spreading code takes more time. Moreover, phase tends to fluctuate in response to external disturbances. On the other hand, if it is

( made smaller, then the lock range is reduced. However, the slope of the Swerve becomes extremely steep, loop gain can be enlarged and fluctuation of the phase in response to external disturbances diminishes.

Accordingly, as shown in (a) of Fig 17, hI is enlarged initially and a 5 synchronizing operation is performed. Thus, when a certain degree of synchronization has been achieved, the output level of the correlator declines. The output level is discriminated, is reduced and a changeover is made to a linear combined code set including narrower range of phases, as shown in (b) of Fig. 17. If control is performed in similar fashion so as to gradually reduce M (Fig 1 7(c)), synchronization can be achieved 10 earlier and the slope of the S-curve with respect to phase is made much steeper. This makes it possible to raise the loop gain and to improve the characteristic of the DLL circuit. Fig. lB shows a second DL circuit (not part of the present invention), in which components identical with those shown in Fig. 14 are designated by I 15 lilce reference characters. Reference numeral 51 designates the PN generator. Combined code generators 52 - 52N generate combined spreading codes in a case where = 2, = 4,...,1 = N hold, respectively. The multiplier 53 multiplies the combined reference code A and the received spreading code B chip by chip.

Reference numeral 54 denotes the filter and 55 the voltage-controlled oscillator.

20 Reference numeral 61 designates a state detector for detecting a state in which the output of the low-pass filter falls below a set level when a certain degree of synchronization has been achieved. Further, reference numeral 62 designates a selector for selecting and outputting the next combined spreading code having a small M.

The configuration c!f the combined code generator S2N is obtained when M in Fig 14 is made equal to N. The weights wit - WN are decided in a manner sirni1ar to that of Fig. 14. Ll particular, the weights of N/-num. ber of reference spreading codes of a small phase difference constituting the first half of the N-number of reference spreading codes 5 successively shifted in phase are made positive and successively smaller. The weights of N/2-number of reference spreading codes of large phase difference constituting the second half of the N-number of reference spreading codes are made negative and successively larger.

The combined code generator 522 has a configuration identical with that of the 10 combined code generator in the Did. circuit shown in Fig. 11, and the combined code generator 52 has a configuration identical with that of the conventional combined code generator, shown in Fig. 25(b), for which the lock range is one chip width To Initially, the selector 62 outputs a combined reference code, which is produced by the combined code generator S2N for which M = N holds, and performs a synchronizing 15 operation. The multiplier 53 multiplies the combined spreading code and the received spreading code B. chip by chip. The filter 54 subjects the output of the correlator to a filtering process and outputs the result. The voltage-controlled oscillator 55 controls the clock frequency based upon the output of the low-pass filter in such a manner that the phase difference I becomes zero.

20 As a result, when a certain degree of synchronization is achieved and the filter output decreases, the state detector 61 instructs the selector 62 to select the next combined spreading code. In response, the selector 62 outputs a combined spreading code for which M = Nl2 holds and performs a synchronizing operation. If control is

) ( subsequently performed in similar fashion in such a manner that Tomes gradually smaller, synchronization to within one chip will eventually be obtained.

Though tithe present invention has been designed in accordance with embodiments thereof, the present invention can be modified in various ways in accordance with the gist thereof set forth in the claims and covers these modifications In accordance with the present invention, the phase difference between a received spreading code and a reference spreading code (the phase of the received spreading code) is detected using combined spreading coded obtained by weighting and combining a plurality (M-number) of reference spreading codes that have 10 been shined in phase. Accordingly, it is possible to obtain, by a single correlation operation, a response of a linear sum of correlation outputs with respect to the plurality (M-number) of code phases in the spreading code phase space. As a result, the time needed for the correlator to perform phase detection can be made smaller than that of a sliding correlator. Moreover, the scale of the circuitry is also made smaller than that of a 15 snatched filter.

Further, in accordance with the present invention,;. the phase difference between a received spreading code and a reference spreading code (the phase of the received spreading code) is detected using first and second combined spreading codes. The combined codes are obtained by subjecting a plurality of phase-shiDed 20 reference spreading codes to first and second weighting and then combining the weighted codes. As a result, besides shortening phase detection time and reducing the scale of the circuitry, it is possible to detect phase correctly even if the reception level varies in dependence upon the state of reception.

Further, in an embodiment, code phase is detected correctly by enlarging the units in which phase is shifted, obtaining the phase difference (code phase) between the received spreading code and reference spreading code at these phase-shid units and then sequentially searching the interior of a coarse phase area in the phase-shift urnts 5 obtained by using a sliding Relator, for example. As a result, the time needed for the correlator to perform phase detection is made shorter than that of a sliding correlator.

Moreover, the scale of the circuitry is also smaller than that of a matched filter.

Claims

1. A coagulator for determining a phase difference between a received spreading code included in a spread-spectrum signal and a reference spreading code, comprising: a reference spreading code generator for generating the reference spreading code; a first combined code generator for generating a first combined code from the reference spreading code; a first arithmetic circuit for calculating a first correlation between the 10 received spreading code and the first combined code; a second combined code generator for generating a second combined code from the reference spreading code; a second arithmetic circuit for calculating a second correlation between the received spreading code and the second combined code; and 15 a third arithmetic circuit for determining the phase difference based on the first and second correlations.

2. The correlator of claim 1, wherein the third arithmetic circuit divides the first correlation by the second correlation.

3. The correlator according to claim I or 2, wherein the first combined code 20 generator applies first weighting to a plurality of phase-shifted occurrences of the reference spreading code on the basis of values obtained by sampling one period of a sine-wave signal in units in which the phase shift is performed and then combines the plurality of phaseshifted occurrences of the reference spreading code after being weighted.

) (

4. The correlator of claim I, 2 or 3, wherein the second combined code generator applies second weighting to a plurality of phase-shifted occurrences of the spreading codes on the basis of values obtained by sampling one period of a cosine-

wave signal in units in which said phase shift is performed and then combines the 5 plurality of phase-shifted occurrences of the reference spreading code after being weighted.

5. The correlator of any preceding claim wherein the first arithmetic circuit includes: a multiplier for multiplying the received spreading code and the first 10 combined spreading code; and an integrator for integrating an output of the multiplier to produce the first correlation.

6. The correlator according to any preceding claim, wherein the second arithmetic circuit includes: 15 a multiplier for multiplying the received spreading code and the second combined spreading code; and an integrator for integrating an output of the multiplier to provide the second correlation.

7. The correlator of any preceding claim, which in a case where multipath 20 signals constitute noise in phase detection and are obstacles to accurate detection of said phase difference between the received spreading code and the reference code, further includes: a first phase detection circuit for discriminating, on the basis or a pnase difference, a phase area in which the phase difference resides;

( a sliding correlator for searching within the phase area sequentially to output correlation values of different code phases; and a second phase detection circuit which finds the code phase for which the correlation between the received spreading code and the reference code is maximized.