GB2385220A

GB2385220A - Logic circuits using polycrystalline semiconductor thin film transistors

Info

Publication number: GB2385220A
Application number: GB0203194A
Authority: GB
Inventors: Mujahid Islam
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2002-02-11
Filing date: 2002-02-11
Publication date: 2003-08-13
Also published as: GB0203194D0

Abstract

A large scale integrated (LSI) or a very large scale integrated (VLSI) logic circuit comprises a plurality of polysilicon tin film transistors TFTs. The circuit, which may include a delay circuit, is asynchronous and does not comprise a clock. Thus, operations to be performed by the TFTs need not be performed within a single clock period - rather the operation of each stage of TFTs in the circuit is dependent on receiving a signal either from an input to the circuit or from a preceding stage in the circuit. Problems with variations in the threshold voltage between the TFTs are therefore avoided.

Description

LOGIC CIRCUITS USING POLYCRYSTALLINE SEMICONDUCTOR THIN FILM TRANSISTORS The present invention relates to digital logic circuits using thin film transistors (TFTs) formed using a polycrystalline semiconductor film, such as polysilicon TFTs in which the film is polycrystalline silicon.

Polysilicon TFTs are well known and the structure of a conventional N-type TFT 10 will be explained with reference to Fig. 1.

As illustrated in Fig. 1, a bedding protective film 51 made of a silicon oxide film is formed on a surface of a substrate 50. On the surface of this bedding protective film 51, a polycrystalline semiconductor film 100 is formed that is patterned into island forms. On the surface of the semiconductor film 100, a gate insulating film 12 is formed, and a gate electrode 14 is formed on the surface of this gate insulating film 12. In the semiconductor film 100, a channel region 15 is formed at a region facing the gate electrode 14 through the gate insulating film 12. At the sides of this channel region 15, a high concentration source region 16 and a high concentration drain region 17 are formed in a self-aligned condition relative to the gate electrode 14. To the high concentration source region 16 and high concentration drain region 17, a source electrode 41 and a drain electrode 42 are respectively electrically connected through contact holes in an interlayer insulating film 52.

Such polysilicon TFTs have an advantage over field effect transistors (FETs) formed with a single crystal semiconductor, such as MOS transistors, in that they can be inexpensively produced since the constraints of producing a satisfactory single crystal silicon substrate are avoided. The transistors can be fabricated on any suitable insulating substrate, such as glass sheet. It follows that the size constraints necessitated by the production of a single crystal are obviated, so that large numbers of TFTs can be produced using a single polysilicon film fabricated on a single inexpensive insulating substrate.

However, polysilicon TFTs have the significant problem that they have widely varying threshold voltages, even when manufactured in the same batch and using a common polysilicon film. The threshold voltage is effectively the voltage applied to the gate electrode 14 at which current can flow through the channel region 15 of the TFT and so determines the ON-state of the TFT. This threshold voltage is in turn determined by the semiconductor film material.

In integrated circuits comprised of single crystal silicon FETs, the single crystal structure is substantially the same for all of the FETs and, consequently, FETs of the same construction will have substantially the same threshold voltage. This effect can be further improved, as required, by the closer proximity of the single crystal FETs to each other on the integrated circuit.

In contrast, in polysilicon TFTs it is difficult to guarantee continuity of individual crystal sizes in the polysilicon film. Furthermore, there are also variations in substrate purity. Thus, the polysilicon film material varies between TFTs, even when the TFTs are formed using the same polysilicon film. This variation in substrate purity, and more particularly in the number of grain boundaries of the crystals in the polysilicon film, affects the threshold voltage, no matter how close the mutual proximity of the polysilicon TFTs on the integrated circuit. Accordingly, threshold voltage varies considerably between polysilicon TFTs, even when using adjacent transistors on a common substrate. Polysilicon TFTs also show other parameter variations, such as saturation current variations, for similar reasons. As a consequence of these parameter variations, there have been considerable problems in implementing digital logic circuits and, in particular, large scale integrated (LSI) or very large scale integrated (VLSI) digital circuits using polysilicon TFTs and this has inhibited the adoption of such transistors for many digital circuit applications.

Moreover, LSI digital circuits are conventionally designed to have synchronous logic.

In such synchronous logic circuits, the timing of all switching operations performed by the circuit transistors is controlled by clock pulses generated by a master clock. Thus, synchronous logic circuits operate on a fixed cycle operation in which a fixed time is assigned in advance to each operation to be performed. Because all of the transistors are clocked by the master clock, all operations to be performed by the transistors of the circuit must be performed within one clock period. However, the variation in threshold voltage and other parameters between polysilicon TFTs leads to a variation in the logic delay of such polysilicon TFT circuits. As a consequence, it is difficult to guarantee that each operation to be performed by the polysilicon TFTs, if polysilicon TFTs are used in conventional synchronous digital logic circuits, will occur during one clock period and hence that the circuit will function to design requirements. This problem is further compounded in LSI digital circuits comprising polysilicon TFTs, since the large number of polysilicon TFTs necessarily required leads to an even greater variation in logic delay for the circuit.

In contrast, since single crystal FETs are formed using a single crystal as the substrate, the variation in threshold voltage and other parameters between single crystal FETs is considerably smaller, in comparison to TFTs, and hence the variation in logic delay is correspondingly reduced. Thus, the implementation of functional digital circuits has been considered to be significantly eased by using ICs comprised of single crystal FETs. However, as discussed above, the use of a single crystal poses problems in that it is not at present possible to manufacture LSI circuits using single crystals to the desired large size. It follows therefore that the single crystal solution is restricting the size of the circuits which can be produced. Single crystal FETs are also more expensive to manufacture than polysilicon TFTs, since growth of the single crystal requires different manufacturing conditions and greater accuracy. This can become of significant importance in VLSI circuits where several million transistor devices may be necessary to carry out the circuit function. Furthermore, because the TFTs can be fabricated on an insulating substrate rather than on a semiconductor substrate, the bulk capacitance of the transistor devices is reduced, in comparison to MOS transistors, and hence the operating speed of the transistor devices can be increased. Again, this is a desirable feature for VLSI logic circuits as the circuits can then be operated at a higher speed, reducing processing time.

Asynchronous logic circuits, which are not clocked, are known. However, very few LSI circuits have been designed which use asynchronous techniques. This is because synchronous logic has the general advantage that fewer and simpler circuits are required to implement it, which conflicts to a lesser degree with the size constraints imposed by the restricted size of the single crystal substrates. Thus, synchronous logic has been commonly adopted for logic circuits. Moreover, because synchronous logic requires fewer and simpler circuits, it has been possible to implement accurate logic using single crystal FETs.

However, there is an increasing need for digital logic circuits to carry out increasingly complex tasks which means that the circuits are becoming more complex, which in turn means that a larger number of transistors are required to complete the logic operations. A methodology which overcomes the size constraints presented by the use of single crystal MOS circuits, such as may be provided by the use of TFTs, is seen therefore as being particularly advantageous. However, for the reasons outlined above, the use of polysilicon TFTs in synchronous logic LSI digital circuits has been considered unworkable. Hence, the use of polysilicon TFTs and the adoption of asynchronous methodology for LSI digital circuits is hitherto unknown.

According to a first aspect of the present invention, there is provided a polycrystalline semiconductor thin film transistor asynchronous logic circuit comprising an array of logic blocks including a first logic block for performing a logic operation and for providing logic output signals to a second logic block, wherein the second logic block is arranged not to commence its logic operation until the first logic block has completed its logic operation.

According to a second aspect of the present invention, there is provided a method of performing asynchronous logic comprising providing an asynchronous logic circuit of polycrystalline semiconductor thin film transistors arranged as an array of logic blocks including a first logic block performing a logic operation and providing logic output signals to a second logic block and arranging the second logic block not to commence its logic operation until the first logic block has completed its logic operation.

Embodiments of the present invention will now be described by way of further example only and with reference to the accompanying drawings, in which: FIG. I is a schematic cross-sectional view of a conventional polysicoh thin film transistor; FIG. 2 is a functional schematic diagram of a logic circuit; FIG. 3 is a timing diagram showing the clock period used for the circuit illustrated in FIG. 2.

FIG. 4 illustrates schematically a logic block for use in the present invention.

FIG. 5 is a circuit diagram of a delay element for use in a TFT logic circuit in accordance with the present invention; FIG. 6 is a circuit diagram of an alternative embodiment of a delay element for use in a TFT logic circuit in accordance with the present invention; and FIG. 7 is a circuit diagram of a third embodiment of a delay element for use in a TFT logic circuit in accordance with the present invention.

Figure 2 illustrates schematically a typical LSI digital circuit 20, which is operated using synchronous methodology. The digital circuit comprises a logic circuit 22 coupled in series between two D-type flip flop circuits 24 and 26. The clock period required for the circuit to function can be determined with reasonable accuracy when single crystal transistors are used because the switching delays associated with each transistor, being fabricated on a single crystal substrate, are relatively constant and, therefore, quantifiable. The clock period T is therefore usually allocated so as to equal the delay 28 of the flip flop circuit 24, the set up time 30 for the flip flop 26, the delay 32 of the logic circuit, plus a relatively small period of

r

spare time 34. The spare time is allocated to accommodate, for example, the difference in time for a common clock pulse to arrive at both D-type circuits, which might be physically located at opposite ends of the overall integrated circuit. This is commonly referred to in this art as clock skew. Such a clock period is shown in Figure 3.

If TFT transistors are used to provide the circuit, the variations in delay of the various circuit components become very large and it becomes difficult to allocate a clock period which will guarantee operation of the circuit. If a long clock period is allocated which is predicted to confidently accommodate the critical path circuit delays, the overall circuit operation is likely to become too slow for practical use.

With the present invention, it has been realised that if asynchronous methodology is adopted, and if each stage of the circuit is triggered by the completion of the operation of the preceding stage, then the circuit will be able to complete its required function taking into account the variable operational delays of the various circuit elements. Furthermore, the speed at which the circuit function is completed is determined by the critical path delay of the circuit elements and is not governed by an externally determined and arbitrary clock period, which may be of unnecessarily long duration. This enables LSI digital circuits to be implemented using TFTs and therefore overcomes the size constraints arising from the use of single crystal silicon substrates.

Figure 4 shows schematically two logic blocks 60 and 62, together with an interface circuit 64 suitable for use in an asynchronous logic circuit according to the present invention.

In the embodiment shown, each logic block 60 and 62 is provided with a respective enable input terminal 66,68. Each logic block 60,62 represents a stage in the overall logic circuit and, as will be appreciated by a person familiar with this art, is configured as an array of logic gates to perform a respective logic function. Each of the logic blocks 60,62 is provided, in the example shown, with three input and three output terminals and the respective output terminals of one logic block are coupled to respective input terminals of the next logic block by two parallel conductive paths because two bit logic is used to communicate between the logic blocks in the logic circuit according to this embodiment of the present invention.

By using two bit logic, the following exemplary encoding may be used to convey information between the various parts of the circuit. The binary combination 00 can be used to indicate that a part of the circuit is not ready; the binary combinations 01 and 10 can be used to respectively represent logic 0 and 1, or vice versa; and the binary combination 11 can

be used to indicate a'not allowed'condition, such as, for example, to show that a fault has occurred in the circuit.

The interface circuit 64 shown in Figure 4 comprises OR gates 70,72 and 74, which have their inputs coupled respectively to output terminals outl, out2 and out3 of logic block 60. Hence, the OR gates 70,72 and 74 receive the binary output signals fed to logic block 62 from logic block 60.

The interface circuit 64 also includes OR gate 76, which is arranged to receive binary output signals from a logic block of a preceding stage (not shown) of the logic circuit. The outputs of OR gates 70,72 and 74 are fed to a delay element A which is designed such that when the output signals from OR gates 70,72 and 74 are all logic ZERO, the output signal from delay element A is also logic ZERO, and when the output signals from OR gates 70,72 and 74 are all logic 1, the output signal from delay element A is also logic 1. However, delay element A is arranged such that its output will only return to logic ZERO when the output signals from OR gates 70,72 and 74 have all returned to logic ZERO. If the signal at the outputs of any one of OR gates 70,72 and 74 remains at logic 1, the output of the delay element A will remain at logic 1. From figure 4 it can also be seen that the interface circuit 64 also receives output signals from a preceding stage via the OR gate 76. This receipt of binary output signals from a preceding stage is shown by way of example and is intended to indicate that any logic block in the logic circuit, logic block 62 in this example, may require to receive logic signals from not only the immediately preceding stage of the overall circuit but also from another preceding stage of the circuit. However, it should be realised that any logic block of the circuit may require output logic signals from the immediately preceding stage only, in which case the OR gate 76 and delay element B would not be provided.

It can be seen from Figure 4 that the output of OR gate 76 is coupled to one input of delay element B, which is also arranged to receive on a second input the output signal from delay element A.

Delay element B is configured to operate in a similar manner to delay element A in that the output signal from delay element B will remain at logic ZERO until the outputs from delay element A and OR gate 76 are both logic 1, and the output from delay element B will remain at logic 1 until the output signals from both delay element A and OR gate 76 return to logic ZERO.

The interface unit 64 functions as follows.

It is assumed that logic block 60 comprises of three respective circuit paths, CP1, CP2, CP3, between input terminals inl to in3 and output terminals outl to out3, each path being configured by a series of logic gates fabricated using TFTs. It is also assumed that the circuit path CP1 between terminals inl and outl is able to complete its switching operations in less time than the circuit path CP2 between terminals in2 and out2, which in turn is able to complete its switching operations in less time than the circuit path CP3 between terminals in3 and out3.

Circuit path CP 1 will therefore complete its logic operations first, and the required logic output, for example logic 1 represented by the code 10, will be passed to OR gate 70.

The output of OR gate 70 switches therefore to logic 1 and is passed to one input of delay element A. However, the output from delay element A remains at logic ZERO because the output signals from output terminals out2 and out3 both indicate that circuit paths CP2 and CP3 have not completed their operations by providing the code 00 and hence the output signals from OR gates 72 and 74, which are input to delay element A, remain at logic ZERO.

When circuit paths CP 1 and CP2 have also completed their logic operations, the output signals on output terminals out2 and out3 will change from code 00 to, for example, code 01, indicating that the logic output from terminals out2 and out3 are both logic ZERO, the output signals of OR gates 72 and 74 will also switch to logic 1 and the output signal from delay element A will then switch from logic ZERO to logic 1. If it is assumed that the output signal from OR gate 76 is already at logic 1, the signals at both input terminals to delay element B will be logic 1, and the output signal from delay element B will switch from logic ZERO to logic 1.

Delay element B, in switching from logic ZERO to logic 1 at its output, signifies that the logic operations of the immediately preceding stage, namely logic block 60, and the preceding stage (not shown) coupled to OR gate 76 are complete. The output signal from delay element B can then be used as a trigger for logic block 62 to commence its logic operations.

It can be seen therefore that by using asynchronous logic, the logic operations of the logic circuit as a whole are completed in the shortest time possible, but compensating for the variability in the TFT characteristics, because each stage commences its operations only when it is told that the preceding stages on which it relies have each completed their respective operations.

Figures 5,6 and 7 all show embodiments of delay circuits suitable for use as delay elements A and B of figure 4 fabricated from polysilicon TFTs. No single crystal FETs are used.

Thus, in an asynchronous logic circuit according to the present invention, since the operation of each stage is dependent on receiving a signal from a preceding stage indicating that the preceding stage has completed its operation, the problems of variations in threshold voltage and other parameters associated with the use of polysilicon TFTs are overcome.

Thus, the most attractive features of polysilicon TFTs can be fully utilised. These include reduced manufacturing costs and increased yield in the manufacturing process, a lowering of the size constraints presently imposed on LSI and VLSI circuits and the ability to use a larger size of integrated circuit for such circuits. Moreover, the use of TFTs imparts greater reliability to such circuits. Since there is no need to perform each operation in one clock period and to delay the performance of a subsequent operation until the next clock period, an asynchronous logic circuit according to the present invention can have the benefit of a faster processing speed than a conventional logic circuit. In addition, the parts of the circuit run only when needed and not when clocked by the clock pulse. Consequently, an asynchronous TFT logic circuit according to the present invention also exhibits reduced power consumption. This is particularly advantageous where the logic circuit is to be used as part of a portable, hand-held device operating from an integral voltage supply, such as a laptop computer or a mobile phone.

Moreover, the use of polysilicon TFTs need not be confined to the LSI logic circuits themselves but, as is apparent from figures 5,6 and 7, may also be used to implement the delay elements used in combination with such circuits. Rather, a large number of circuits having widely differing functions and using only polysilicon TFTs can be implemented using asynchronous circuit design methodology.

The aforegoing description has been given by way of example only and it will be appreciated by a person skilled in the art that modifications can be made without departing from the scope of the present invention. For example, a succeeding stage may sense that a preceding stage has completed its operation by sensing that an output signal from the preceding stages changes from a first level to a second level, such as a high level to a low level, or vice versa.

Additionally, in the embodiments described, a two wire system and two bit logic have been used to convey data and data completion. However, other encoding systems may also be used for this purpose, such as 1 of 4 or 3 of 7 encoding.

Furthermore, the logic gates of the interface circuit 64 are shown as OR gates.

However, other configurations of logic gates may be used, as will be apparent to a person skilled in this art.

Claims

CLAIMS 1. A polycrystalline semiconductor thin film transistor asynchronous logic circuit comprising an array of logic blocks including a first logic block for performing a logic operation and for providing logic output signals to a second logic block, wherein the second logic block is arranged not to commence its logic operation until the first logic block has completed its logic operation.
2. An asynchronous logic circuit according to claim 1 wherein the second logic block is arranged to receive a further signal for indicating that the first logic block has completed its logic operation and the second logic block is further arranged not to commence its logic operation until receipt of the further signal.
3. An asynchronous logic circuit according to claim 2 comprising an interface circuit coupled to the first and second logic blocks and arranged to receive the logic output signals from the first logic block and not to provide the further signal until all of the logic output signals from the first logic block indicate that the first logic block has completed its logic operation.
4. An asynchronous logic circuit according to claim 3, wherein the interface circuit is further arranged to receive a logic output signal from a further logic block of the array and is arranged not to provide the further signal until receipt of the logic output signal from the further logic block.
5. An asynchronous logic circuit according to claim 3 or 4, wherein the interface circuit comprises an array of logic gates coupled in series with a delay circuit.
6. An asynchronous logic circuit according to any one of the preceding claims, wherein the logic blocks are arranged to provide logic output signals in binary form comprising of at least two bits such that the logic output signals can be used to signify logic ONE, logic ZERO, a not ready condition, and an unacceptable condition for each logic block.

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7. An asynchronous logic circuit according to claim 6 wherein logic blocks of the array are interconnected using interconnects comprising a number of conductive paths corresponding to the number of bits used for the logic output signals.
8. An asynchronous logic circuit according to claim 7, or claim 6 when appendant to claim 5, wherein the array of logic gates comprises OR gates arranged to receive the at least two bit logic output signals.
9. An asynchronous logic circuit according to any one of the preceding claims, wherein said circuit comprises no transistors other than polycrystalline semiconductor thin film transistors.
10. An asynchronous logic circuit according to any one of the preceding claims, wherein said asynchronous logic circuit is a large scale integrated or a very large scale integrated digital logic circuit.
11. An asynchronous logic circuit according to any one of the preceding claims, wherein said semiconductor includes polysilicon as an active layer.
12. An asynchronous logic circuit as described herein with reference to and as illustrated in any one of figures 4 to 7 of the accompanying drawings.
13. A method of performing asynchronous logic comprising providing an asynchronous logic circuit of polycrystalline semiconductor thin film transistors arranged as an array of logic blocks including a first logic block performing a logic operation and providing logic output signals to a second logic block and arranging the second logic block not to commence its logic operation until the first logic block has completed its logic operation.
14. A method according to claim 13 comprising providing the second logic block with a further signal for indicating that the first logic block has completed its logic operation and arranging the second logic block so that it does not commence its logic operation until receipt of the further signal.

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15. A method according to claim 14 comprising arranging an interface circuit between the first and second logic blocks such that the interface circuit receives the logic output signals from the first logic block but does not provide the further signal until all of the logic output signals from the first logic block indicate that the first logic block has completed its logic operation.
16. A method according to claim 15, wherein the interface circuit is also arranged to receive a logic output signal from a further logic block of the array and is arranged not to provide the further signal until receipt of the logic output signal from the further logic block.
17. A method according to claim 15 or 16, wherein the interface circuit is provided in the form of an array of logic gates coupled in series with a delay circuit.
18. A method according to any one of claims 13 to 17 comprising providing logic output signals in binary form having at least two bits such that the logic output signals are used to signify logic ONE, logic ZERO, a not ready condition for a logic block, and an unacceptable condition for a logic block.
19. A method according to claim 18 comprising providing interconnects between the logic blocks having a number of conductive paths equal to the number of bits of the logic output signals.
20. A method according to claim 19, or claim 18 when appendant to claim 17, wherein the logic gates are provided as OR gates arranged to receive the at least two bit logic output signals.
21. A method according to any one of claims 13 to 20 comprising providing the asynchronous logic circuit so as to comprise no transistors other than polycrystalline semiconductor thin film transistors.

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22. A method according to any one of claims 13 to 21, wherein the asynchronous logic circuit is provided as a large scale integrated or a very large scale integrated digital logic circuit.
23. A method according to any one of claims 13 to 22, wherein said semiconductor is selected to comprise polysilicon as an active layer.
24. A method as described with reference to any one of figures 4 to 7 of the accompanying drawings.