GB2385201A - Noise suppression for open bit line dram architectures - Google Patents

Noise suppression for open bit line dram architectures

Info

Publication number
GB2385201A
GB2385201A GB0310604A GB0310604A GB2385201A GB 2385201 A GB2385201 A GB 2385201A GB 0310604 A GB0310604 A GB 0310604A GB 0310604 A GB0310604 A GB 0310604A GB 2385201 A GB2385201 A GB 2385201A
Authority
GB
United Kingdom
Prior art keywords
bit line
dram
cells
coupling
approach
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0310604A
Other versions
GB0310604D0 (en
GB2385201B (en
Inventor
Shih-Lien Lu
Dinesh Somasekhar
Vivek De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to GB0425947A priority Critical patent/GB2406197B/en
Priority to GB0425949A priority patent/GB2406198B/en
Priority to GB0425950A priority patent/GB2406199B/en
Publication of GB0310604D0 publication Critical patent/GB0310604D0/en
Publication of GB2385201A publication Critical patent/GB2385201A/en
Application granted granted Critical
Publication of GB2385201B publication Critical patent/GB2385201B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
GB0310604A 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures Expired - Fee Related GB2385201B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0425947A GB2406197B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425949A GB2406198B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425950A GB2406199B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/690,513 US6496402B1 (en) 2000-10-17 2000-10-17 Noise suppression for open bit line DRAM architectures
PCT/US2001/031159 WO2002033706A2 (en) 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures

Publications (3)

Publication Number Publication Date
GB0310604D0 GB0310604D0 (en) 2003-06-11
GB2385201A true GB2385201A (en) 2003-08-13
GB2385201B GB2385201B (en) 2005-04-27

Family

ID=24772765

Family Applications (4)

Application Number Title Priority Date Filing Date
GB0310604A Expired - Fee Related GB2385201B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line dram architectures
GB0425947A Expired - Fee Related GB2406197B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425950A Expired - Fee Related GB2406199B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425949A Expired - Fee Related GB2406198B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures

Family Applications After (3)

Application Number Title Priority Date Filing Date
GB0425947A Expired - Fee Related GB2406197B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425950A Expired - Fee Related GB2406199B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures
GB0425949A Expired - Fee Related GB2406198B (en) 2000-10-17 2001-10-03 Noise suppression for open bit line DRAM architectures

Country Status (8)

Country Link
US (2) US6496402B1 (en)
CN (3) CN101330086B (en)
AU (1) AU2002211437A1 (en)
DE (1) DE10196802B4 (en)
GB (4) GB2385201B (en)
HK (1) HK1055506A1 (en)
TW (1) TW529027B (en)
WO (1) WO2002033706A2 (en)

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Also Published As

Publication number Publication date
CN101330086A (en) 2008-12-24
GB0425950D0 (en) 2004-12-29
WO2002033706A2 (en) 2002-04-25
DE10196802T5 (en) 2004-04-15
AU2002211437A1 (en) 2002-04-29
CN101330086B (en) 2011-02-23
GB2406197A (en) 2005-03-23
GB2406198B (en) 2005-05-18
GB2406198A (en) 2005-03-23
DE10196802B4 (en) 2013-06-06
GB0425949D0 (en) 2004-12-29
CN1572002A (en) 2005-01-26
CN100511474C (en) 2009-07-08
US6721222B2 (en) 2004-04-13
GB2406199A (en) 2005-03-23
GB2406197B (en) 2005-06-08
GB0310604D0 (en) 2003-06-11
CN101329904B (en) 2012-01-25
HK1055506A1 (en) 2004-01-09
CN101329904A (en) 2008-12-24
GB2406199B (en) 2005-05-18
US6496402B1 (en) 2002-12-17
GB0425947D0 (en) 2004-12-29
TW529027B (en) 2003-04-21
GB2385201B (en) 2005-04-27
WO2002033706A3 (en) 2003-04-17
US20030072172A1 (en) 2003-04-17

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