GB2378331A

GB2378331A - Digital filter for multi-rate communication

Info

Publication number: GB2378331A
Application number: GB0118414A
Authority: GB
Inventors: Paul Howard
Original assignee: IPWireless Inc
Current assignee: IPWireless Inc
Priority date: 2001-07-30
Filing date: 2001-07-30
Publication date: 2003-02-05
Also published as: GB0118414D0

Abstract

A method for digital filtering in a communication unit includes the step of providing a sequence of delay registers, Z<SP>-D</SP> 630 in a forward path of an infinite impulse response digital filter 522, where D is greater than 1. A digital filter arrangement and an infinite impulse response filter are also provided. This provides the advantage that it is now possible to implement an IIR filter that can provide extra delays (in a similar manner to a FIR structure) without changing or affecting the transfer response. In particular, the invention is applicable to multi-rate filtering operations, for example in digital wireless communication systems and units.

Description

DIGITAL FILTER FOR MULTI RATE COMMUNICATION Field of the Invention The present invention is directed to the provision of multiple data rates in a high capacity communication system. The invention is applicable to, but not limited to, a digital filter arrangement to facilitate multiple data rate communication in a cellular wireless Internet access based communication system.

Background of the Invention Wireless communication systems, for example cellular telephony or private mobile radio communication systems, typically provide for radio telecommunication links to be arranged between a plurality of base transceiver stations (BTSs) and a plurality of subscriber units. The term subscriber unit generally includes both hand-portable and vehicular mounted radio units.

Wireless communication systems are distinguished over fixed communications systems, such as the public switched telephone networks (PSTN), principally in that subscriber units move between service providers (and/or different BTS) and in doing so encounter varying radio propagation environments.

In a wireless communication system, each BTS has associated with it a particular geographical coverage area (or cell). The coverage area defines a particular range that the BTS can maintain acceptable communications with subscriber units operating in its serving cell.

Often these cells combine to produce an expanded system coverage area, with the infrastructure supporting respective cells interconnected via centralised switching equipment. Furthermore, such infrastructure is often operably coupled into the public telecommunications network, to provide communication to or from fixed communication terminals. In particular, such communication links can now provide Internet-access to users.

There is disclosed in co-pending U. S. patent application, Serial No. 09/432,824, filed November 2,1999, assigned to the present applicant, and published in equivalent form as European patent publication EP1098539, a cellular wireless Internet-access based communication that can be adapted to benefit from the inventive concepts of the present invention.

A particular focus of the aforementioned patent application is to better utilise multiple frequencies within a given spectrum allocation. One such spectrum allocation is known as the"MMDS"for multi-channel, multi-point distribution service in the United States of America, which is in the 2.50-2. 68 GHz frequency range.

One requirement of this particular wireless communication

system is that the wireless system must be capable of operating over a number of bandwidths or frequencies.

A designer of communication equipment, that is capable of being used in such a variable-bandwidth communication system, must consider the requirement for the circuits and circuit elements to be able to operate across a wide frequency range as well as cope with more than one signal bandwidth.

In particular, the frequency selective components and circuits, such as filters, require special consideration.

Furthermore, due to the large number of filter arrangements that will be used in the communication units, it is important to design an adaptable, economical and efficient filtering configuration.

In the field of filter design, filters can be divided into two distinct areas-analogue filters and digital filters. In wireless communication products, analogue filters are predominantly (but not solely) found in radio frequency circuits, where the high frequencies/bandwidths (and therefore very high sampling rates) required of digital filters are not fast enough to enable processing of the signals. However, with the increase in processing power, most baseband filtering circuits in communication products utilise digital filters to perform their frequency selective functions. Furthermore, as they are often software-based, the frequency responses can be carefully controlled and dynamically adjusted.

A digital filter may be realised in either'hardware'or a'software'form. In a hardware form, a suitable set of digital (logic) electronic circuits is interconnected to provide the essential building blocks of a digital filtering operation-implementing storage, delay, addition, subtraction, and multiplication functions by use of various electronic gates and constant values.

Recent developments in electronics allow a complete digital filter to be constructed in such an integrated circuit form. A major advantage of using such specialpurpose hardware, dedicated to a particular signalprocessing task, is speed-particularly if some of the necessary operations are performed in parallel.

The alternative,'software', approach is to program a general-purpose microprocessor as a digital filter. A benefit in using software digital filters is that signals, records and data may be stored and subsequently processed'off-line'.

To better understand the benefits of the present invention, it is worth noting that there are two rather distinct methods in which a sampled-data signal may be filtered. The first involves taking the Discrete Fourier Transform (DFT) of the signal, generally by use of a Fast Fourier Transform (FFT) algorithm. Having found the signal spectrum of a received signal, the magnitudes and phases of its various frequency components may then be adjusted in accordance with the desired filter characteristics. The filtered time-domain signal is then evaluated by an inverse transformation-again using the

FFT.

In this first method, the filtering may be considered to take place in the frequency-domain. It is an important and widely used approach, which allows great flexibility in the choice of filter characteristics. Since the signal spectrum is simply multiplied by the desired filter characteristic, it often proves faster than the equivalent time-domain convolution. On the other hand, its flexibility is not needed for many practical filtering tasks, and time-domain filtering, as discussed below, is often preferable.

The second method of implementing a digital filter, which is a focus of the present invention, is to perform the filtering operation in the time-domain. In effect, this is done by convolution of the input signal with the impulse response of the appropriate filter. Whether a time-domain or a frequency-domain filter is more appropriate depends upon a number of factors such as the storage available in the computer, the duration of the signal, the operating speed, and whether or not a'realtime'operation is required.

In such an operation, a new output sample value is calculated every time an input sample is generated, due to efficient use of FFT storage and processing of substantial blocks of data.

Digital filters are commonly designed by first choosing a transfer function H (z) which represents a useful

frequency-response characteristic. Knowing H (z), it is a relatively simple matter to derive the time-domain formula that describes the operation of the filter.

The usual way of choosing a suitable transfer function H (z) for a particular filtering task is to specify a set of z-plane poles and zeros. A sampled-data signal can be represented by such poles and zeros, and its frequency spectrum inferred by considering the changes in lengths and phase of vectors drawn from the various poles and zeros to points on the unit circle (representing a series of sinusoidal frequencies), as known to those skilled in the art.

The time domain aspect of digital filtering can also be divided into two classes known as finite impulse response (FIR) or infinite impulse response (IIR).

Referring first to FIG. 1, a prior art FIR filter 100 is shown. As can be seen, FIR filters are inherently stable, as they do not involve any feedback path for signals. As such, they are generally termed nonrecursive filters.

The FIR class of filters has the form of a number of delay stages 130, with positive or negative multipliers 120, in conjunction with combiners 160 to add the various multiplied and delayed samples. The output 170 is a function of past and present input 110 samples. The art of designing such a FIR filter lies in the ability to

specify a minimum number of delay and multiplier elements to achieve an acceptable filter performance.

One common difficulty associated with the implementation of FIR filters is the speed requirements of the weighting sections (multiplying by the b coefficients) 120 and the combiners 160 used to add the weighted input samples together. This is because this basic form of a FIR filter does not allow for the propagation of the sum through the cascaded adders. It is noteworthy that the delay elements only allow delays of one clock cycle for the computation of the output sample before a new input sample 110 is clocked in.

The basic filter form has a limited clock rate determined by the propagation delay through the combiners 160 and multipliers 120. To address this problem, a technique known as pipelining can be adopted. Pipelining inserts additional delay elements 140,150 into the structure to minimise the number of cascaded stages, as shown in FIG.

1. This allows the filter to operate at a higher clock speed at the expense of additional delay elements.

FIG. 1 shows the structure of a pipelined FIR filter that

has incorporated two additional delay functions, Z-A 140 and Z'150. The delay element Z-A140 is added to allow sufficient time ('A'extra clock cycles) for the adders to function ; Z~B 150 is added to allow sufficient time ('B'extra clock cycles) for the multipliers to function.

Equation [1] (below) is the transfer function of the

pipelined structure and it shows the effect that adding the extra delay elements 140,150 only increases the delay through the filter.

The magnitude of the frequency response is not affected because the locations of the zeros do not change. The total extra delay is AB clock cycles.

Pipelining can be applied to FIR filters because they are non-recursive. This means that if additional delay is required in branch x, to allow extra time for the output to be generated, then the effect of this additional delay can be counteracted by duplicating the delay in all paths that require the result from branch x.

In general, the design of such filters is discussed in a text by Proakis and Manolakis, Digital Signal Processing, Principles, Algorithms and Applications, 2nd edition, Macmillan, NY, 1992. In addition, from a design standpoint, computer-based simulation design tools are widely available for designing digital filters, for example the MATLAB product by MathWorks of Boston, Massachusetts.

Referring now to FIG. 2, a known infinite impulse response structure 200, which is a transposed direct form Infinite Impulse structure, is shown. In contrast to the

FIR filter, the output 270 from an IIR filter is a function of past output samples as well as the present input sample 210. Thus, feedback is present, and as a consequence IIR filters are referred to as recursive networks. The input samples are delayed (by delay elements 230) and the output is fed back to the input via multiplier elements 220 and combiners 260. Any digital filter that is specified in terms of one or more z-plane poles (or more specifically uncancelled poles), has an infinite impulse response.

A realisable IIR filter cannot be symmetrical in form as it cannot start before't=0'. Therefore, IIR filters cannot display pure linear-phase characteristics. The major advantage of IIR filters is that the filter designer can position one or more poles inside the unit circle, as known to skilled artisans, to achieve very selective filter passband characteristics.

Since the IIR filter is a recursive design it is not possible to insert extra delays as in the FIR structure without changing or affecting the transfer response. The transfer function is given in Equation [2].

Hence, in the context of the present invention the use of IIR filters cannot be considered, particularly in relation to the changes in the IIR transfer function that

would result from the filter being required to operate in over multiple bandwidths/high-data speeds.

The prior art IIR structure in FIG. 2 is efficient in terms of the propagation delays of the multipliers and adders since all multiplier operations occur in parallel and all adders are inherently pipelined by one delay element. Also, there is steep roll-off with few sections required. In hardware implementations, multiply operations are often carried out by combination of shift and adds which removes the need to physically implement a multiply structure.

Although this approach saves hardware, it does mean that the propagation delay of these stages is large since the result has to ripple through a number of add/subtract stages. As discussed above, and critically to a designer attempting to design a flexible and multiple speed/bandwidth digital filter design, it is not possible to directly pipeline (for greater throughput) an IIR filter implementation without affecting the pole locations.

It is possible to use an efficient class of FIR filters for multi-rate systems that support chip-rates related by integer powers of 2. An example of such a class of FIR filters are the family of filters known as'half-band' filters. However, even the efficient FIR filter structures require many more sections to obtain specific rejection when compared to an IIR implementation.

A need therefore exists for an improved filtering process, in particular one that allows additional delays to be incorporated into an IIR filter structure without changing the IIR filter transfer function, for use in a multi-bandwidth radio communication system wherein the abovementioned disadvantages may be alleviated.

Statement of Invention In accordance with a first aspect of the present invention, there is provided a method for digital filtering in a communication unit, as claimed in claim 1.

In accordance with a second aspect of the present invention, there is provided a storage medium storing processor-implementable instructions, as claimed in claim 13.

In accordance with a third aspect of the present invention, there is provided an infinite impulse response digital filter, as claimed in claim 14.

In accordance with a fourth aspect of the present invention, there is provided a digital filter arrangement, as claimed in claim 17.

In accordance with a fifth aspect of the present invention, there is provided a communication system, as claimed in claim 24.

In accordance with a sixth aspect of the present invention, there is provided a communication unit, as claimed in claim 27.

Further aspects of the present invention are as claimed in the dependent claims.

In summary, the present invention aims to provide a digital filtering arrangement, particularly for use in a high data-rate, multiple bandwidth digital wireless communication system.

In particular, a digital filter arrangement is described for use in a communication system having at least two operating bandwidths. The digital filter arrangement, includes a first filtering path incorporating an analogue-to-digital converter directly coupled to a finite impulse response filter arranged to provide the desired channel selection filtering at the highest of the at least two radio frequency operating bandwidths. A second filtering path, incorporating the analogue-todigital converter coupled to the finite impulse response filter includes an infinite impulse response filter having a sequence of delay registers, Z- (where D > = 1) in a forward path of a said infinite impulse response filter.

Hence, the IIR filter in the new filter arrangement encompasses known IIR filters and the new IIR filter according to a preferred embodiment of the present invention. In this manner, the first path incorporates a

minimal number of components and is designed to operate at the highest bandwidth of the digital filter arrangement. Subsequent path (s) are designed to provide adequate filtering of lower data-rate signals, whilst utilising the components optimised for the highest datarate. In general, the FIR filter 540 is the section that is most economically re-used.

An infinite impulse response digital filter is also described, for example, for use in the second path of the above digital filter arrangement. The infinite impulse response digital filter includes a sequence of delay registers, Z-D (where D > 1) in a forward path of said digital filter.

Furthermore, a method for digital filtering in a communication unit is described. The method includes the step of providing a sequence of delay registers, Z-D (where D > 1) in a forward path of an infinite impulse response digital filter.

In this manner, it is now possible to implement, say, an IIR filter that can provide extra delays (in a similar manner to a FIR structure) without changing or affecting the transfer response of the filter, for example with regard to an alternative filtering path that incorporates an FIR structure. It is noteworthy that in prior art IIR filter designs; D has always been equal to 1.

Brief Description of the Drawings Exemplary embodiments of the present invention will now be described, with reference to the accompanying drawings, in which: FIG. 1 shows a schematic diagram of a prior art finite impulse response filter (FIR) that is pipelined.

FIG. 2 shows a schematic block diagram of a prior art transposed direct form II infinite impulse response (IIR) digital filter.

FIG. 3 shows a block diagram of a communication system that can be adapted to support the various inventive concepts of a preferred embodiment of the present invention.

FIG. 4 shows a block diagram of a communication unit that can be adapted to support the various inventive concepts of a preferred embodiment of the present invention.

FIG. 5 shows a block diagram of a baseband processing operation of a communication unit adapted to support the various inventive concepts of a preferred embodiment of the present invention.

FIG. 6 shows an infinite impulse response (IIR) filter adapted to support the various inventive concepts of a preferred embodiment of the present invention.

FIG. 7 shows an alternative infinite impulse response (IIR) filter adapted to support the various inventive concepts of a preferred embodiment of the present invention.

Description of Preferred Embodiments Referring now to FIG. 3, a multi-rate cellular-based telephone communication system 300 is shown in outline, in accordance with a preferred embodiment of the invention. Preferably, the cellular-based telephone communication system 300 is compliant with, and cpntains network elements capable of operating over, a UMTS airinterface. In particular, the invention relates to the Third Generation Partnership Project (3GPP) specification for wide-band code-division multiple access (WCDMA) standard relating to the UTRAN radio Interface (described in the 3G TS 25. xxx series of specifications).

A plurality of subscriber terminals (or user equipment (UE) in UMTS nomenclature) 312,314, 316 communicate over radio links 318,319, 320 with a plurality of base transceiver stations, referred to under UMTS terminology as Node-Bs, 322,324, 326,328, 330,332. The system comprises many other UEs and Node Bs, which for clarity purposes are not shown.

The wireless communication system, sometimes referred to as a Network Operator's Network Domain, is connected to

an external network 334, for example the Internet. The Network Operator's Network Domain includes: (i) A core network, namely at least one Gateway GPRS Support Node (GGSN) 344 and or at least one Serving GPRS Support Nodes (SGSN) ; and (ii) An access network, namely: (ai) a GPRS (or UMTS) Radio network controller (RNC) 336-340; or (aii) Base Site Controller (BSC) in a GSM system and/or (bi) a GPRS (or UMTS) Node B 322-332; or (bii) a Base Transceiver Station (BTS) in a GSM system.

The GGSN/SGSN 344 is responsible for GPRS (or UMTS) interfacing with a Public Switched Data Network (PSDN) such as the Internet 334 or a Public Switched Telephone Network (PSTN) 334. A SGSN 344 performs a routing and tunnelling function for traffic within say, a GPRS core network, whilst a GGSN 344 links to external packet networks, in this case ones accessing the GPRS mode of the system The Node-Bs 322-332 are connected to external networks, through base station controllers, referred to under UMTS terminology as Radio Network Controller stations (RNC), including the RNCs 336,338, 340 and mobile switching centres (MSCs), such as MSC 342 (the others are, for clarity purposes, not shown) and SGSN 344 (the others are, for clarity purposes, not shown).

Each Node-B 322-332 contains one or more transceiver units and communicates with the rest of the cell-based system infrastructure via an IUb interface, as defined in the UMTS specification.

Each RNC 336-340 may control one or more Node-Bs 322-332.

Each MSC 342 provides a gateway to the external network 334. The Operations and Management Centre (OMC) 346 is operably connected to RNCs 336-340 and Node-Bs 322-332 (shown only with respect to Node-B 326 for clarity). The OMC 346 administers and manages sections of the cellular telephone communication system 300, as is understood by those skilled in the art.

In the preferred embodiment of the invention, at least one UE 312-316 and at least one Node-B 322-332 have been adapted, to offer, and provide for, transmission, reception and processing of multi-rate high-speed signals generated in accordance with the approach detailed below, particularly with respect to FIGs 4-6.

More particularly, in this embodiment the above elements have been adapted to implement the present invention in both transmitting and receiving modes of operation, such that in this embodiment the invention may be applied to both down-link and up-link transmissions.

It is also within the contemplation of the invention that such adaptation of the physical layer (air-interface) elements may alternatively be controlled, implemented in

full or implemented in part by adapting any other suitable part of the communication system 300. For example, equivalent parts in other types of systems may, in some circumstances, be adapted to provide some or all of the digital filtering implementation provided in this embodiment.

Further, in the case of other network infrastructures, implementation of the processing operations may be performed at any appropriate node such as any other appropriate type of base station, base station controller, etc.

Alternatively the aforementioned digital filtering operations may be carried out by various components distributed at different locations or entities within any suitable network or system.

Although the preferred embodiment of the invention is described with reference to a wireless communication system employing a UMTS air-interface, it is within the contemplation of the invention that the inventive concepts described herein can be applied to any multibandwidth/multi-data rate communication system-fixed or wireless.

Referring now to FIG. 4, a block diagram of a communication unit, for example user equipment (UE) 312, adapted to support the inventive concepts of the preferred embodiments of the present invention, is shown.

However, it is within the contemplation of the invention

that a similar block diagram would apply to a Node B element, say Node B 322. Therefore the foregoing description of FIG. 4 is described such that it also encompasses an implementation of a Node B baseband processing circuit, in broad principle, as would be appreciated by a person skilled in the art.

The UE 312 contains an antenna 402 preferably coupled to a duplex filter or circulator or switch 404 that provides isolation between receive and transmit chains within UE 312.

The receiver chain includes scanning receiver front-end circuitry 406 (effectively providing reception, filtering and intermediate or baseband frequency conversion). The scanning front-end circuit 406 scans signal transmissions from its associated Node B. The scanning front-end circuit 406 is serially coupled to a signal processing function (processor, generally realised by a DSP) 408.

The final receiver circuits are a baseband back-end circuit 409 operably coupled to a display unit 410, if the communication unit is a subscriber unit.

Alternatively, if the communication unit is a Node B, the final receiver circuits are a baseband back-end circuit 409 operably coupled to an interface port 410, in order to forward the demodulated received signal to, say, a PC or a RNC.

In accordance with a preferred embodiment of the invention, the receiver chain 410, in particular the

signal processing function 408, coupled to the scanning baseband back-end circuit 409, has been adapted for a receiving communication unit to receive and process multiple, high-speed signals of varying bandwidths.

A controller 414 is operably coupled to the scanning front-end circuitry 406 so that the receiver can calculate receive bit-error-rate (BER) or frame-errorrate (FER) or similar link-quality measurement data from recovered information via a received signal strength indication (RSSI) 412 function. The RSSI 412 function is operably coupled to the scanning front-end circuit 406.

The memory device 416 stores a wide array of UE-specific data, such as decoding/encoding functions, timing details, neighbour and serving cell information relating to timing, channels, power control and the like, as well as link quality measurement information to enable an optimal communication link to be selected.

A timer 418 is operably coupled to the controller 414 to control the timing of operations, namely the transmission or reception of time-dependent signals, within the UE 312.

In the context of the preferred embodiment of the present invention, timer 418 is used to synchronize the timing of the receiving communication unit 400 to be able to switch between two or more filtering paths, as described below, as well as co-ordinate appropriate clocking of signals throughout the receiver.

For completeness, in broad terms, the transmit chain of the communication unit (either a UE or Node B) essentially includes an input device 420, coupled in series through a processor 408, transmitter/modulation circuitry 422 and a power amplifier 424. The processor 408, transmitter/modulation circuitry 422 and the power amplifier 424 are operationally responsive to the controller, with an output from the power amplifier coupled to the duplex filter or circulator 404, as known in the art.

The signal processor function 408 in the transmit chain may be implemented as distinct from the processor in the receive chain. Alternatively, a single processor 408 may be used to implement processing of both transmit and receive signals, as shown in FIG. 4.

Of course, the various components within the communication unit 400 can be realised in discrete or integrated component form, with an ultimate structure therefore being merely an arbitrary selection.

More generally, the digital filtering algorithms associated with the preferred embodiment of the present invention may be implemented in a respective communication unit in any suitable manner. For example, new apparatus may be added to a conventional communication unit (for example UE 312, or Node B 322), or alternatively existing parts of a conventional communication unit may be adapted, for example by

reprogramming one or more processors therein. As such the required adaptation may be implemented in the form of processor-implementable instructions stored on a storage medium, such as a floppy disk, hard disk, PROM, RAM or any combination of these or other storage multimedia.

Referring now to FIG. 5, a block diagram of a baseband processing operation of a communication unit adapted to support the various inventive concepts of a preferred embodiment of the present invention is shown. In particular, FIG. 5 shows a more detailed block diagram of the baseband processing circuitry 409 of FIG. 4.

In accordance with the preferred embodiment of the present invention the baseband processing circuit 409 is capable of receiving one of two or more high-speed data signals (for example, a CDMA or spread spectrum signal), from a transmitting communication unit-be it a UE 312 or Node B 322.

The high-speed data signals are first input to a low-pass analogue anti-alias filter 502. The low-pass filter 502 is designed to reject baseband signals (or noise) of frequencies in excess of the fastest data signal to be received. The analogue filtered signal is then converted into digital form by analogue-to-digital (A/D) converter 504. The conversion process is controlled by processor/controller 560. In the preferred embodiment of the present invention, processor 408 and/or controller

414 of FIG. 4 perform this clock/bandwidth controlling operation.

Theoretically, a number of different FIR filters could be utilized. However, in practice, such a solution would significantly impact the cost and processing requirements of the digital filter.

Thus, the inventor of the present invention has recognised that it is most economical to switch the operating bandwidth (effectively adjust the sampling clock rate) of the main channel selection digital filter (the fixed FIR filter 540 in this example). In accordance with the preferred embodiment of the present invention, a new digital filter arrangement 512 is provided. The new digital filter arrangement 512 is effectively a rate converter, designed to handle multiple signal chip (data)-rates.

The preferred embodiment of the present invention is shown with two example data (chip) rates of 3.84 Mcps (Mega chip per second) and 7.68 Mcps. The anti-alias filter 502, together with the fixed FIR filter 540 are designed for optimal performance with any signals at a rate of 7.68 Mcps. At this rate, the (fixed) channel selection FIR filter 540 in conjunction with the analogue anti-alias filter provides adequate filtering. Hence, for signals at this higher rate of 7.68 Mcps, the direct connection route inside the new digital filter arrangement 510 is selected by the processor/controller 560.

However, for any other lower chip-rate signals, such as those at say, 3.84 Mcps, the fixed FIR filter 540 can still provide the desired channel filtering, providing it is clocked at the new rate (the filtering bandwidth of a fixed FIR filter is always relative to its sample frequency), i. e. the frequency response can be scaled/varied by adjusting the clock rate applied to the fixed FIR filter 540. However, now that the fixed FIR filter 540 is being clocked at a different rate to the A/D converter 504 a rate converter function is required.

It is noteworthy that the clock for the A/D converter is maintained at the highest rate to avoid changing the analogue anti-alias filter. In general rate conversion can be achieved by a cascade of a low-pass filter and a sample selector which selectively'drops'samples from the data stream such that the output sample stream contains the correct number of samples per second. Such a procedure is known to one skilled in the art.

However, the rate conversion in the preferred embodiment of the present invention is realised by a generic cascade of an FIR filter 520, an IIR filter 522 and sample selection function 524. In the preferred embodiment of the invention, the sample selection function 524 is a decimator unit, for example suitable for use in a receiver arrangement. However, it is within the contemplation of the invention that the sample selection function 524 may be an interpolation unit, for example suitable for use in a transmitter arrangement.

As will be discussed below, particularly with respect to FIG. 6, the design of this IIR filter 522 and the associated FIR filter 520 is critical, as these functions have to operate at the highest sample rate.

Finally, the output from the digital filter arrangement is input to the fixed (rate-selectable) FIR filter 540.

The fixed FIR filter 540 is preferably a low pass design of a relatively long length to provide a sharp cut-off to reject any signals of a frequency in excess of the data rate being received. As such, in order to handle multiple data-rate signals, the cut-off frequency of the selectable fixed FIR filter 540 is preferably controlled by processor/controller 560. Often the characteristics of the FIR filter 540 are pre-defined by the standards of the communication system being implemented.

The filtered output from the fixed FIR filter 540 is then digitally demodulated 550 and either coupled to the say, the UE's display or, if the unit is a Node B, to a radio network controller (RNC) for linking to an Internet or Intranet.

To clarify the design and operation of the IIR filter 522 in the digital filter arrangement, let us first consider the mathematical formulae associated with the filter design. Starting with a conventional IIR filter, such as illustrated in FIG. 2, the IIR filter has the transfer function as illustrated in Equation [3].

Factorizing the denominator gives the pole locations shown in Equation [4].

Thus, there are n poles and their locations are z = pi, P2 ... pn. Additional delay elements can be inserted into the structure by replacing each 'with z"D 630 where D represents the total number of delay elements required and is greater than 1. Assuming the coefficients a1 remain unchanged, this transformation gives a new function H2 (Z) of Equation [5].

Factorising this function gives Equation [6].

The poles of H2 are given by z = 7P-'-Each D

root gives D possible poles ; therefore the total number of poles in this transfer function is nD. Thus, the

poles, PI, i, of Hi and the poles, P2, of the transformed transfer function H2 are related by Equation [7].

It is now possible to design a new transfer function H1' which, when transformed to H2', has n of its nD poles in the original desired locations, i. e. the location given by Pl, from Hl. This can be achieved by taking the original desired pole locations pu,,, and mapping them to n new locations using Equation [7] to give a transfer function Hl', as shown in Equation [8].

Expanding Equation [8] gives a new set of coefficients ai', as shown in Equation [9].

This transfer function can now be transformed to H2'by substituting z=z to provide Equation [10], where D is greater than 1. It is noteworthy that in prior art IIR filter designs; D has always been equal to 1, as adapting the delay has caused a consequential effect on the IIR filter's transfer response. In the preferred embodiment of the invention, D is preferably equal to 2 or 3, noting

that increases in D cause a corresponding exponential increase in the size of the filter.

This new transfer function has n of its poles in the desired locations. However, it also has n(D-1) undesired poles which are present due to the increased order of Equation [10]. These poles need to be cancelled by zeros placed in the same location, provided by the FIR filter 520. Hence the overall transfer function needs n (D-1) + 1 coefficients on the numerator, as shown in Equation

[11].

Thus, in summary, in order to maintain the same transfer function whilst increasing the throughput of the IIR filter, a new form of IIR filter 522 is required, as shown in FIG. 6.

The delay registers z's are replaced by new delay registers z'630 where D is greater than 1. In order to maintain the same transfer function, the coefficient or multiplier functions an through a1 620 etc. are modified as illustrated by the primes and in accordance with Equations [9] and [10] to place the poles in their

original desired location. Such a modification of the coefficient or multiplier functions an through al 620 negates the need to provide a number of distinct IIR filters, optimised to perform at the different chip (data) rates processed by the communication unit.

In some cases, as illustrated in FIG. 6, merely inserting new z-D delays 630 is sufficient to provide the enhanced design and maintain the same transfer response.

However, if by computer simulation the filter characteristics of the changed coefficient multipliers a' provide too slow a data rate,"A"type delay elements can be used to pipeline the multiply blocks. Thus, as highlighted in FIG. 7, here an additional final delay - (D-A)-A register output z 710 is added and a Z delay 720- 740 is inserted in each feedback path for all of the multipliers. This z-A delay 720-740 is a redistribution of the original delay Z-D 630 and is not, in effect, an extra delay.

Finally, as indicated by the numerator of Equation [11], several undesired poles are created by the filter of FIG.

6. These are cancelled by the associated FIR filter 520, illustrated in FIG. 5.

The IIR filter can be any characteristic provided it meets the low-pass requirements of the decimator function and the phase response is within the bounds required by the communication system being implemented.

In summary, an improved IIR type recursive filter has been effectively'pipelined'without changing its transfer characteristic. In addition, such a filter is shown as being particularly advantageous in the context of a digital wireless communication system with a digital-to-analogue converter that operates over at least a pair of different bandwidths, in combination with a switchable FIR filter. From a functional point-of-view, the IIR filter 522 and its associated FIR filter 520 has a shorter length compared to the long length of the second, main channel selection low-pass fixed FIR filter 540 and acts effectively as an analogue filter for the bandwidths less than the highest bandwidth signals that are addressed by the filter arrangement.

It will be understood that the filtering arrangement as described above provides at least the following advantages: (i) it is now possible to implement an IIR filter in a digital filtering arrangement that can provide extra delays (in a similar manner to a FIR structure) without changing or affecting the transfer response of the digital filtering arrangement.

(ii) The use of such a digital filter arrangement in multi-bandwidth communication units and systems

allows multiple bandwidths to be filtered in a more efficient and cost effective manner.

(iii) The use of such a digital filter arrangement in multi-bandwidth communication units supporting bandwidth factors not restricted to integer powers of 2 where efficient FIR filters (such as half- band filters) are not applicable.

(iv) The use of an IIR filter incorporating extra delays to effect an increase the maximum operating speed of such an IIR filter in any given digital technology.

Thus, an improved filtering process has been described.

In particular the improved filtering process allows additional delays to be incorporated into a digital filter structure without changing its transfer function thereby maintaining its transfer response. The improved filtering process offers advantages in multi-rate radio communication systems, wherein the aforementioned disadvantages associated with prior art filters and systems have been substantially alleviated.

Claims

Claims 1. A method for digital filtering in a communication unit, the method comprising the step of: providing a sequence of delay registers, Z-D in a forward path of an infinite impulse response digital filter arrangement, where D is greater than 1.
2. The method for digital filtering in a communication unit according to Claim 1, the method further comprising the step of : providing a sequence of coefficient multipliers in a feedback path of said infinite impulse response digital filter, wherein said respective coefficient multipliers

D correspond to said delay registers, Z', to maintain a particular transfer response of said infinite impulse response digital filter to effect an increase in a maximum clock rate of said digital filter arrangement.
3. The method for digital filtering in a communication unit according to Claim 2, the method further comprising the steps of: inserting delay registers according to Z(D-A) in replacement of Z ; and further inserting a delay of Z'in each feedback path for all multipliers to redistribute delay if said coefficient multipliers provide too slow a data rate.

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4. The method for digital filtering in a communication unit according to any preceding Claim, wherein the first data rate is a highest data rate to be filtered by said digital filter arrangement and said second data rate is lower than said first data rate.
5. The method for digital filtering in a communication unit according to any preceding Claim, the method further comprising the step of: cascading a finite impulse response digital filter in series with said infinite impulse response digital filter to eliminate aliases due to the provision of Z delays.
6. The method for digital filtering in a communication unit according to Claim 5, wherein said step of cascading a finite impulse response digital filter in series with said infinite impulse response digital filter forms a rate converter.
7. The method for digital filtering in a communication unit according to Claim 5 or Claim 6, the method further comprising the steps of: providing an analogue to digital converter operably coupled to a fixed finite impulse response digital filter via said rate converter in a first signal path, and operably coupled to said fixed finite impulse response digital filter without being coupled to said rate converter in a second signal path; and

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switching between said first and second signal paths to accommodate respective first and second signal data rates being processed in said communication unit.
8. The method for digital filtering in a communication unit according to Claim 7, wherein said fixed finite impulse response digital filter has a frequency response that is scalable in response to a variable clock rate applied to said fixed finite impulse response digital filter.
9. The method for digital filtering in a communication unit according to Claim 7, the method further comprising the step of: incorporating a decimator function in said rate converter to adjust a clock rate of said rate converter to a clock rate of said fixed finite impulse response filter.
10. The method for digital filtering in a communication unit according to any of Claims 7 to 9, wherein said second signal path corresponds respectively to a higher chip rate of substantially 7.68 Mcps and said first signal path corresponds respectively to a predetermined chip rate of substantially 3.84 Mcps.
11. The method for digital filtering in a communication unit according to any of Claims 7 to 10, the method further comprising the step of:

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providing further a parallel series of infinite impulse response digital filters to accommodate a series of respective signal data rates.
12. The method for digital filtering in a communication unit according to any of Claims 1 to 10, the method further comprising the step of : providing a series of adaptable multiplier coefficients in said infinite impulse response digital filter to accommodate a series of respective signal data rates.
13. A storage medium storing processor-implementable instructions adapted to control a processor to carry out the method of any of claims 1 to 12.

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14. An infinite impulse response digital filter comprising a sequence of delay registers, Z-D in a forward path of said digital filter arrangement, where D is greater than 1.
15. The infinite impulse response digital filter according to Claim 14, the infinite impulse response digital filter further comprising a sequence of coefficient multipliers in a feedback path of said

digital filter, wherein said respective coefficient n multipliers correspond to said delay registers, Z", to maintain a particular transfer response of said digital filter arrangement.
16. The infinite impulse response digital filter according to Claim 15, wherein the infinite impulse response digital filter comprises a sequence of Z

D delay registers in place of Z', in conjunction with a delay of Z'in each feedback path for all multipliers to redistribute delay if said coefficient multipliers provide too slow a data rate.

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17. A digital filter arrangement for use in a communication system having at least two radio frequency operating bandwidths, the digital filter arrangement comprising: a first filtering path incorporating an analogueto-digital converter directly coupled to a fixed finite impulse response filter arranged to provide desired channel selective filtering at a highest of the at least two radio frequency operating bandwidths; and a second filtering path incorporating said analogue-to-digital converter being coupled to said fixed finite impulse response filter via an infinite impulse

D response filter having a sequence of delay registers, Z- in a forward path of a said infinite impulse response filter, where D is greater than or equal to 1.
18. The digital filter arrangement according to Claim 17, the infinite impulse response filter of the digital filter arrangement further comprising coefficient multipliers in a feedback path of said infinite impulse response filter where the coefficient D and said multiplier are selected to maintain a desired transfer response at said lower operating bandwidth.
19. The digital filter arrangement according to Claim 17 or Claim 18, the digital filter arrangement further comprising a switch for switching an operation of the digital filter arrangement between said first and second filtering paths dependent upon the data rate of a signal to be processed.

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20. The digital filter arrangement according to Claim 19, further comprising a processor operably coupled to said switch and said fixed finite impulse response filter to control a clock rate of operation thereof.
21. A digital filter arrangement according to Claim 20, wherein said fixed finite impulse response filter has a frequency response that is scalable in response to a variable clock rate provided by said processor.
22. A digital filter arrangement according to any of Claims 17 to 21, the digital filter arrangement further comprising a second finite impulse response digital filter cascaded with said infinite impulse response filter to remove the additional poles due to the inclusion of the Z-D delay elements.
23. A digital filter arrangement according to any of Claims 18 to 22, wherein a final 'D delay is replaced by z delay and Z delays are inserted in each feedback path to be operably coupled to the respective multipliers, if said coefficient multipliers provide too slow a data rate.
24. A communication system adapted to facilitate the performance of any of the method steps of claims 1 to 12 or to encompass the infinite impulse response digital filter of any of Claims 14 to 16 or digital filter arrangement of any of Claim 17 to 23.

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25. The communication system according to claim 24, wherein the communication system is a UMTS communication system.
26. The communication system according to claim 24 or Claim 25, wherein the communication system provides for operation over multiple data rates by enabling a communication unit operating in said communication system to be adapted to perform any of the steps of method Claims 1 to 12 or to encompass the infinite impulse response digital filter of any of Claims 14 to 16 or digital filter arrangement of any of Claim 17 to 23.
27. A communication unit adapted to perform any of the method steps of claims 1 to 12 or to encompass the infinite impulse response digital filter of any of Claims 14 to 16 or digital filter arrangement of any of Claim 17 to 23.
28. The communication unit according to claim 27, wherein the communication unit is one of: a user equipment, Node B.
29. A method of filtering, substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 5 or FIG. 6 of the accompanying drawings.
30. A digital filter arrangement substantially as hereinbefore described with reference to, and/or as

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illustrated by, FIG. 5 or FIG. 6 of the accompanying drawings.
31. User equipment, for use in a high capacity digital wireless communications system, substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 4 of the accompanying drawings.
32. A node B, for use in a high capacity digital wireless communications system, substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 4 of the accompanying drawings.
33. A high capacity digital wireless communications system substantially as hereinbefore described with reference to, and/or as illustrated by, FIG. 3 of the accompanying drawings.